2 * arch/arm/plat-omap/include/mach/dmtimer.h
4 * OMAP Dual-Mode Timers
6 * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
7 * Tarun Kanti DebBarma <tarun.kanti@ti.com>
8 * Thara Gopinath <thara@ti.com>
10 * Platform device conversion and hwmod support.
12 * Copyright (C) 2005 Nokia Corporation
13 * Author: Lauri Leukkunen <lauri.leukkunen@nokia.com>
14 * PWM and clock framwork support by Timo Teras.
16 * This program is free software; you can redistribute it and/or modify it
17 * under the terms of the GNU General Public License as published by the
18 * Free Software Foundation; either version 2 of the License, or (at your
19 * option) any later version.
21 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
22 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
23 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
24 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
26 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
28 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
30 * You should have received a copy of the GNU General Public License along
31 * with this program; if not, write to the Free Software Foundation, Inc.,
32 * 675 Mass Ave, Cambridge, MA 02139, USA.
35 #include <linux/clk.h>
36 #include <linux/delay.h>
38 #ifndef __ASM_ARCH_DMTIMER_H
39 #define __ASM_ARCH_DMTIMER_H
42 #define OMAP_TIMER_SRC_SYS_CLK 0x00
43 #define OMAP_TIMER_SRC_32_KHZ 0x01
44 #define OMAP_TIMER_SRC_EXT_CLK 0x02
46 /* timer interrupt enable bits */
47 #define OMAP_TIMER_INT_CAPTURE (1 << 2)
48 #define OMAP_TIMER_INT_OVERFLOW (1 << 1)
49 #define OMAP_TIMER_INT_MATCH (1 << 0)
52 #define OMAP_TIMER_TRIGGER_NONE 0x00
53 #define OMAP_TIMER_TRIGGER_OVERFLOW 0x01
54 #define OMAP_TIMER_TRIGGER_OVERFLOW_AND_COMPARE 0x02
57 * IP revision identifier so that Highlander IP
58 * in OMAP4 can be distinguished.
60 #define OMAP_TIMER_IP_VERSION_1 0x1
64 int omap_dm_timer_init(void);
66 struct omap_dm_timer *omap_dm_timer_request(void);
67 struct omap_dm_timer *omap_dm_timer_request_specific(int timer_id);
68 void omap_dm_timer_free(struct omap_dm_timer *timer);
69 void omap_dm_timer_enable(struct omap_dm_timer *timer);
70 void omap_dm_timer_disable(struct omap_dm_timer *timer);
72 int omap_dm_timer_get_irq(struct omap_dm_timer *timer);
74 u32 omap_dm_timer_modify_idlect_mask(u32 inputmask);
75 struct clk *omap_dm_timer_get_fclk(struct omap_dm_timer *timer);
77 void omap_dm_timer_trigger(struct omap_dm_timer *timer);
78 void omap_dm_timer_start(struct omap_dm_timer *timer);
79 void omap_dm_timer_stop(struct omap_dm_timer *timer);
81 int omap_dm_timer_set_source(struct omap_dm_timer *timer, int source);
82 void omap_dm_timer_set_load(struct omap_dm_timer *timer, int autoreload, unsigned int value);
83 void omap_dm_timer_set_load_start(struct omap_dm_timer *timer, int autoreload, unsigned int value);
84 void omap_dm_timer_set_match(struct omap_dm_timer *timer, int enable, unsigned int match);
85 void omap_dm_timer_set_pwm(struct omap_dm_timer *timer, int def_on, int toggle, int trigger);
86 void omap_dm_timer_set_prescaler(struct omap_dm_timer *timer, int prescaler);
88 void omap_dm_timer_set_int_enable(struct omap_dm_timer *timer, unsigned int value);
90 unsigned int omap_dm_timer_read_status(struct omap_dm_timer *timer);
91 void omap_dm_timer_write_status(struct omap_dm_timer *timer, unsigned int value);
92 unsigned int omap_dm_timer_read_counter(struct omap_dm_timer *timer);
93 void omap_dm_timer_write_counter(struct omap_dm_timer *timer, unsigned int value);
95 int omap_dm_timers_active(void);
98 * Do not use the defines below, they are not needed. They should be only
99 * used by dmtimer.c and sys_timer related code.
102 /* register offsets */
103 #define _OMAP_TIMER_ID_OFFSET 0x00
104 #define _OMAP_TIMER_OCP_CFG_OFFSET 0x10
105 #define _OMAP_TIMER_SYS_STAT_OFFSET 0x14
106 #define _OMAP_TIMER_STAT_OFFSET 0x18
107 #define _OMAP_TIMER_INT_EN_OFFSET 0x1c
108 #define _OMAP_TIMER_WAKEUP_EN_OFFSET 0x20
109 #define _OMAP_TIMER_CTRL_OFFSET 0x24
110 #define OMAP_TIMER_CTRL_GPOCFG (1 << 14)
111 #define OMAP_TIMER_CTRL_CAPTMODE (1 << 13)
112 #define OMAP_TIMER_CTRL_PT (1 << 12)
113 #define OMAP_TIMER_CTRL_TCM_LOWTOHIGH (0x1 << 8)
114 #define OMAP_TIMER_CTRL_TCM_HIGHTOLOW (0x2 << 8)
115 #define OMAP_TIMER_CTRL_TCM_BOTHEDGES (0x3 << 8)
116 #define OMAP_TIMER_CTRL_SCPWM (1 << 7)
117 #define OMAP_TIMER_CTRL_CE (1 << 6) /* compare enable */
118 #define OMAP_TIMER_CTRL_PRE (1 << 5) /* prescaler enable */
119 #define OMAP_TIMER_CTRL_PTV_SHIFT 2 /* prescaler value shift */
120 #define OMAP_TIMER_CTRL_POSTED (1 << 2)
121 #define OMAP_TIMER_CTRL_AR (1 << 1) /* auto-reload enable */
122 #define OMAP_TIMER_CTRL_ST (1 << 0) /* start timer */
123 #define _OMAP_TIMER_COUNTER_OFFSET 0x28
124 #define _OMAP_TIMER_LOAD_OFFSET 0x2c
125 #define _OMAP_TIMER_TRIGGER_OFFSET 0x30
126 #define _OMAP_TIMER_WRITE_PEND_OFFSET 0x34
127 #define WP_NONE 0 /* no write pending bit */
128 #define WP_TCLR (1 << 0)
129 #define WP_TCRR (1 << 1)
130 #define WP_TLDR (1 << 2)
131 #define WP_TTGR (1 << 3)
132 #define WP_TMAR (1 << 4)
133 #define WP_TPIR (1 << 5)
134 #define WP_TNIR (1 << 6)
135 #define WP_TCVR (1 << 7)
136 #define WP_TOCR (1 << 8)
137 #define WP_TOWR (1 << 9)
138 #define _OMAP_TIMER_MATCH_OFFSET 0x38
139 #define _OMAP_TIMER_CAPTURE_OFFSET 0x3c
140 #define _OMAP_TIMER_IF_CTRL_OFFSET 0x40
141 #define _OMAP_TIMER_CAPTURE2_OFFSET 0x44 /* TCAR2, 34xx only */
142 #define _OMAP_TIMER_TICK_POS_OFFSET 0x48 /* TPIR, 34xx only */
143 #define _OMAP_TIMER_TICK_NEG_OFFSET 0x4c /* TNIR, 34xx only */
144 #define _OMAP_TIMER_TICK_COUNT_OFFSET 0x50 /* TCVR, 34xx only */
145 #define _OMAP_TIMER_TICK_INT_MASK_SET_OFFSET 0x54 /* TOCR, 34xx only */
146 #define _OMAP_TIMER_TICK_INT_MASK_COUNT_OFFSET 0x58 /* TOWR, 34xx only */
148 /* register offsets with the write pending bit encoded */
151 #define OMAP_TIMER_ID_REG (_OMAP_TIMER_ID_OFFSET \
152 | (WP_NONE << WPSHIFT))
154 #define OMAP_TIMER_OCP_CFG_REG (_OMAP_TIMER_OCP_CFG_OFFSET \
155 | (WP_NONE << WPSHIFT))
157 #define OMAP_TIMER_SYS_STAT_REG (_OMAP_TIMER_SYS_STAT_OFFSET \
158 | (WP_NONE << WPSHIFT))
160 #define OMAP_TIMER_STAT_REG (_OMAP_TIMER_STAT_OFFSET \
161 | (WP_NONE << WPSHIFT))
163 #define OMAP_TIMER_INT_EN_REG (_OMAP_TIMER_INT_EN_OFFSET \
164 | (WP_NONE << WPSHIFT))
166 #define OMAP_TIMER_WAKEUP_EN_REG (_OMAP_TIMER_WAKEUP_EN_OFFSET \
167 | (WP_NONE << WPSHIFT))
169 #define OMAP_TIMER_CTRL_REG (_OMAP_TIMER_CTRL_OFFSET \
170 | (WP_TCLR << WPSHIFT))
172 #define OMAP_TIMER_COUNTER_REG (_OMAP_TIMER_COUNTER_OFFSET \
173 | (WP_TCRR << WPSHIFT))
175 #define OMAP_TIMER_LOAD_REG (_OMAP_TIMER_LOAD_OFFSET \
176 | (WP_TLDR << WPSHIFT))
178 #define OMAP_TIMER_TRIGGER_REG (_OMAP_TIMER_TRIGGER_OFFSET \
179 | (WP_TTGR << WPSHIFT))
181 #define OMAP_TIMER_WRITE_PEND_REG (_OMAP_TIMER_WRITE_PEND_OFFSET \
182 | (WP_NONE << WPSHIFT))
184 #define OMAP_TIMER_MATCH_REG (_OMAP_TIMER_MATCH_OFFSET \
185 | (WP_TMAR << WPSHIFT))
187 #define OMAP_TIMER_CAPTURE_REG (_OMAP_TIMER_CAPTURE_OFFSET \
188 | (WP_NONE << WPSHIFT))
190 #define OMAP_TIMER_IF_CTRL_REG (_OMAP_TIMER_IF_CTRL_OFFSET \
191 | (WP_NONE << WPSHIFT))
193 #define OMAP_TIMER_CAPTURE2_REG (_OMAP_TIMER_CAPTURE2_OFFSET \
194 | (WP_NONE << WPSHIFT))
196 #define OMAP_TIMER_TICK_POS_REG (_OMAP_TIMER_TICK_POS_OFFSET \
197 | (WP_TPIR << WPSHIFT))
199 #define OMAP_TIMER_TICK_NEG_REG (_OMAP_TIMER_TICK_NEG_OFFSET \
200 | (WP_TNIR << WPSHIFT))
202 #define OMAP_TIMER_TICK_COUNT_REG (_OMAP_TIMER_TICK_COUNT_OFFSET \
203 | (WP_TCVR << WPSHIFT))
205 #define OMAP_TIMER_TICK_INT_MASK_SET_REG \
206 (_OMAP_TIMER_TICK_INT_MASK_SET_OFFSET | (WP_TOCR << WPSHIFT))
208 #define OMAP_TIMER_TICK_INT_MASK_COUNT_REG \
209 (_OMAP_TIMER_TICK_INT_MASK_COUNT_OFFSET | (WP_TOWR << WPSHIFT))
211 struct omap_dm_timer {
212 unsigned long phys_base;
214 #ifdef CONFIG_ARCH_OMAP2PLUS
215 struct clk *iclk, *fclk;
217 void __iomem *io_base;
224 void omap_dm_timer_prepare(struct omap_dm_timer *timer);
226 static inline u32 __omap_dm_timer_read(void __iomem *base, u32 reg,
230 while (__raw_readl(base + (OMAP_TIMER_WRITE_PEND_REG & 0xff))
234 return __raw_readl(base + (reg & 0xff));
237 static inline void __omap_dm_timer_write(void __iomem *base, u32 reg, u32 val,
241 while (__raw_readl(base + (OMAP_TIMER_WRITE_PEND_REG & 0xff))
245 __raw_writel(val, base + (reg & 0xff));
248 /* Assumes the source clock has been set by caller */
249 static inline void __omap_dm_timer_reset(void __iomem *base, int autoidle,
254 l = __omap_dm_timer_read(base, OMAP_TIMER_OCP_CFG_REG, 0);
255 l |= 0x02 << 3; /* Set to smart-idle mode */
256 l |= 0x2 << 8; /* Set clock activity to perserve f-clock on idle */
264 __omap_dm_timer_write(base, OMAP_TIMER_OCP_CFG_REG, l, 0);
266 /* Match hardware reset default of posted mode */
267 __omap_dm_timer_write(base, OMAP_TIMER_IF_CTRL_REG,
268 OMAP_TIMER_CTRL_POSTED, 0);
271 static inline int __omap_dm_timer_set_source(struct clk *timer_fck,
276 clk_disable(timer_fck);
277 ret = clk_set_parent(timer_fck, parent);
278 clk_enable(timer_fck);
281 * When the functional clock disappears, too quick writes seem
282 * to cause an abort. XXX Is this still necessary?
289 static inline void __omap_dm_timer_stop(void __iomem *base, int posted,
294 l = __omap_dm_timer_read(base, OMAP_TIMER_CTRL_REG, posted);
295 if (l & OMAP_TIMER_CTRL_ST) {
297 __omap_dm_timer_write(base, OMAP_TIMER_CTRL_REG, l, posted);
298 #ifdef CONFIG_ARCH_OMAP2PLUS
299 /* Readback to make sure write has completed */
300 __omap_dm_timer_read(base, OMAP_TIMER_CTRL_REG, posted);
302 * Wait for functional clock period x 3.5 to make sure that
305 udelay(3500000 / rate + 1);
309 /* Ack possibly pending interrupt */
310 __omap_dm_timer_write(base, OMAP_TIMER_STAT_REG,
311 OMAP_TIMER_INT_OVERFLOW, 0);
314 static inline void __omap_dm_timer_load_start(void __iomem *base, u32 ctrl,
315 unsigned int load, int posted)
317 __omap_dm_timer_write(base, OMAP_TIMER_COUNTER_REG, load, posted);
318 __omap_dm_timer_write(base, OMAP_TIMER_CTRL_REG, ctrl, posted);
321 static inline void __omap_dm_timer_int_enable(void __iomem *base,
324 __omap_dm_timer_write(base, OMAP_TIMER_INT_EN_REG, value, 0);
325 __omap_dm_timer_write(base, OMAP_TIMER_WAKEUP_EN_REG, value, 0);
328 static inline unsigned int __omap_dm_timer_read_counter(void __iomem *base,
331 return __omap_dm_timer_read(base, OMAP_TIMER_COUNTER_REG, posted);
334 static inline void __omap_dm_timer_write_status(void __iomem *base,
337 __omap_dm_timer_write(base, OMAP_TIMER_STAT_REG, value, 0);
340 #endif /* __ASM_ARCH_DMTIMER_H */