arch/arm/plat-omap/include/plat/dmtimer.h

   1 /*
   2  * arch/arm/plat-omap/include/plat/dmtimer.h
   3  *
   4  * OMAP Dual-Mode Timers
   5  *
   6  * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
   7  * Tarun Kanti DebBarma <tarun.kanti@ti.com>
   8  * Thara Gopinath <thara@ti.com>
   9  *
  10  * Platform device conversion and hwmod support.
  11  *
  12  * Copyright (C) 2005 Nokia Corporation
  13  * Author: Lauri Leukkunen <lauri.leukkunen@nokia.com>
  14  * PWM and clock framwork support by Timo Teras.
  15  *
  16  * This program is free software; you can redistribute it and/or modify it
  17  * under the terms of the GNU General Public License as published by the
  18  * Free Software Foundation; either version 2 of the License, or (at your
  19  * option) any later version.
  20  *
  21  * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
  22  * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
  23  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
  24  * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  25  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  26  * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  27  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  28  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  29  *
  30  * You should have received a copy of the  GNU General Public License along
  31  * with this program; if not, write  to the Free Software Foundation, Inc.,
  32  * 675 Mass Ave, Cambridge, MA 02139, USA.
  33  */
  34
  35 #include <linux/clk.h>
  36 #include <linux/delay.h>
  37 #include <linux/io.h>
  38 #include <linux/platform_device.h>
  39
  40 #ifndef __ASM_ARCH_DMTIMER_H
  41 #define __ASM_ARCH_DMTIMER_H
  42
  43 /* clock sources */
  44 #define OMAP_TIMER_SRC_SYS_CLK                  0x00
  45 #define OMAP_TIMER_SRC_32_KHZ                   0x01
  46 #define OMAP_TIMER_SRC_EXT_CLK                  0x02
  47
  48 /* timer interrupt enable bits */
  49 #define OMAP_TIMER_INT_CAPTURE                  (1 << 2)
  50 #define OMAP_TIMER_INT_OVERFLOW                 (1 << 1)
  51 #define OMAP_TIMER_INT_MATCH                    (1 << 0)
  52
  53 /* trigger types */
  54 #define OMAP_TIMER_TRIGGER_NONE                 0x00
  55 #define OMAP_TIMER_TRIGGER_OVERFLOW             0x01
  56 #define OMAP_TIMER_TRIGGER_OVERFLOW_AND_COMPARE 0x02
  57
  58 /*
  59  * IP revision identifier so that Highlander IP
  60  * in OMAP4 can be distinguished.
  61  */
  62 #define OMAP_TIMER_IP_VERSION_1                        0x1
  63
  64 /* timer capabilities used in hwmod database */
  65 #define OMAP_TIMER_SECURE                               0x80000000
  66 #define OMAP_TIMER_ALWON                                0x40000000
  67 #define OMAP_TIMER_HAS_PWM                              0x20000000
  68
  69 struct omap_timer_capability_dev_attr {
  70         u32 timer_capability;
  71 };
  72
  73 struct omap_dm_timer;
  74 struct clk;
  75
  76 struct timer_regs {
  77         u32 tidr;
  78         u32 tistat;
  79         u32 tisr;
  80         u32 tier;
  81         u32 twer;
  82         u32 tclr;
  83         u32 tcrr;
  84         u32 tldr;
  85         u32 ttrg;
  86         u32 twps;
  87         u32 tmar;
  88         u32 tcar1;
  89         u32 tsicr;
  90         u32 tcar2;
  91         u32 tpir;
  92         u32 tnir;
  93         u32 tcvr;
  94         u32 tocr;
  95         u32 towr;
  96 };
  97
  98 struct dmtimer_platform_data {
  99         int (*set_timer_src)(struct platform_device *pdev, int source);
 100         int timer_ip_version;
 101         u32 needs_manual_reset:1;
 102         bool reserved;
 103
 104         bool loses_context;
 105
 106         int (*get_context_loss_count)(struct device *dev);
 107 };
 108
 109 struct omap_dm_timer *omap_dm_timer_request(void);
 110 struct omap_dm_timer *omap_dm_timer_request_specific(int timer_id);
 111 int omap_dm_timer_free(struct omap_dm_timer *timer);
 112 void omap_dm_timer_enable(struct omap_dm_timer *timer);
 113 void omap_dm_timer_disable(struct omap_dm_timer *timer);
 114
 115 int omap_dm_timer_get_irq(struct omap_dm_timer *timer);
 116
 117 u32 omap_dm_timer_modify_idlect_mask(u32 inputmask);
 118 struct clk *omap_dm_timer_get_fclk(struct omap_dm_timer *timer);
 119
 120 int omap_dm_timer_trigger(struct omap_dm_timer *timer);
 121 int omap_dm_timer_start(struct omap_dm_timer *timer);
 122 int omap_dm_timer_stop(struct omap_dm_timer *timer);
 123
 124 int omap_dm_timer_set_source(struct omap_dm_timer *timer, int source);
 125 int omap_dm_timer_set_load(struct omap_dm_timer *timer, int autoreload, unsigned int value);
 126 int omap_dm_timer_set_load_start(struct omap_dm_timer *timer, int autoreload, unsigned int value);
 127 int omap_dm_timer_set_match(struct omap_dm_timer *timer, int enable, unsigned int match);
 128 int omap_dm_timer_set_pwm(struct omap_dm_timer *timer, int def_on, int toggle, int trigger);
 129 int omap_dm_timer_set_prescaler(struct omap_dm_timer *timer, int prescaler);
 130
 131 int omap_dm_timer_set_int_enable(struct omap_dm_timer *timer, unsigned int value);
 132
 133 unsigned int omap_dm_timer_read_status(struct omap_dm_timer *timer);
 134 int omap_dm_timer_write_status(struct omap_dm_timer *timer, unsigned int value);
 135 unsigned int omap_dm_timer_read_counter(struct omap_dm_timer *timer);
 136 int omap_dm_timer_write_counter(struct omap_dm_timer *timer, unsigned int value);
 137
 138 int omap_dm_timers_active(void);
 139
 140 /*
 141  * Do not use the defines below, they are not needed. They should be only
 142  * used by dmtimer.c and sys_timer related code.
 143  */
 144
 145 /*
 146  * The interrupt registers are different between v1 and v2 ip.
 147  * These registers are offsets from timer->iobase.
 148  */
 149 #define OMAP_TIMER_ID_OFFSET            0x00
 150 #define OMAP_TIMER_OCP_CFG_OFFSET       0x10
 151
 152 #define OMAP_TIMER_V1_SYS_STAT_OFFSET   0x14
 153 #define OMAP_TIMER_V1_STAT_OFFSET       0x18
 154 #define OMAP_TIMER_V1_INT_EN_OFFSET     0x1c
 155
 156 #define OMAP_TIMER_V2_IRQSTATUS_RAW     0x24
 157 #define OMAP_TIMER_V2_IRQSTATUS         0x28
 158 #define OMAP_TIMER_V2_IRQENABLE_SET     0x2c
 159 #define OMAP_TIMER_V2_IRQENABLE_CLR     0x30
 160
 161 /*
 162  * The functional registers have a different base on v1 and v2 ip.
 163  * These registers are offsets from timer->func_base. The func_base
 164  * is samae as io_base for v1 and io_base + 0x14 for v2 ip.
 165  *
 166  */
 167 #define OMAP_TIMER_V2_FUNC_OFFSET               0x14
 168
 169 #define _OMAP_TIMER_WAKEUP_EN_OFFSET    0x20
 170 #define _OMAP_TIMER_CTRL_OFFSET         0x24
 171 #define         OMAP_TIMER_CTRL_GPOCFG          (1 << 14)
 172 #define         OMAP_TIMER_CTRL_CAPTMODE        (1 << 13)
 173 #define         OMAP_TIMER_CTRL_PT              (1 << 12)
 174 #define         OMAP_TIMER_CTRL_TCM_LOWTOHIGH   (0x1 << 8)
 175 #define         OMAP_TIMER_CTRL_TCM_HIGHTOLOW   (0x2 << 8)
 176 #define         OMAP_TIMER_CTRL_TCM_BOTHEDGES   (0x3 << 8)
 177 #define         OMAP_TIMER_CTRL_SCPWM           (1 << 7)
 178 #define         OMAP_TIMER_CTRL_CE              (1 << 6) /* compare enable */
 179 #define         OMAP_TIMER_CTRL_PRE             (1 << 5) /* prescaler enable */
 180 #define         OMAP_TIMER_CTRL_PTV_SHIFT       2 /* prescaler value shift */
 181 #define         OMAP_TIMER_CTRL_POSTED          (1 << 2)
 182 #define         OMAP_TIMER_CTRL_AR              (1 << 1) /* auto-reload enable */
 183 #define         OMAP_TIMER_CTRL_ST              (1 << 0) /* start timer */
 184 #define _OMAP_TIMER_COUNTER_OFFSET      0x28
 185 #define _OMAP_TIMER_LOAD_OFFSET         0x2c
 186 #define _OMAP_TIMER_TRIGGER_OFFSET      0x30
 187 #define _OMAP_TIMER_WRITE_PEND_OFFSET   0x34
 188 #define         WP_NONE                 0       /* no write pending bit */
 189 #define         WP_TCLR                 (1 << 0)
 190 #define         WP_TCRR                 (1 << 1)
 191 #define         WP_TLDR                 (1 << 2)
 192 #define         WP_TTGR                 (1 << 3)
 193 #define         WP_TMAR                 (1 << 4)
 194 #define         WP_TPIR                 (1 << 5)
 195 #define         WP_TNIR                 (1 << 6)
 196 #define         WP_TCVR                 (1 << 7)
 197 #define         WP_TOCR                 (1 << 8)
 198 #define         WP_TOWR                 (1 << 9)
 199 #define _OMAP_TIMER_MATCH_OFFSET        0x38
 200 #define _OMAP_TIMER_CAPTURE_OFFSET      0x3c
 201 #define _OMAP_TIMER_IF_CTRL_OFFSET      0x40
 202 #define _OMAP_TIMER_CAPTURE2_OFFSET             0x44    /* TCAR2, 34xx only */
 203 #define _OMAP_TIMER_TICK_POS_OFFSET             0x48    /* TPIR, 34xx only */
 204 #define _OMAP_TIMER_TICK_NEG_OFFSET             0x4c    /* TNIR, 34xx only */
 205 #define _OMAP_TIMER_TICK_COUNT_OFFSET           0x50    /* TCVR, 34xx only */
 206 #define _OMAP_TIMER_TICK_INT_MASK_SET_OFFSET    0x54    /* TOCR, 34xx only */
 207 #define _OMAP_TIMER_TICK_INT_MASK_COUNT_OFFSET  0x58    /* TOWR, 34xx only */
 208
 209 /* register offsets with the write pending bit encoded */
 210 #define WPSHIFT                                 16
 211
 212 #define OMAP_TIMER_WAKEUP_EN_REG                (_OMAP_TIMER_WAKEUP_EN_OFFSET \
 213                                                         | (WP_NONE << WPSHIFT))
 214
 215 #define OMAP_TIMER_CTRL_REG                     (_OMAP_TIMER_CTRL_OFFSET \
 216                                                         | (WP_TCLR << WPSHIFT))
 217
 218 #define OMAP_TIMER_COUNTER_REG                  (_OMAP_TIMER_COUNTER_OFFSET \
 219                                                         | (WP_TCRR << WPSHIFT))
 220
 221 #define OMAP_TIMER_LOAD_REG                     (_OMAP_TIMER_LOAD_OFFSET \
 222                                                         | (WP_TLDR << WPSHIFT))
 223
 224 #define OMAP_TIMER_TRIGGER_REG                  (_OMAP_TIMER_TRIGGER_OFFSET \
 225                                                         | (WP_TTGR << WPSHIFT))
 226
 227 #define OMAP_TIMER_WRITE_PEND_REG               (_OMAP_TIMER_WRITE_PEND_OFFSET \
 228                                                         | (WP_NONE << WPSHIFT))
 229
 230 #define OMAP_TIMER_MATCH_REG                    (_OMAP_TIMER_MATCH_OFFSET \
 231                                                         | (WP_TMAR << WPSHIFT))
 232
 233 #define OMAP_TIMER_CAPTURE_REG                  (_OMAP_TIMER_CAPTURE_OFFSET \
 234                                                         | (WP_NONE << WPSHIFT))
 235
 236 #define OMAP_TIMER_IF_CTRL_REG                  (_OMAP_TIMER_IF_CTRL_OFFSET \
 237                                                         | (WP_NONE << WPSHIFT))
 238
 239 #define OMAP_TIMER_CAPTURE2_REG                 (_OMAP_TIMER_CAPTURE2_OFFSET \
 240                                                         | (WP_NONE << WPSHIFT))
 241
 242 #define OMAP_TIMER_TICK_POS_REG                 (_OMAP_TIMER_TICK_POS_OFFSET \
 243                                                         | (WP_TPIR << WPSHIFT))
 244
 245 #define OMAP_TIMER_TICK_NEG_REG                 (_OMAP_TIMER_TICK_NEG_OFFSET \
 246                                                         | (WP_TNIR << WPSHIFT))
 247
 248 #define OMAP_TIMER_TICK_COUNT_REG               (_OMAP_TIMER_TICK_COUNT_OFFSET \
 249                                                         | (WP_TCVR << WPSHIFT))
 250
 251 #define OMAP_TIMER_TICK_INT_MASK_SET_REG                                \
 252                 (_OMAP_TIMER_TICK_INT_MASK_SET_OFFSET | (WP_TOCR << WPSHIFT))
 253
 254 #define OMAP_TIMER_TICK_INT_MASK_COUNT_REG                              \
 255                 (_OMAP_TIMER_TICK_INT_MASK_COUNT_OFFSET | (WP_TOWR << WPSHIFT))
 256
 257 struct omap_dm_timer {
 258         unsigned long phys_base;
 259         int id;
 260         int irq;
 261         struct clk *fclk;
 262
 263         void __iomem    *io_base;
 264         void __iomem    *sys_stat;      /* TISTAT timer status */
 265         void __iomem    *irq_stat;      /* TISR/IRQSTATUS interrupt status */
 266         void __iomem    *irq_ena;       /* irq enable */
 267         void __iomem    *irq_dis;       /* irq disable, only on v2 ip */
 268         void __iomem    *pend;          /* write pending */
 269         void __iomem    *func_base;     /* function register base */
 270
 271         unsigned long rate;
 272         unsigned reserved:1;
 273         unsigned posted:1;
 274         struct timer_regs context;
 275         bool loses_context;
 276         int ctx_loss_count;
 277         int revision;
 278         struct platform_device *pdev;
 279         struct list_head node;
 280
 281         int (*get_context_loss_count)(struct device *dev);
 282 };
 283
 284 int omap_dm_timer_prepare(struct omap_dm_timer *timer);
 285
 286 static inline u32 __omap_dm_timer_read(struct omap_dm_timer *timer, u32 reg,
 287                                                 int posted)
 288 {
 289         if (posted)
 290                 while (__raw_readl(timer->pend) & (reg >> WPSHIFT))
 291                         cpu_relax();
 292
 293         return __raw_readl(timer->func_base + (reg & 0xff));
 294 }
 295
 296 static inline void __omap_dm_timer_write(struct omap_dm_timer *timer,
 297                                         u32 reg, u32 val, int posted)
 298 {
 299         if (posted)
 300                 while (__raw_readl(timer->pend) & (reg >> WPSHIFT))
 301                         cpu_relax();
 302
 303         __raw_writel(val, timer->func_base + (reg & 0xff));
 304 }
 305
 306 static inline void __omap_dm_timer_init_regs(struct omap_dm_timer *timer)
 307 {
 308         u32 tidr;
 309
 310         /* Assume v1 ip if bits [31:16] are zero */
 311         tidr = __raw_readl(timer->io_base);
 312         if (!(tidr >> 16)) {
 313                 timer->revision = 1;
 314                 timer->sys_stat = timer->io_base +
 315                                 OMAP_TIMER_V1_SYS_STAT_OFFSET;
 316                 timer->irq_stat = timer->io_base + OMAP_TIMER_V1_STAT_OFFSET;
 317                 timer->irq_ena = timer->io_base + OMAP_TIMER_V1_INT_EN_OFFSET;
 318                 timer->irq_dis = NULL;
 319                 timer->pend = timer->io_base + _OMAP_TIMER_WRITE_PEND_OFFSET;
 320                 timer->func_base = timer->io_base;
 321         } else {
 322                 timer->revision = 2;
 323                 timer->sys_stat = NULL;
 324                 timer->irq_stat = timer->io_base + OMAP_TIMER_V2_IRQSTATUS;
 325                 timer->irq_ena = timer->io_base + OMAP_TIMER_V2_IRQENABLE_SET;
 326                 timer->irq_dis = timer->io_base + OMAP_TIMER_V2_IRQENABLE_CLR;
 327                 timer->pend = timer->io_base +
 328                         _OMAP_TIMER_WRITE_PEND_OFFSET +
 329                                 OMAP_TIMER_V2_FUNC_OFFSET;
 330                 timer->func_base = timer->io_base + OMAP_TIMER_V2_FUNC_OFFSET;
 331         }
 332 }
 333
 334 /* Assumes the source clock has been set by caller */
 335 static inline void __omap_dm_timer_reset(struct omap_dm_timer *timer,
 336                                         int autoidle, int wakeup)
 337 {
 338         u32 l;
 339
 340         l = __raw_readl(timer->io_base + OMAP_TIMER_OCP_CFG_OFFSET);
 341         l |= 0x02 << 3;  /* Set to smart-idle mode */
 342         l |= 0x2 << 8;   /* Set clock activity to perserve f-clock on idle */
 343
 344         if (autoidle)
 345                 l |= 0x1 << 0;
 346
 347         if (wakeup)
 348                 l |= 1 << 2;
 349
 350         __raw_writel(l, timer->io_base + OMAP_TIMER_OCP_CFG_OFFSET);
 351
 352         /* Match hardware reset default of posted mode */
 353         __omap_dm_timer_write(timer, OMAP_TIMER_IF_CTRL_REG,
 354                                         OMAP_TIMER_CTRL_POSTED, 0);
 355 }
 356
 357 static inline int __omap_dm_timer_set_source(struct clk *timer_fck,
 358                                                 struct clk *parent)
 359 {
 360         int ret;
 361
 362         clk_disable(timer_fck);
 363         ret = clk_set_parent(timer_fck, parent);
 364         clk_enable(timer_fck);
 365
 366         /*
 367          * When the functional clock disappears, too quick writes seem
 368          * to cause an abort. XXX Is this still necessary?
 369          */
 370         __delay(300000);
 371
 372         return ret;
 373 }
 374
 375 static inline void __omap_dm_timer_stop(struct omap_dm_timer *timer,
 376                                         int posted, unsigned long rate)
 377 {
 378         u32 l;
 379
 380         l = __omap_dm_timer_read(timer, OMAP_TIMER_CTRL_REG, posted);
 381         if (l & OMAP_TIMER_CTRL_ST) {
 382                 l &= ~0x1;
 383                 __omap_dm_timer_write(timer, OMAP_TIMER_CTRL_REG, l, posted);
 384 #ifdef CONFIG_ARCH_OMAP2PLUS
 385                 /* Readback to make sure write has completed */
 386                 __omap_dm_timer_read(timer, OMAP_TIMER_CTRL_REG, posted);
 387                 /*
 388                  * Wait for functional clock period x 3.5 to make sure that
 389                  * timer is stopped
 390                  */
 391                 udelay(3500000 / rate + 1);
 392 #endif
 393         }
 394
 395         /* Ack possibly pending interrupt */
 396         __raw_writel(OMAP_TIMER_INT_OVERFLOW, timer->irq_stat);
 397 }
 398
 399 static inline void __omap_dm_timer_load_start(struct omap_dm_timer *timer,
 400                                                 u32 ctrl, unsigned int load,
 401                                                 int posted)
 402 {
 403         __omap_dm_timer_write(timer, OMAP_TIMER_COUNTER_REG, load, posted);
 404         __omap_dm_timer_write(timer, OMAP_TIMER_CTRL_REG, ctrl, posted);
 405 }
 406
 407 static inline void __omap_dm_timer_int_enable(struct omap_dm_timer *timer,
 408                                                 unsigned int value)
 409 {
 410         __raw_writel(value, timer->irq_ena);
 411         __omap_dm_timer_write(timer, OMAP_TIMER_WAKEUP_EN_REG, value, 0);
 412 }
 413
 414 static inline unsigned int
 415 __omap_dm_timer_read_counter(struct omap_dm_timer *timer, int posted)
 416 {
 417         return __omap_dm_timer_read(timer, OMAP_TIMER_COUNTER_REG, posted);
 418 }
 419
 420 static inline void __omap_dm_timer_write_status(struct omap_dm_timer *timer,
 421                                                 unsigned int value)
 422 {
 423         __raw_writel(value, timer->irq_stat);
 424 }
 425
 426 #endif /* __ASM_ARCH_DMTIMER_H */