2 * linux/arch/arm/plat-omap/gpio.c
4 * Support functions for OMAP GPIO
6 * Copyright (C) 2003-2005 Nokia Corporation
7 * Written by Juha Yrjölä <juha.yrjola@nokia.com>
9 * Copyright (C) 2009 Texas Instruments
10 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation.
17 #include <linux/init.h>
18 #include <linux/module.h>
19 #include <linux/interrupt.h>
20 #include <linux/sysdev.h>
21 #include <linux/err.h>
22 #include <linux/clk.h>
25 #include <mach/hardware.h>
27 #include <mach/irqs.h>
28 #include <mach/gpio.h>
29 #include <asm/mach/irq.h>
32 * OMAP1510 GPIO registers
34 #define OMAP1510_GPIO_BASE 0xfffce000
35 #define OMAP1510_GPIO_DATA_INPUT 0x00
36 #define OMAP1510_GPIO_DATA_OUTPUT 0x04
37 #define OMAP1510_GPIO_DIR_CONTROL 0x08
38 #define OMAP1510_GPIO_INT_CONTROL 0x0c
39 #define OMAP1510_GPIO_INT_MASK 0x10
40 #define OMAP1510_GPIO_INT_STATUS 0x14
41 #define OMAP1510_GPIO_PIN_CONTROL 0x18
43 #define OMAP1510_IH_GPIO_BASE 64
46 * OMAP1610 specific GPIO registers
48 #define OMAP1610_GPIO1_BASE 0xfffbe400
49 #define OMAP1610_GPIO2_BASE 0xfffbec00
50 #define OMAP1610_GPIO3_BASE 0xfffbb400
51 #define OMAP1610_GPIO4_BASE 0xfffbbc00
52 #define OMAP1610_GPIO_REVISION 0x0000
53 #define OMAP1610_GPIO_SYSCONFIG 0x0010
54 #define OMAP1610_GPIO_SYSSTATUS 0x0014
55 #define OMAP1610_GPIO_IRQSTATUS1 0x0018
56 #define OMAP1610_GPIO_IRQENABLE1 0x001c
57 #define OMAP1610_GPIO_WAKEUPENABLE 0x0028
58 #define OMAP1610_GPIO_DATAIN 0x002c
59 #define OMAP1610_GPIO_DATAOUT 0x0030
60 #define OMAP1610_GPIO_DIRECTION 0x0034
61 #define OMAP1610_GPIO_EDGE_CTRL1 0x0038
62 #define OMAP1610_GPIO_EDGE_CTRL2 0x003c
63 #define OMAP1610_GPIO_CLEAR_IRQENABLE1 0x009c
64 #define OMAP1610_GPIO_CLEAR_WAKEUPENA 0x00a8
65 #define OMAP1610_GPIO_CLEAR_DATAOUT 0x00b0
66 #define OMAP1610_GPIO_SET_IRQENABLE1 0x00dc
67 #define OMAP1610_GPIO_SET_WAKEUPENA 0x00e8
68 #define OMAP1610_GPIO_SET_DATAOUT 0x00f0
71 * OMAP7XX specific GPIO registers
73 #define OMAP7XX_GPIO1_BASE 0xfffbc000
74 #define OMAP7XX_GPIO2_BASE 0xfffbc800
75 #define OMAP7XX_GPIO3_BASE 0xfffbd000
76 #define OMAP7XX_GPIO4_BASE 0xfffbd800
77 #define OMAP7XX_GPIO5_BASE 0xfffbe000
78 #define OMAP7XX_GPIO6_BASE 0xfffbe800
79 #define OMAP7XX_GPIO_DATA_INPUT 0x00
80 #define OMAP7XX_GPIO_DATA_OUTPUT 0x04
81 #define OMAP7XX_GPIO_DIR_CONTROL 0x08
82 #define OMAP7XX_GPIO_INT_CONTROL 0x0c
83 #define OMAP7XX_GPIO_INT_MASK 0x10
84 #define OMAP7XX_GPIO_INT_STATUS 0x14
86 #define OMAP1_MPUIO_VBASE OMAP1_MPUIO_BASE
89 * omap24xx specific GPIO registers
91 #define OMAP242X_GPIO1_BASE 0x48018000
92 #define OMAP242X_GPIO2_BASE 0x4801a000
93 #define OMAP242X_GPIO3_BASE 0x4801c000
94 #define OMAP242X_GPIO4_BASE 0x4801e000
96 #define OMAP243X_GPIO1_BASE 0x4900C000
97 #define OMAP243X_GPIO2_BASE 0x4900E000
98 #define OMAP243X_GPIO3_BASE 0x49010000
99 #define OMAP243X_GPIO4_BASE 0x49012000
100 #define OMAP243X_GPIO5_BASE 0x480B6000
102 #define OMAP24XX_GPIO_REVISION 0x0000
103 #define OMAP24XX_GPIO_SYSCONFIG 0x0010
104 #define OMAP24XX_GPIO_SYSSTATUS 0x0014
105 #define OMAP24XX_GPIO_IRQSTATUS1 0x0018
106 #define OMAP24XX_GPIO_IRQSTATUS2 0x0028
107 #define OMAP24XX_GPIO_IRQENABLE2 0x002c
108 #define OMAP24XX_GPIO_IRQENABLE1 0x001c
109 #define OMAP24XX_GPIO_WAKE_EN 0x0020
110 #define OMAP24XX_GPIO_CTRL 0x0030
111 #define OMAP24XX_GPIO_OE 0x0034
112 #define OMAP24XX_GPIO_DATAIN 0x0038
113 #define OMAP24XX_GPIO_DATAOUT 0x003c
114 #define OMAP24XX_GPIO_LEVELDETECT0 0x0040
115 #define OMAP24XX_GPIO_LEVELDETECT1 0x0044
116 #define OMAP24XX_GPIO_RISINGDETECT 0x0048
117 #define OMAP24XX_GPIO_FALLINGDETECT 0x004c
118 #define OMAP24XX_GPIO_DEBOUNCE_EN 0x0050
119 #define OMAP24XX_GPIO_DEBOUNCE_VAL 0x0054
120 #define OMAP24XX_GPIO_CLEARIRQENABLE1 0x0060
121 #define OMAP24XX_GPIO_SETIRQENABLE1 0x0064
122 #define OMAP24XX_GPIO_CLEARWKUENA 0x0080
123 #define OMAP24XX_GPIO_SETWKUENA 0x0084
124 #define OMAP24XX_GPIO_CLEARDATAOUT 0x0090
125 #define OMAP24XX_GPIO_SETDATAOUT 0x0094
127 #define OMAP4_GPIO_REVISION 0x0000
128 #define OMAP4_GPIO_SYSCONFIG 0x0010
129 #define OMAP4_GPIO_EOI 0x0020
130 #define OMAP4_GPIO_IRQSTATUSRAW0 0x0024
131 #define OMAP4_GPIO_IRQSTATUSRAW1 0x0028
132 #define OMAP4_GPIO_IRQSTATUS0 0x002c
133 #define OMAP4_GPIO_IRQSTATUS1 0x0030
134 #define OMAP4_GPIO_IRQSTATUSSET0 0x0034
135 #define OMAP4_GPIO_IRQSTATUSSET1 0x0038
136 #define OMAP4_GPIO_IRQSTATUSCLR0 0x003c
137 #define OMAP4_GPIO_IRQSTATUSCLR1 0x0040
138 #define OMAP4_GPIO_IRQWAKEN0 0x0044
139 #define OMAP4_GPIO_IRQWAKEN1 0x0048
140 #define OMAP4_GPIO_SYSSTATUS 0x0104
141 #define OMAP4_GPIO_CTRL 0x0130
142 #define OMAP4_GPIO_OE 0x0134
143 #define OMAP4_GPIO_DATAIN 0x0138
144 #define OMAP4_GPIO_DATAOUT 0x013c
145 #define OMAP4_GPIO_LEVELDETECT0 0x0140
146 #define OMAP4_GPIO_LEVELDETECT1 0x0144
147 #define OMAP4_GPIO_RISINGDETECT 0x0148
148 #define OMAP4_GPIO_FALLINGDETECT 0x014c
149 #define OMAP4_GPIO_DEBOUNCENABLE 0x0150
150 #define OMAP4_GPIO_DEBOUNCINGTIME 0x0154
151 #define OMAP4_GPIO_CLEARDATAOUT 0x0190
152 #define OMAP4_GPIO_SETDATAOUT 0x0194
154 * omap34xx specific GPIO registers
157 #define OMAP34XX_GPIO1_BASE 0x48310000
158 #define OMAP34XX_GPIO2_BASE 0x49050000
159 #define OMAP34XX_GPIO3_BASE 0x49052000
160 #define OMAP34XX_GPIO4_BASE 0x49054000
161 #define OMAP34XX_GPIO5_BASE 0x49056000
162 #define OMAP34XX_GPIO6_BASE 0x49058000
165 * OMAP44XX specific GPIO registers
167 #define OMAP44XX_GPIO1_BASE 0x4a310000
168 #define OMAP44XX_GPIO2_BASE 0x48055000
169 #define OMAP44XX_GPIO3_BASE 0x48057000
170 #define OMAP44XX_GPIO4_BASE 0x48059000
171 #define OMAP44XX_GPIO5_BASE 0x4805B000
172 #define OMAP44XX_GPIO6_BASE 0x4805D000
178 u16 virtual_irq_start;
180 #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP24XX) || \
181 defined(CONFIG_ARCH_OMAP34XX) || defined(CONFIG_ARCH_OMAP4)
185 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
186 defined(CONFIG_ARCH_OMAP4)
187 u32 non_wakeup_gpios;
188 u32 enabled_non_wakeup_gpios;
191 u32 saved_fallingdetect;
192 u32 saved_risingdetect;
197 struct gpio_chip chip;
202 #define METHOD_MPUIO 0
203 #define METHOD_GPIO_1510 1
204 #define METHOD_GPIO_1610 2
205 #define METHOD_GPIO_7XX 3
206 #define METHOD_GPIO_24XX 5
208 #ifdef CONFIG_ARCH_OMAP16XX
209 static struct gpio_bank gpio_bank_1610[5] = {
210 { OMAP1_MPUIO_VBASE, NULL, INT_MPUIO, IH_MPUIO_BASE,
212 { OMAP1610_GPIO1_BASE, NULL, INT_GPIO_BANK1, IH_GPIO_BASE,
214 { OMAP1610_GPIO2_BASE, NULL, INT_1610_GPIO_BANK2, IH_GPIO_BASE + 16,
216 { OMAP1610_GPIO3_BASE, NULL, INT_1610_GPIO_BANK3, IH_GPIO_BASE + 32,
218 { OMAP1610_GPIO4_BASE, NULL, INT_1610_GPIO_BANK4, IH_GPIO_BASE + 48,
223 #ifdef CONFIG_ARCH_OMAP15XX
224 static struct gpio_bank gpio_bank_1510[2] = {
225 { OMAP1_MPUIO_VBASE, NULL, INT_MPUIO, IH_MPUIO_BASE,
227 { OMAP1510_GPIO_BASE, NULL, INT_GPIO_BANK1, IH_GPIO_BASE,
232 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
233 static struct gpio_bank gpio_bank_7xx[7] = {
234 { OMAP1_MPUIO_VBASE, NULL, INT_7XX_MPUIO, IH_MPUIO_BASE,
236 { OMAP7XX_GPIO1_BASE, NULL, INT_7XX_GPIO_BANK1, IH_GPIO_BASE,
238 { OMAP7XX_GPIO2_BASE, NULL, INT_7XX_GPIO_BANK2, IH_GPIO_BASE + 32,
240 { OMAP7XX_GPIO3_BASE, NULL, INT_7XX_GPIO_BANK3, IH_GPIO_BASE + 64,
242 { OMAP7XX_GPIO4_BASE, NULL, INT_7XX_GPIO_BANK4, IH_GPIO_BASE + 96,
244 { OMAP7XX_GPIO5_BASE, NULL, INT_7XX_GPIO_BANK5, IH_GPIO_BASE + 128,
246 { OMAP7XX_GPIO6_BASE, NULL, INT_7XX_GPIO_BANK6, IH_GPIO_BASE + 160,
251 #ifdef CONFIG_ARCH_OMAP24XX
253 static struct gpio_bank gpio_bank_242x[4] = {
254 { OMAP242X_GPIO1_BASE, NULL, INT_24XX_GPIO_BANK1, IH_GPIO_BASE,
256 { OMAP242X_GPIO2_BASE, NULL, INT_24XX_GPIO_BANK2, IH_GPIO_BASE + 32,
258 { OMAP242X_GPIO3_BASE, NULL, INT_24XX_GPIO_BANK3, IH_GPIO_BASE + 64,
260 { OMAP242X_GPIO4_BASE, NULL, INT_24XX_GPIO_BANK4, IH_GPIO_BASE + 96,
264 static struct gpio_bank gpio_bank_243x[5] = {
265 { OMAP243X_GPIO1_BASE, NULL, INT_24XX_GPIO_BANK1, IH_GPIO_BASE,
267 { OMAP243X_GPIO2_BASE, NULL, INT_24XX_GPIO_BANK2, IH_GPIO_BASE + 32,
269 { OMAP243X_GPIO3_BASE, NULL, INT_24XX_GPIO_BANK3, IH_GPIO_BASE + 64,
271 { OMAP243X_GPIO4_BASE, NULL, INT_24XX_GPIO_BANK4, IH_GPIO_BASE + 96,
273 { OMAP243X_GPIO5_BASE, NULL, INT_24XX_GPIO_BANK5, IH_GPIO_BASE + 128,
279 #ifdef CONFIG_ARCH_OMAP34XX
280 static struct gpio_bank gpio_bank_34xx[6] = {
281 { OMAP34XX_GPIO1_BASE, NULL, INT_34XX_GPIO_BANK1, IH_GPIO_BASE,
283 { OMAP34XX_GPIO2_BASE, NULL, INT_34XX_GPIO_BANK2, IH_GPIO_BASE + 32,
285 { OMAP34XX_GPIO3_BASE, NULL, INT_34XX_GPIO_BANK3, IH_GPIO_BASE + 64,
287 { OMAP34XX_GPIO4_BASE, NULL, INT_34XX_GPIO_BANK4, IH_GPIO_BASE + 96,
289 { OMAP34XX_GPIO5_BASE, NULL, INT_34XX_GPIO_BANK5, IH_GPIO_BASE + 128,
291 { OMAP34XX_GPIO6_BASE, NULL, INT_34XX_GPIO_BANK6, IH_GPIO_BASE + 160,
295 struct omap3_gpio_regs {
311 static struct omap3_gpio_regs gpio_context[OMAP34XX_NR_GPIOS];
314 #ifdef CONFIG_ARCH_OMAP4
315 static struct gpio_bank gpio_bank_44xx[6] = {
316 { OMAP44XX_GPIO1_BASE, NULL, INT_44XX_GPIO_BANK1, IH_GPIO_BASE,
318 { OMAP44XX_GPIO2_BASE, NULL, INT_44XX_GPIO_BANK2, IH_GPIO_BASE + 32,
320 { OMAP44XX_GPIO3_BASE, NULL, INT_44XX_GPIO_BANK3, IH_GPIO_BASE + 64,
322 { OMAP44XX_GPIO4_BASE, NULL, INT_44XX_GPIO_BANK4, IH_GPIO_BASE + 96,
324 { OMAP44XX_GPIO5_BASE, NULL, INT_44XX_GPIO_BANK5, IH_GPIO_BASE + 128,
326 { OMAP44XX_GPIO6_BASE, NULL, INT_44XX_GPIO_BANK6, IH_GPIO_BASE + 160,
332 static struct gpio_bank *gpio_bank;
333 static int gpio_bank_count;
335 static inline struct gpio_bank *get_gpio_bank(int gpio)
337 if (cpu_is_omap15xx()) {
338 if (OMAP_GPIO_IS_MPUIO(gpio))
339 return &gpio_bank[0];
340 return &gpio_bank[1];
342 if (cpu_is_omap16xx()) {
343 if (OMAP_GPIO_IS_MPUIO(gpio))
344 return &gpio_bank[0];
345 return &gpio_bank[1 + (gpio >> 4)];
347 if (cpu_is_omap7xx()) {
348 if (OMAP_GPIO_IS_MPUIO(gpio))
349 return &gpio_bank[0];
350 return &gpio_bank[1 + (gpio >> 5)];
352 if (cpu_is_omap24xx())
353 return &gpio_bank[gpio >> 5];
354 if (cpu_is_omap34xx() || cpu_is_omap44xx())
355 return &gpio_bank[gpio >> 5];
360 static inline int get_gpio_index(int gpio)
362 if (cpu_is_omap7xx())
364 if (cpu_is_omap24xx())
366 if (cpu_is_omap34xx() || cpu_is_omap44xx())
371 static inline int gpio_valid(int gpio)
375 if (cpu_class_is_omap1() && OMAP_GPIO_IS_MPUIO(gpio)) {
376 if (gpio >= OMAP_MAX_GPIO_LINES + 16)
380 if (cpu_is_omap15xx() && gpio < 16)
382 if ((cpu_is_omap16xx()) && gpio < 64)
384 if (cpu_is_omap7xx() && gpio < 192)
386 if (cpu_is_omap24xx() && gpio < 128)
388 if ((cpu_is_omap34xx() || cpu_is_omap44xx()) && gpio < 192)
393 static int check_gpio(int gpio)
395 if (unlikely(gpio_valid(gpio) < 0)) {
396 printk(KERN_ERR "omap-gpio: invalid GPIO %d\n", gpio);
403 static void _set_gpio_direction(struct gpio_bank *bank, int gpio, int is_input)
405 void __iomem *reg = bank->base;
408 switch (bank->method) {
409 #ifdef CONFIG_ARCH_OMAP1
411 reg += OMAP_MPUIO_IO_CNTL;
414 #ifdef CONFIG_ARCH_OMAP15XX
415 case METHOD_GPIO_1510:
416 reg += OMAP1510_GPIO_DIR_CONTROL;
419 #ifdef CONFIG_ARCH_OMAP16XX
420 case METHOD_GPIO_1610:
421 reg += OMAP1610_GPIO_DIRECTION;
424 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
425 case METHOD_GPIO_7XX:
426 reg += OMAP7XX_GPIO_DIR_CONTROL;
429 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
430 case METHOD_GPIO_24XX:
431 reg += OMAP24XX_GPIO_OE;
434 #if defined(CONFIG_ARCH_OMAP4)
435 case METHOD_GPIO_24XX:
436 reg += OMAP4_GPIO_OE;
443 l = __raw_readl(reg);
448 __raw_writel(l, reg);
451 static void _set_gpio_dataout(struct gpio_bank *bank, int gpio, int enable)
453 void __iomem *reg = bank->base;
456 switch (bank->method) {
457 #ifdef CONFIG_ARCH_OMAP1
459 reg += OMAP_MPUIO_OUTPUT;
460 l = __raw_readl(reg);
467 #ifdef CONFIG_ARCH_OMAP15XX
468 case METHOD_GPIO_1510:
469 reg += OMAP1510_GPIO_DATA_OUTPUT;
470 l = __raw_readl(reg);
477 #ifdef CONFIG_ARCH_OMAP16XX
478 case METHOD_GPIO_1610:
480 reg += OMAP1610_GPIO_SET_DATAOUT;
482 reg += OMAP1610_GPIO_CLEAR_DATAOUT;
486 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
487 case METHOD_GPIO_7XX:
488 reg += OMAP7XX_GPIO_DATA_OUTPUT;
489 l = __raw_readl(reg);
496 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
497 case METHOD_GPIO_24XX:
499 reg += OMAP24XX_GPIO_SETDATAOUT;
501 reg += OMAP24XX_GPIO_CLEARDATAOUT;
505 #ifdef CONFIG_ARCH_OMAP4
506 case METHOD_GPIO_24XX:
508 reg += OMAP4_GPIO_SETDATAOUT;
510 reg += OMAP4_GPIO_CLEARDATAOUT;
518 __raw_writel(l, reg);
521 static int _get_gpio_datain(struct gpio_bank *bank, int gpio)
525 if (check_gpio(gpio) < 0)
528 switch (bank->method) {
529 #ifdef CONFIG_ARCH_OMAP1
531 reg += OMAP_MPUIO_INPUT_LATCH;
534 #ifdef CONFIG_ARCH_OMAP15XX
535 case METHOD_GPIO_1510:
536 reg += OMAP1510_GPIO_DATA_INPUT;
539 #ifdef CONFIG_ARCH_OMAP16XX
540 case METHOD_GPIO_1610:
541 reg += OMAP1610_GPIO_DATAIN;
544 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
545 case METHOD_GPIO_7XX:
546 reg += OMAP7XX_GPIO_DATA_INPUT;
549 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
550 case METHOD_GPIO_24XX:
551 reg += OMAP24XX_GPIO_DATAIN;
554 #ifdef CONFIG_ARCH_OMAP4
555 case METHOD_GPIO_24XX:
556 reg += OMAP4_GPIO_DATAIN;
562 return (__raw_readl(reg)
563 & (1 << get_gpio_index(gpio))) != 0;
566 static int _get_gpio_dataout(struct gpio_bank *bank, int gpio)
570 if (check_gpio(gpio) < 0)
574 switch (bank->method) {
575 #ifdef CONFIG_ARCH_OMAP1
577 reg += OMAP_MPUIO_OUTPUT;
580 #ifdef CONFIG_ARCH_OMAP15XX
581 case METHOD_GPIO_1510:
582 reg += OMAP1510_GPIO_DATA_OUTPUT;
585 #ifdef CONFIG_ARCH_OMAP16XX
586 case METHOD_GPIO_1610:
587 reg += OMAP1610_GPIO_DATAOUT;
590 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
591 case METHOD_GPIO_7XX:
592 reg += OMAP7XX_GPIO_DATA_OUTPUT;
595 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
596 defined(CONFIG_ARCH_OMAP4)
597 case METHOD_GPIO_24XX:
598 reg += OMAP24XX_GPIO_DATAOUT;
605 return (__raw_readl(reg) & (1 << get_gpio_index(gpio))) != 0;
608 #define MOD_REG_BIT(reg, bit_mask, set) \
610 int l = __raw_readl(base + reg); \
611 if (set) l |= bit_mask; \
612 else l &= ~bit_mask; \
613 __raw_writel(l, base + reg); \
616 void omap_set_gpio_debounce(int gpio, int enable)
618 struct gpio_bank *bank;
621 u32 val, l = 1 << get_gpio_index(gpio);
623 if (cpu_class_is_omap1())
626 bank = get_gpio_bank(gpio);
628 #ifdef CONFIG_ARCH_OMAP4
629 reg += OMAP4_GPIO_DEBOUNCENABLE;
631 reg += OMAP24XX_GPIO_DEBOUNCE_EN;
633 if (!(bank->mod_usage & l)) {
634 printk(KERN_ERR "GPIO %d not requested\n", gpio);
638 spin_lock_irqsave(&bank->lock, flags);
639 val = __raw_readl(reg);
641 if (enable && !(val & l))
643 else if (!enable && (val & l))
648 if (cpu_is_omap34xx() || cpu_is_omap44xx()) {
650 clk_enable(bank->dbck);
652 clk_disable(bank->dbck);
655 __raw_writel(val, reg);
657 spin_unlock_irqrestore(&bank->lock, flags);
659 EXPORT_SYMBOL(omap_set_gpio_debounce);
661 void omap_set_gpio_debounce_time(int gpio, int enc_time)
663 struct gpio_bank *bank;
666 if (cpu_class_is_omap1())
669 bank = get_gpio_bank(gpio);
672 if (!bank->mod_usage) {
673 printk(KERN_ERR "GPIO not requested\n");
678 #ifdef CONFIG_ARCH_OMAP4
679 reg += OMAP4_GPIO_DEBOUNCINGTIME;
681 reg += OMAP24XX_GPIO_DEBOUNCE_VAL;
683 __raw_writel(enc_time, reg);
685 EXPORT_SYMBOL(omap_set_gpio_debounce_time);
687 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
688 defined(CONFIG_ARCH_OMAP4)
689 static inline void set_24xx_gpio_triggering(struct gpio_bank *bank, int gpio,
692 void __iomem *base = bank->base;
693 u32 gpio_bit = 1 << gpio;
696 if (cpu_is_omap44xx()) {
697 MOD_REG_BIT(OMAP4_GPIO_LEVELDETECT0, gpio_bit,
698 trigger & IRQ_TYPE_LEVEL_LOW);
699 MOD_REG_BIT(OMAP4_GPIO_LEVELDETECT1, gpio_bit,
700 trigger & IRQ_TYPE_LEVEL_HIGH);
701 MOD_REG_BIT(OMAP4_GPIO_RISINGDETECT, gpio_bit,
702 trigger & IRQ_TYPE_EDGE_RISING);
703 MOD_REG_BIT(OMAP4_GPIO_FALLINGDETECT, gpio_bit,
704 trigger & IRQ_TYPE_EDGE_FALLING);
706 MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT0, gpio_bit,
707 trigger & IRQ_TYPE_LEVEL_LOW);
708 MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT1, gpio_bit,
709 trigger & IRQ_TYPE_LEVEL_HIGH);
710 MOD_REG_BIT(OMAP24XX_GPIO_RISINGDETECT, gpio_bit,
711 trigger & IRQ_TYPE_EDGE_RISING);
712 MOD_REG_BIT(OMAP24XX_GPIO_FALLINGDETECT, gpio_bit,
713 trigger & IRQ_TYPE_EDGE_FALLING);
715 if (likely(!(bank->non_wakeup_gpios & gpio_bit))) {
716 if (cpu_is_omap44xx()) {
718 __raw_writel(1 << gpio, bank->base+
719 OMAP4_GPIO_IRQWAKEN0);
721 val = __raw_readl(bank->base +
722 OMAP4_GPIO_IRQWAKEN0);
723 __raw_writel(val & (~(1 << gpio)), bank->base +
724 OMAP4_GPIO_IRQWAKEN0);
728 __raw_writel(1 << gpio, bank->base
729 + OMAP24XX_GPIO_SETWKUENA);
731 __raw_writel(1 << gpio, bank->base
732 + OMAP24XX_GPIO_CLEARWKUENA);
736 bank->enabled_non_wakeup_gpios |= gpio_bit;
738 bank->enabled_non_wakeup_gpios &= ~gpio_bit;
741 if (cpu_is_omap44xx()) {
743 __raw_readl(bank->base + OMAP4_GPIO_LEVELDETECT0) |
744 __raw_readl(bank->base + OMAP4_GPIO_LEVELDETECT1);
747 __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0) |
748 __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1);
753 #ifdef CONFIG_ARCH_OMAP1
755 * This only applies to chips that can't do both rising and falling edge
756 * detection at once. For all other chips, this function is a noop.
758 static void _toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio)
760 void __iomem *reg = bank->base;
763 switch (bank->method) {
765 reg += OMAP_MPUIO_GPIO_INT_EDGE;
767 #ifdef CONFIG_ARCH_OMAP15XX
768 case METHOD_GPIO_1510:
769 reg += OMAP1510_GPIO_INT_CONTROL;
772 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
773 case METHOD_GPIO_7XX:
774 reg += OMAP7XX_GPIO_INT_CONTROL;
781 l = __raw_readl(reg);
787 __raw_writel(l, reg);
791 static int _set_gpio_triggering(struct gpio_bank *bank, int gpio, int trigger)
793 void __iomem *reg = bank->base;
796 switch (bank->method) {
797 #ifdef CONFIG_ARCH_OMAP1
799 reg += OMAP_MPUIO_GPIO_INT_EDGE;
800 l = __raw_readl(reg);
801 if (trigger & IRQ_TYPE_EDGE_BOTH)
802 bank->toggle_mask |= 1 << gpio;
803 if (trigger & IRQ_TYPE_EDGE_RISING)
805 else if (trigger & IRQ_TYPE_EDGE_FALLING)
811 #ifdef CONFIG_ARCH_OMAP15XX
812 case METHOD_GPIO_1510:
813 reg += OMAP1510_GPIO_INT_CONTROL;
814 l = __raw_readl(reg);
815 if (trigger & IRQ_TYPE_EDGE_BOTH)
816 bank->toggle_mask |= 1 << gpio;
817 if (trigger & IRQ_TYPE_EDGE_RISING)
819 else if (trigger & IRQ_TYPE_EDGE_FALLING)
825 #ifdef CONFIG_ARCH_OMAP16XX
826 case METHOD_GPIO_1610:
828 reg += OMAP1610_GPIO_EDGE_CTRL2;
830 reg += OMAP1610_GPIO_EDGE_CTRL1;
832 l = __raw_readl(reg);
833 l &= ~(3 << (gpio << 1));
834 if (trigger & IRQ_TYPE_EDGE_RISING)
835 l |= 2 << (gpio << 1);
836 if (trigger & IRQ_TYPE_EDGE_FALLING)
837 l |= 1 << (gpio << 1);
839 /* Enable wake-up during idle for dynamic tick */
840 __raw_writel(1 << gpio, bank->base + OMAP1610_GPIO_SET_WAKEUPENA);
842 __raw_writel(1 << gpio, bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA);
845 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
846 case METHOD_GPIO_7XX:
847 reg += OMAP7XX_GPIO_INT_CONTROL;
848 l = __raw_readl(reg);
849 if (trigger & IRQ_TYPE_EDGE_BOTH)
850 bank->toggle_mask |= 1 << gpio;
851 if (trigger & IRQ_TYPE_EDGE_RISING)
853 else if (trigger & IRQ_TYPE_EDGE_FALLING)
859 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
860 defined(CONFIG_ARCH_OMAP4)
861 case METHOD_GPIO_24XX:
862 set_24xx_gpio_triggering(bank, gpio, trigger);
868 __raw_writel(l, reg);
874 static int gpio_irq_type(unsigned irq, unsigned type)
876 struct gpio_bank *bank;
881 if (!cpu_class_is_omap2() && irq > IH_MPUIO_BASE)
882 gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE);
884 gpio = irq - IH_GPIO_BASE;
886 if (check_gpio(gpio) < 0)
889 if (type & ~IRQ_TYPE_SENSE_MASK)
892 /* OMAP1 allows only only edge triggering */
893 if (!cpu_class_is_omap2()
894 && (type & (IRQ_TYPE_LEVEL_LOW|IRQ_TYPE_LEVEL_HIGH)))
897 bank = get_irq_chip_data(irq);
898 spin_lock_irqsave(&bank->lock, flags);
899 retval = _set_gpio_triggering(bank, get_gpio_index(gpio), type);
901 irq_desc[irq].status &= ~IRQ_TYPE_SENSE_MASK;
902 irq_desc[irq].status |= type;
904 spin_unlock_irqrestore(&bank->lock, flags);
906 if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
907 __set_irq_handler_unlocked(irq, handle_level_irq);
908 else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
909 __set_irq_handler_unlocked(irq, handle_edge_irq);
914 static void _clear_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
916 void __iomem *reg = bank->base;
918 switch (bank->method) {
919 #ifdef CONFIG_ARCH_OMAP1
921 /* MPUIO irqstatus is reset by reading the status register,
922 * so do nothing here */
925 #ifdef CONFIG_ARCH_OMAP15XX
926 case METHOD_GPIO_1510:
927 reg += OMAP1510_GPIO_INT_STATUS;
930 #ifdef CONFIG_ARCH_OMAP16XX
931 case METHOD_GPIO_1610:
932 reg += OMAP1610_GPIO_IRQSTATUS1;
935 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
936 case METHOD_GPIO_7XX:
937 reg += OMAP7XX_GPIO_INT_STATUS;
940 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
941 case METHOD_GPIO_24XX:
942 reg += OMAP24XX_GPIO_IRQSTATUS1;
945 #if defined(CONFIG_ARCH_OMAP4)
946 case METHOD_GPIO_24XX:
947 reg += OMAP4_GPIO_IRQSTATUS0;
954 __raw_writel(gpio_mask, reg);
956 /* Workaround for clearing DSP GPIO interrupts to allow retention */
957 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
958 reg = bank->base + OMAP24XX_GPIO_IRQSTATUS2;
960 #if defined(CONFIG_ARCH_OMAP4)
961 reg = bank->base + OMAP4_GPIO_IRQSTATUS1;
963 if (cpu_is_omap24xx() || cpu_is_omap34xx() || cpu_is_omap44xx()) {
964 __raw_writel(gpio_mask, reg);
966 /* Flush posted write for the irq status to avoid spurious interrupts */
971 static inline void _clear_gpio_irqstatus(struct gpio_bank *bank, int gpio)
973 _clear_gpio_irqbank(bank, 1 << get_gpio_index(gpio));
976 static u32 _get_gpio_irqbank_mask(struct gpio_bank *bank)
978 void __iomem *reg = bank->base;
983 switch (bank->method) {
984 #ifdef CONFIG_ARCH_OMAP1
986 reg += OMAP_MPUIO_GPIO_MASKIT;
991 #ifdef CONFIG_ARCH_OMAP15XX
992 case METHOD_GPIO_1510:
993 reg += OMAP1510_GPIO_INT_MASK;
998 #ifdef CONFIG_ARCH_OMAP16XX
999 case METHOD_GPIO_1610:
1000 reg += OMAP1610_GPIO_IRQENABLE1;
1004 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
1005 case METHOD_GPIO_7XX:
1006 reg += OMAP7XX_GPIO_INT_MASK;
1011 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1012 case METHOD_GPIO_24XX:
1013 reg += OMAP24XX_GPIO_IRQENABLE1;
1017 #if defined(CONFIG_ARCH_OMAP4)
1018 case METHOD_GPIO_24XX:
1019 reg += OMAP4_GPIO_IRQSTATUSSET0;
1028 l = __raw_readl(reg);
1035 static void _enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask, int enable)
1037 void __iomem *reg = bank->base;
1040 switch (bank->method) {
1041 #ifdef CONFIG_ARCH_OMAP1
1043 reg += OMAP_MPUIO_GPIO_MASKIT;
1044 l = __raw_readl(reg);
1051 #ifdef CONFIG_ARCH_OMAP15XX
1052 case METHOD_GPIO_1510:
1053 reg += OMAP1510_GPIO_INT_MASK;
1054 l = __raw_readl(reg);
1061 #ifdef CONFIG_ARCH_OMAP16XX
1062 case METHOD_GPIO_1610:
1064 reg += OMAP1610_GPIO_SET_IRQENABLE1;
1066 reg += OMAP1610_GPIO_CLEAR_IRQENABLE1;
1070 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
1071 case METHOD_GPIO_7XX:
1072 reg += OMAP7XX_GPIO_INT_MASK;
1073 l = __raw_readl(reg);
1080 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1081 case METHOD_GPIO_24XX:
1083 reg += OMAP24XX_GPIO_SETIRQENABLE1;
1085 reg += OMAP24XX_GPIO_CLEARIRQENABLE1;
1089 #ifdef CONFIG_ARCH_OMAP4
1090 case METHOD_GPIO_24XX:
1092 reg += OMAP4_GPIO_IRQSTATUSSET0;
1094 reg += OMAP4_GPIO_IRQSTATUSCLR0;
1102 __raw_writel(l, reg);
1105 static inline void _set_gpio_irqenable(struct gpio_bank *bank, int gpio, int enable)
1107 _enable_gpio_irqbank(bank, 1 << get_gpio_index(gpio), enable);
1111 * Note that ENAWAKEUP needs to be enabled in GPIO_SYSCONFIG register.
1112 * 1510 does not seem to have a wake-up register. If JTAG is connected
1113 * to the target, system will wake up always on GPIO events. While
1114 * system is running all registered GPIO interrupts need to have wake-up
1115 * enabled. When system is suspended, only selected GPIO interrupts need
1116 * to have wake-up enabled.
1118 static int _set_gpio_wakeup(struct gpio_bank *bank, int gpio, int enable)
1120 unsigned long uninitialized_var(flags);
1122 switch (bank->method) {
1123 #ifdef CONFIG_ARCH_OMAP16XX
1125 case METHOD_GPIO_1610:
1126 spin_lock_irqsave(&bank->lock, flags);
1128 bank->suspend_wakeup |= (1 << gpio);
1130 bank->suspend_wakeup &= ~(1 << gpio);
1131 spin_unlock_irqrestore(&bank->lock, flags);
1134 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
1135 defined(CONFIG_ARCH_OMAP4)
1136 case METHOD_GPIO_24XX:
1137 if (bank->non_wakeup_gpios & (1 << gpio)) {
1138 printk(KERN_ERR "Unable to modify wakeup on "
1139 "non-wakeup GPIO%d\n",
1140 (bank - gpio_bank) * 32 + gpio);
1143 spin_lock_irqsave(&bank->lock, flags);
1145 bank->suspend_wakeup |= (1 << gpio);
1147 bank->suspend_wakeup &= ~(1 << gpio);
1148 spin_unlock_irqrestore(&bank->lock, flags);
1152 printk(KERN_ERR "Can't enable GPIO wakeup for method %i\n",
1158 static void _reset_gpio(struct gpio_bank *bank, int gpio)
1160 _set_gpio_direction(bank, get_gpio_index(gpio), 1);
1161 _set_gpio_irqenable(bank, gpio, 0);
1162 _clear_gpio_irqstatus(bank, gpio);
1163 _set_gpio_triggering(bank, get_gpio_index(gpio), IRQ_TYPE_NONE);
1166 /* Use disable_irq_wake() and enable_irq_wake() functions from drivers */
1167 static int gpio_wake_enable(unsigned int irq, unsigned int enable)
1169 unsigned int gpio = irq - IH_GPIO_BASE;
1170 struct gpio_bank *bank;
1173 if (check_gpio(gpio) < 0)
1175 bank = get_irq_chip_data(irq);
1176 retval = _set_gpio_wakeup(bank, get_gpio_index(gpio), enable);
1181 static int omap_gpio_request(struct gpio_chip *chip, unsigned offset)
1183 struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip);
1184 unsigned long flags;
1186 spin_lock_irqsave(&bank->lock, flags);
1188 /* Set trigger to none. You need to enable the desired trigger with
1189 * request_irq() or set_irq_type().
1191 _set_gpio_triggering(bank, offset, IRQ_TYPE_NONE);
1193 #ifdef CONFIG_ARCH_OMAP15XX
1194 if (bank->method == METHOD_GPIO_1510) {
1197 /* Claim the pin for MPU */
1198 reg = bank->base + OMAP1510_GPIO_PIN_CONTROL;
1199 __raw_writel(__raw_readl(reg) | (1 << offset), reg);
1202 if (!cpu_class_is_omap1()) {
1203 if (!bank->mod_usage) {
1205 ctrl = __raw_readl(bank->base + OMAP24XX_GPIO_CTRL);
1207 /* Module is enabled, clocks are not gated */
1208 __raw_writel(ctrl, bank->base + OMAP24XX_GPIO_CTRL);
1210 bank->mod_usage |= 1 << offset;
1212 spin_unlock_irqrestore(&bank->lock, flags);
1217 static void omap_gpio_free(struct gpio_chip *chip, unsigned offset)
1219 struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip);
1220 unsigned long flags;
1222 spin_lock_irqsave(&bank->lock, flags);
1223 #ifdef CONFIG_ARCH_OMAP16XX
1224 if (bank->method == METHOD_GPIO_1610) {
1225 /* Disable wake-up during idle for dynamic tick */
1226 void __iomem *reg = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
1227 __raw_writel(1 << offset, reg);
1230 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
1231 defined(CONFIG_ARCH_OMAP4)
1232 if (bank->method == METHOD_GPIO_24XX) {
1233 /* Disable wake-up during idle for dynamic tick */
1234 void __iomem *reg = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
1235 __raw_writel(1 << offset, reg);
1238 if (!cpu_class_is_omap1()) {
1239 bank->mod_usage &= ~(1 << offset);
1240 if (!bank->mod_usage) {
1242 ctrl = __raw_readl(bank->base + OMAP24XX_GPIO_CTRL);
1243 /* Module is disabled, clocks are gated */
1245 __raw_writel(ctrl, bank->base + OMAP24XX_GPIO_CTRL);
1248 _reset_gpio(bank, bank->chip.base + offset);
1249 spin_unlock_irqrestore(&bank->lock, flags);
1253 * We need to unmask the GPIO bank interrupt as soon as possible to
1254 * avoid missing GPIO interrupts for other lines in the bank.
1255 * Then we need to mask-read-clear-unmask the triggered GPIO lines
1256 * in the bank to avoid missing nested interrupts for a GPIO line.
1257 * If we wait to unmask individual GPIO lines in the bank after the
1258 * line's interrupt handler has been run, we may miss some nested
1261 static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
1263 void __iomem *isr_reg = NULL;
1265 unsigned int gpio_irq, gpio_index;
1266 struct gpio_bank *bank;
1270 desc->chip->ack(irq);
1272 bank = get_irq_data(irq);
1273 #ifdef CONFIG_ARCH_OMAP1
1274 if (bank->method == METHOD_MPUIO)
1275 isr_reg = bank->base + OMAP_MPUIO_GPIO_INT;
1277 #ifdef CONFIG_ARCH_OMAP15XX
1278 if (bank->method == METHOD_GPIO_1510)
1279 isr_reg = bank->base + OMAP1510_GPIO_INT_STATUS;
1281 #if defined(CONFIG_ARCH_OMAP16XX)
1282 if (bank->method == METHOD_GPIO_1610)
1283 isr_reg = bank->base + OMAP1610_GPIO_IRQSTATUS1;
1285 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
1286 if (bank->method == METHOD_GPIO_7XX)
1287 isr_reg = bank->base + OMAP7XX_GPIO_INT_STATUS;
1289 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1290 if (bank->method == METHOD_GPIO_24XX)
1291 isr_reg = bank->base + OMAP24XX_GPIO_IRQSTATUS1;
1293 #if defined(CONFIG_ARCH_OMAP4)
1294 if (bank->method == METHOD_GPIO_24XX)
1295 isr_reg = bank->base + OMAP4_GPIO_IRQSTATUS0;
1298 u32 isr_saved, level_mask = 0;
1301 enabled = _get_gpio_irqbank_mask(bank);
1302 isr_saved = isr = __raw_readl(isr_reg) & enabled;
1304 if (cpu_is_omap15xx() && (bank->method == METHOD_MPUIO))
1307 if (cpu_class_is_omap2()) {
1308 level_mask = bank->level_mask & enabled;
1311 /* clear edge sensitive interrupts before handler(s) are
1312 called so that we don't miss any interrupt occurred while
1314 _enable_gpio_irqbank(bank, isr_saved & ~level_mask, 0);
1315 _clear_gpio_irqbank(bank, isr_saved & ~level_mask);
1316 _enable_gpio_irqbank(bank, isr_saved & ~level_mask, 1);
1318 /* if there is only edge sensitive GPIO pin interrupts
1319 configured, we could unmask GPIO bank interrupt immediately */
1320 if (!level_mask && !unmasked) {
1322 desc->chip->unmask(irq);
1330 gpio_irq = bank->virtual_irq_start;
1331 for (; isr != 0; isr >>= 1, gpio_irq++) {
1332 gpio_index = get_gpio_index(irq_to_gpio(gpio_irq));
1337 #ifdef CONFIG_ARCH_OMAP1
1339 * Some chips can't respond to both rising and falling
1340 * at the same time. If this irq was requested with
1341 * both flags, we need to flip the ICR data for the IRQ
1342 * to respond to the IRQ for the opposite direction.
1343 * This will be indicated in the bank toggle_mask.
1345 if (bank->toggle_mask & (1 << gpio_index))
1346 _toggle_gpio_edge_triggering(bank, gpio_index);
1349 generic_handle_irq(gpio_irq);
1352 /* if bank has any level sensitive GPIO pin interrupt
1353 configured, we must unmask the bank interrupt only after
1354 handler(s) are executed in order to avoid spurious bank
1357 desc->chip->unmask(irq);
1361 static void gpio_irq_shutdown(unsigned int irq)
1363 unsigned int gpio = irq - IH_GPIO_BASE;
1364 struct gpio_bank *bank = get_irq_chip_data(irq);
1366 _reset_gpio(bank, gpio);
1369 static void gpio_ack_irq(unsigned int irq)
1371 unsigned int gpio = irq - IH_GPIO_BASE;
1372 struct gpio_bank *bank = get_irq_chip_data(irq);
1374 _clear_gpio_irqstatus(bank, gpio);
1377 static void gpio_mask_irq(unsigned int irq)
1379 unsigned int gpio = irq - IH_GPIO_BASE;
1380 struct gpio_bank *bank = get_irq_chip_data(irq);
1382 _set_gpio_irqenable(bank, gpio, 0);
1383 _set_gpio_triggering(bank, get_gpio_index(gpio), IRQ_TYPE_NONE);
1386 static void gpio_unmask_irq(unsigned int irq)
1388 unsigned int gpio = irq - IH_GPIO_BASE;
1389 struct gpio_bank *bank = get_irq_chip_data(irq);
1390 unsigned int irq_mask = 1 << get_gpio_index(gpio);
1391 struct irq_desc *desc = irq_to_desc(irq);
1392 u32 trigger = desc->status & IRQ_TYPE_SENSE_MASK;
1395 _set_gpio_triggering(bank, get_gpio_index(gpio), trigger);
1397 /* For level-triggered GPIOs, the clearing must be done after
1398 * the HW source is cleared, thus after the handler has run */
1399 if (bank->level_mask & irq_mask) {
1400 _set_gpio_irqenable(bank, gpio, 0);
1401 _clear_gpio_irqstatus(bank, gpio);
1404 _set_gpio_irqenable(bank, gpio, 1);
1407 static struct irq_chip gpio_irq_chip = {
1409 .shutdown = gpio_irq_shutdown,
1410 .ack = gpio_ack_irq,
1411 .mask = gpio_mask_irq,
1412 .unmask = gpio_unmask_irq,
1413 .set_type = gpio_irq_type,
1414 .set_wake = gpio_wake_enable,
1417 /*---------------------------------------------------------------------*/
1419 #ifdef CONFIG_ARCH_OMAP1
1421 /* MPUIO uses the always-on 32k clock */
1423 static void mpuio_ack_irq(unsigned int irq)
1425 /* The ISR is reset automatically, so do nothing here. */
1428 static void mpuio_mask_irq(unsigned int irq)
1430 unsigned int gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE);
1431 struct gpio_bank *bank = get_irq_chip_data(irq);
1433 _set_gpio_irqenable(bank, gpio, 0);
1436 static void mpuio_unmask_irq(unsigned int irq)
1438 unsigned int gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE);
1439 struct gpio_bank *bank = get_irq_chip_data(irq);
1441 _set_gpio_irqenable(bank, gpio, 1);
1444 static struct irq_chip mpuio_irq_chip = {
1446 .ack = mpuio_ack_irq,
1447 .mask = mpuio_mask_irq,
1448 .unmask = mpuio_unmask_irq,
1449 .set_type = gpio_irq_type,
1450 #ifdef CONFIG_ARCH_OMAP16XX
1451 /* REVISIT: assuming only 16xx supports MPUIO wake events */
1452 .set_wake = gpio_wake_enable,
1457 #define bank_is_mpuio(bank) ((bank)->method == METHOD_MPUIO)
1460 #ifdef CONFIG_ARCH_OMAP16XX
1462 #include <linux/platform_device.h>
1464 static int omap_mpuio_suspend_noirq(struct device *dev)
1466 struct platform_device *pdev = to_platform_device(dev);
1467 struct gpio_bank *bank = platform_get_drvdata(pdev);
1468 void __iomem *mask_reg = bank->base + OMAP_MPUIO_GPIO_MASKIT;
1469 unsigned long flags;
1471 spin_lock_irqsave(&bank->lock, flags);
1472 bank->saved_wakeup = __raw_readl(mask_reg);
1473 __raw_writel(0xffff & ~bank->suspend_wakeup, mask_reg);
1474 spin_unlock_irqrestore(&bank->lock, flags);
1479 static int omap_mpuio_resume_noirq(struct device *dev)
1481 struct platform_device *pdev = to_platform_device(dev);
1482 struct gpio_bank *bank = platform_get_drvdata(pdev);
1483 void __iomem *mask_reg = bank->base + OMAP_MPUIO_GPIO_MASKIT;
1484 unsigned long flags;
1486 spin_lock_irqsave(&bank->lock, flags);
1487 __raw_writel(bank->saved_wakeup, mask_reg);
1488 spin_unlock_irqrestore(&bank->lock, flags);
1493 static const struct dev_pm_ops omap_mpuio_dev_pm_ops = {
1494 .suspend_noirq = omap_mpuio_suspend_noirq,
1495 .resume_noirq = omap_mpuio_resume_noirq,
1498 /* use platform_driver for this, now that there's no longer any
1499 * point to sys_device (other than not disturbing old code).
1501 static struct platform_driver omap_mpuio_driver = {
1504 .pm = &omap_mpuio_dev_pm_ops,
1508 static struct platform_device omap_mpuio_device = {
1512 .driver = &omap_mpuio_driver.driver,
1514 /* could list the /proc/iomem resources */
1517 static inline void mpuio_init(void)
1519 platform_set_drvdata(&omap_mpuio_device, &gpio_bank_1610[0]);
1521 if (platform_driver_register(&omap_mpuio_driver) == 0)
1522 (void) platform_device_register(&omap_mpuio_device);
1526 static inline void mpuio_init(void) {}
1531 extern struct irq_chip mpuio_irq_chip;
1533 #define bank_is_mpuio(bank) 0
1534 static inline void mpuio_init(void) {}
1538 /*---------------------------------------------------------------------*/
1540 /* REVISIT these are stupid implementations! replace by ones that
1541 * don't switch on METHOD_* and which mostly avoid spinlocks
1544 static int gpio_input(struct gpio_chip *chip, unsigned offset)
1546 struct gpio_bank *bank;
1547 unsigned long flags;
1549 bank = container_of(chip, struct gpio_bank, chip);
1550 spin_lock_irqsave(&bank->lock, flags);
1551 _set_gpio_direction(bank, offset, 1);
1552 spin_unlock_irqrestore(&bank->lock, flags);
1556 static int gpio_is_input(struct gpio_bank *bank, int mask)
1558 void __iomem *reg = bank->base;
1560 switch (bank->method) {
1562 reg += OMAP_MPUIO_IO_CNTL;
1564 case METHOD_GPIO_1510:
1565 reg += OMAP1510_GPIO_DIR_CONTROL;
1567 case METHOD_GPIO_1610:
1568 reg += OMAP1610_GPIO_DIRECTION;
1570 case METHOD_GPIO_7XX:
1571 reg += OMAP7XX_GPIO_DIR_CONTROL;
1573 case METHOD_GPIO_24XX:
1574 reg += OMAP24XX_GPIO_OE;
1577 return __raw_readl(reg) & mask;
1580 static int gpio_get(struct gpio_chip *chip, unsigned offset)
1582 struct gpio_bank *bank;
1587 gpio = chip->base + offset;
1588 bank = get_gpio_bank(gpio);
1590 mask = 1 << get_gpio_index(gpio);
1592 if (gpio_is_input(bank, mask))
1593 return _get_gpio_datain(bank, gpio);
1595 return _get_gpio_dataout(bank, gpio);
1598 static int gpio_output(struct gpio_chip *chip, unsigned offset, int value)
1600 struct gpio_bank *bank;
1601 unsigned long flags;
1603 bank = container_of(chip, struct gpio_bank, chip);
1604 spin_lock_irqsave(&bank->lock, flags);
1605 _set_gpio_dataout(bank, offset, value);
1606 _set_gpio_direction(bank, offset, 0);
1607 spin_unlock_irqrestore(&bank->lock, flags);
1611 static void gpio_set(struct gpio_chip *chip, unsigned offset, int value)
1613 struct gpio_bank *bank;
1614 unsigned long flags;
1616 bank = container_of(chip, struct gpio_bank, chip);
1617 spin_lock_irqsave(&bank->lock, flags);
1618 _set_gpio_dataout(bank, offset, value);
1619 spin_unlock_irqrestore(&bank->lock, flags);
1622 static int gpio_2irq(struct gpio_chip *chip, unsigned offset)
1624 struct gpio_bank *bank;
1626 bank = container_of(chip, struct gpio_bank, chip);
1627 return bank->virtual_irq_start + offset;
1630 /*---------------------------------------------------------------------*/
1632 static int initialized;
1633 #if !(defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4))
1634 static struct clk * gpio_ick;
1637 #if defined(CONFIG_ARCH_OMAP2)
1638 static struct clk * gpio_fck;
1641 #if defined(CONFIG_ARCH_OMAP2430)
1642 static struct clk * gpio5_ick;
1643 static struct clk * gpio5_fck;
1646 #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
1647 static struct clk *gpio_iclks[OMAP34XX_NR_GPIOS];
1650 static void __init omap_gpio_show_rev(void)
1654 if (cpu_is_omap16xx())
1655 rev = __raw_readw(gpio_bank[1].base + OMAP1610_GPIO_REVISION);
1656 else if (cpu_is_omap24xx() || cpu_is_omap34xx())
1657 rev = __raw_readl(gpio_bank[0].base + OMAP24XX_GPIO_REVISION);
1658 else if (cpu_is_omap44xx())
1659 rev = __raw_readl(gpio_bank[0].base + OMAP4_GPIO_REVISION);
1663 printk(KERN_INFO "OMAP GPIO hardware version %d.%d\n",
1664 (rev >> 4) & 0x0f, rev & 0x0f);
1667 /* This lock class tells lockdep that GPIO irqs are in a different
1668 * category than their parents, so it won't report false recursion.
1670 static struct lock_class_key gpio_lock_class;
1672 static int __init _omap_gpio_init(void)
1676 struct gpio_bank *bank;
1677 int bank_size = SZ_8K; /* Module 4KB + L4 4KB except on omap1 */
1682 #if defined(CONFIG_ARCH_OMAP1)
1683 if (cpu_is_omap15xx()) {
1684 gpio_ick = clk_get(NULL, "arm_gpio_ck");
1685 if (IS_ERR(gpio_ick))
1686 printk("Could not get arm_gpio_ck\n");
1688 clk_enable(gpio_ick);
1691 #if defined(CONFIG_ARCH_OMAP2)
1692 if (cpu_class_is_omap2()) {
1693 gpio_ick = clk_get(NULL, "gpios_ick");
1694 if (IS_ERR(gpio_ick))
1695 printk("Could not get gpios_ick\n");
1697 clk_enable(gpio_ick);
1698 gpio_fck = clk_get(NULL, "gpios_fck");
1699 if (IS_ERR(gpio_fck))
1700 printk("Could not get gpios_fck\n");
1702 clk_enable(gpio_fck);
1705 * On 2430 & 3430 GPIO 5 uses CORE L4 ICLK
1707 #if defined(CONFIG_ARCH_OMAP2430)
1708 if (cpu_is_omap2430()) {
1709 gpio5_ick = clk_get(NULL, "gpio5_ick");
1710 if (IS_ERR(gpio5_ick))
1711 printk("Could not get gpio5_ick\n");
1713 clk_enable(gpio5_ick);
1714 gpio5_fck = clk_get(NULL, "gpio5_fck");
1715 if (IS_ERR(gpio5_fck))
1716 printk("Could not get gpio5_fck\n");
1718 clk_enable(gpio5_fck);
1724 #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
1725 if (cpu_is_omap34xx() || cpu_is_omap44xx()) {
1726 for (i = 0; i < OMAP34XX_NR_GPIOS; i++) {
1727 sprintf(clk_name, "gpio%d_ick", i + 1);
1728 gpio_iclks[i] = clk_get(NULL, clk_name);
1729 if (IS_ERR(gpio_iclks[i]))
1730 printk(KERN_ERR "Could not get %s\n", clk_name);
1732 clk_enable(gpio_iclks[i]);
1738 #ifdef CONFIG_ARCH_OMAP15XX
1739 if (cpu_is_omap15xx()) {
1740 gpio_bank_count = 2;
1741 gpio_bank = gpio_bank_1510;
1745 #if defined(CONFIG_ARCH_OMAP16XX)
1746 if (cpu_is_omap16xx()) {
1747 gpio_bank_count = 5;
1748 gpio_bank = gpio_bank_1610;
1752 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
1753 if (cpu_is_omap7xx()) {
1754 gpio_bank_count = 7;
1755 gpio_bank = gpio_bank_7xx;
1759 #ifdef CONFIG_ARCH_OMAP24XX
1760 if (cpu_is_omap242x()) {
1761 gpio_bank_count = 4;
1762 gpio_bank = gpio_bank_242x;
1764 if (cpu_is_omap243x()) {
1765 gpio_bank_count = 5;
1766 gpio_bank = gpio_bank_243x;
1769 #ifdef CONFIG_ARCH_OMAP34XX
1770 if (cpu_is_omap34xx()) {
1771 gpio_bank_count = OMAP34XX_NR_GPIOS;
1772 gpio_bank = gpio_bank_34xx;
1775 #ifdef CONFIG_ARCH_OMAP4
1776 if (cpu_is_omap44xx()) {
1777 gpio_bank_count = OMAP34XX_NR_GPIOS;
1778 gpio_bank = gpio_bank_44xx;
1781 for (i = 0; i < gpio_bank_count; i++) {
1782 int j, gpio_count = 16;
1784 bank = &gpio_bank[i];
1785 spin_lock_init(&bank->lock);
1787 /* Static mapping, never released */
1788 bank->base = ioremap(bank->pbase, bank_size);
1790 printk(KERN_ERR "Could not ioremap gpio bank%i\n", i);
1794 if (bank_is_mpuio(bank))
1795 __raw_writew(0xffff, bank->base + OMAP_MPUIO_GPIO_MASKIT);
1796 if (cpu_is_omap15xx() && bank->method == METHOD_GPIO_1510) {
1797 __raw_writew(0xffff, bank->base + OMAP1510_GPIO_INT_MASK);
1798 __raw_writew(0x0000, bank->base + OMAP1510_GPIO_INT_STATUS);
1800 if (cpu_is_omap16xx() && bank->method == METHOD_GPIO_1610) {
1801 __raw_writew(0x0000, bank->base + OMAP1610_GPIO_IRQENABLE1);
1802 __raw_writew(0xffff, bank->base + OMAP1610_GPIO_IRQSTATUS1);
1803 __raw_writew(0x0014, bank->base + OMAP1610_GPIO_SYSCONFIG);
1805 if (cpu_is_omap7xx() && bank->method == METHOD_GPIO_7XX) {
1806 __raw_writel(0xffffffff, bank->base + OMAP7XX_GPIO_INT_MASK);
1807 __raw_writel(0x00000000, bank->base + OMAP7XX_GPIO_INT_STATUS);
1809 gpio_count = 32; /* 7xx has 32-bit GPIOs */
1812 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
1813 defined(CONFIG_ARCH_OMAP4)
1814 if (bank->method == METHOD_GPIO_24XX) {
1815 static const u32 non_wakeup_gpios[] = {
1816 0xe203ffc0, 0x08700040
1818 if (cpu_is_omap44xx()) {
1819 __raw_writel(0xffffffff, bank->base +
1820 OMAP4_GPIO_IRQSTATUSCLR0);
1821 __raw_writew(0x0015, bank->base +
1822 OMAP4_GPIO_SYSCONFIG);
1823 __raw_writel(0x00000000, bank->base +
1824 OMAP4_GPIO_DEBOUNCENABLE);
1825 /* Initialize interface clock ungated, module enabled */
1826 __raw_writel(0, bank->base + OMAP4_GPIO_CTRL);
1828 __raw_writel(0x00000000, bank->base + OMAP24XX_GPIO_IRQENABLE1);
1829 __raw_writel(0xffffffff, bank->base + OMAP24XX_GPIO_IRQSTATUS1);
1830 __raw_writew(0x0015, bank->base + OMAP24XX_GPIO_SYSCONFIG);
1831 __raw_writel(0x00000000, bank->base + OMAP24XX_GPIO_DEBOUNCE_EN);
1833 /* Initialize interface clock ungated, module enabled */
1834 __raw_writel(0, bank->base + OMAP24XX_GPIO_CTRL);
1836 if (i < ARRAY_SIZE(non_wakeup_gpios))
1837 bank->non_wakeup_gpios = non_wakeup_gpios[i];
1842 bank->mod_usage = 0;
1843 /* REVISIT eventually switch from OMAP-specific gpio structs
1844 * over to the generic ones
1846 bank->chip.request = omap_gpio_request;
1847 bank->chip.free = omap_gpio_free;
1848 bank->chip.direction_input = gpio_input;
1849 bank->chip.get = gpio_get;
1850 bank->chip.direction_output = gpio_output;
1851 bank->chip.set = gpio_set;
1852 bank->chip.to_irq = gpio_2irq;
1853 if (bank_is_mpuio(bank)) {
1854 bank->chip.label = "mpuio";
1855 #ifdef CONFIG_ARCH_OMAP16XX
1856 bank->chip.dev = &omap_mpuio_device.dev;
1858 bank->chip.base = OMAP_MPUIO(0);
1860 bank->chip.label = "gpio";
1861 bank->chip.base = gpio;
1864 bank->chip.ngpio = gpio_count;
1866 gpiochip_add(&bank->chip);
1868 for (j = bank->virtual_irq_start;
1869 j < bank->virtual_irq_start + gpio_count; j++) {
1870 lockdep_set_class(&irq_desc[j].lock, &gpio_lock_class);
1871 set_irq_chip_data(j, bank);
1872 if (bank_is_mpuio(bank))
1873 set_irq_chip(j, &mpuio_irq_chip);
1875 set_irq_chip(j, &gpio_irq_chip);
1876 set_irq_handler(j, handle_simple_irq);
1877 set_irq_flags(j, IRQF_VALID);
1879 set_irq_chained_handler(bank->irq, gpio_irq_handler);
1880 set_irq_data(bank->irq, bank);
1882 if (cpu_is_omap34xx() || cpu_is_omap44xx()) {
1883 sprintf(clk_name, "gpio%d_dbck", i + 1);
1884 bank->dbck = clk_get(NULL, clk_name);
1885 if (IS_ERR(bank->dbck))
1886 printk(KERN_ERR "Could not get %s\n", clk_name);
1890 /* Enable system clock for GPIO module.
1891 * The CAM_CLK_CTRL *is* really the right place. */
1892 if (cpu_is_omap16xx())
1893 omap_writel(omap_readl(ULPD_CAM_CLK_CTRL) | 0x04, ULPD_CAM_CLK_CTRL);
1895 /* Enable autoidle for the OCP interface */
1896 if (cpu_is_omap24xx())
1897 omap_writel(1 << 0, 0x48019010);
1898 if (cpu_is_omap34xx())
1899 omap_writel(1 << 0, 0x48306814);
1901 omap_gpio_show_rev();
1906 #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP24XX) || \
1907 defined(CONFIG_ARCH_OMAP34XX) || defined(CONFIG_ARCH_OMAP4)
1908 static int omap_gpio_suspend(struct sys_device *dev, pm_message_t mesg)
1912 if (!cpu_class_is_omap2() && !cpu_is_omap16xx())
1915 for (i = 0; i < gpio_bank_count; i++) {
1916 struct gpio_bank *bank = &gpio_bank[i];
1917 void __iomem *wake_status;
1918 void __iomem *wake_clear;
1919 void __iomem *wake_set;
1920 unsigned long flags;
1922 switch (bank->method) {
1923 #ifdef CONFIG_ARCH_OMAP16XX
1924 case METHOD_GPIO_1610:
1925 wake_status = bank->base + OMAP1610_GPIO_WAKEUPENABLE;
1926 wake_clear = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
1927 wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA;
1930 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1931 case METHOD_GPIO_24XX:
1932 wake_status = bank->base + OMAP24XX_GPIO_WAKE_EN;
1933 wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
1934 wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA;
1937 #ifdef CONFIG_ARCH_OMAP4
1938 case METHOD_GPIO_24XX:
1939 wake_status = bank->base + OMAP4_GPIO_IRQWAKEN0;
1940 wake_clear = bank->base + OMAP4_GPIO_IRQWAKEN0;
1941 wake_set = bank->base + OMAP4_GPIO_IRQWAKEN0;
1948 spin_lock_irqsave(&bank->lock, flags);
1949 bank->saved_wakeup = __raw_readl(wake_status);
1950 __raw_writel(0xffffffff, wake_clear);
1951 __raw_writel(bank->suspend_wakeup, wake_set);
1952 spin_unlock_irqrestore(&bank->lock, flags);
1958 static int omap_gpio_resume(struct sys_device *dev)
1962 if (!cpu_class_is_omap2() && !cpu_is_omap16xx())
1965 for (i = 0; i < gpio_bank_count; i++) {
1966 struct gpio_bank *bank = &gpio_bank[i];
1967 void __iomem *wake_clear;
1968 void __iomem *wake_set;
1969 unsigned long flags;
1971 switch (bank->method) {
1972 #ifdef CONFIG_ARCH_OMAP16XX
1973 case METHOD_GPIO_1610:
1974 wake_clear = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
1975 wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA;
1978 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1979 case METHOD_GPIO_24XX:
1980 wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
1981 wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA;
1984 #ifdef CONFIG_ARCH_OMAP4
1985 case METHOD_GPIO_24XX:
1986 wake_clear = bank->base + OMAP4_GPIO_IRQWAKEN0;
1987 wake_set = bank->base + OMAP4_GPIO_IRQWAKEN0;
1994 spin_lock_irqsave(&bank->lock, flags);
1995 __raw_writel(0xffffffff, wake_clear);
1996 __raw_writel(bank->saved_wakeup, wake_set);
1997 spin_unlock_irqrestore(&bank->lock, flags);
2003 static struct sysdev_class omap_gpio_sysclass = {
2005 .suspend = omap_gpio_suspend,
2006 .resume = omap_gpio_resume,
2009 static struct sys_device omap_gpio_device = {
2011 .cls = &omap_gpio_sysclass,
2016 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
2017 defined(CONFIG_ARCH_OMAP4)
2019 static int workaround_enabled;
2021 void omap2_gpio_prepare_for_retention(void)
2025 /* Remove triggering for all non-wakeup GPIOs. Otherwise spurious
2026 * IRQs will be generated. See OMAP2420 Errata item 1.101. */
2027 for (i = 0; i < gpio_bank_count; i++) {
2028 struct gpio_bank *bank = &gpio_bank[i];
2031 if (!(bank->enabled_non_wakeup_gpios))
2033 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
2034 bank->saved_datain = __raw_readl(bank->base + OMAP24XX_GPIO_DATAIN);
2035 l1 = __raw_readl(bank->base + OMAP24XX_GPIO_FALLINGDETECT);
2036 l2 = __raw_readl(bank->base + OMAP24XX_GPIO_RISINGDETECT);
2038 #ifdef CONFIG_ARCH_OMAP4
2039 bank->saved_datain = __raw_readl(bank->base +
2041 l1 = __raw_readl(bank->base + OMAP4_GPIO_FALLINGDETECT);
2042 l2 = __raw_readl(bank->base + OMAP4_GPIO_RISINGDETECT);
2044 bank->saved_fallingdetect = l1;
2045 bank->saved_risingdetect = l2;
2046 l1 &= ~bank->enabled_non_wakeup_gpios;
2047 l2 &= ~bank->enabled_non_wakeup_gpios;
2048 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
2049 __raw_writel(l1, bank->base + OMAP24XX_GPIO_FALLINGDETECT);
2050 __raw_writel(l2, bank->base + OMAP24XX_GPIO_RISINGDETECT);
2052 #ifdef CONFIG_ARCH_OMAP4
2053 __raw_writel(l1, bank->base + OMAP4_GPIO_FALLINGDETECT);
2054 __raw_writel(l2, bank->base + OMAP4_GPIO_RISINGDETECT);
2059 workaround_enabled = 0;
2062 workaround_enabled = 1;
2065 void omap2_gpio_resume_after_retention(void)
2069 if (!workaround_enabled)
2071 for (i = 0; i < gpio_bank_count; i++) {
2072 struct gpio_bank *bank = &gpio_bank[i];
2073 u32 l, gen, gen0, gen1;
2075 if (!(bank->enabled_non_wakeup_gpios))
2077 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
2078 __raw_writel(bank->saved_fallingdetect,
2079 bank->base + OMAP24XX_GPIO_FALLINGDETECT);
2080 __raw_writel(bank->saved_risingdetect,
2081 bank->base + OMAP24XX_GPIO_RISINGDETECT);
2082 l = __raw_readl(bank->base + OMAP24XX_GPIO_DATAIN);
2084 #ifdef CONFIG_ARCH_OMAP4
2085 __raw_writel(bank->saved_fallingdetect,
2086 bank->base + OMAP4_GPIO_FALLINGDETECT);
2087 __raw_writel(bank->saved_risingdetect,
2088 bank->base + OMAP4_GPIO_RISINGDETECT);
2089 l = __raw_readl(bank->base + OMAP4_GPIO_DATAIN);
2091 /* Check if any of the non-wakeup interrupt GPIOs have changed
2092 * state. If so, generate an IRQ by software. This is
2093 * horribly racy, but it's the best we can do to work around
2094 * this silicon bug. */
2095 l ^= bank->saved_datain;
2096 l &= bank->non_wakeup_gpios;
2099 * No need to generate IRQs for the rising edge for gpio IRQs
2100 * configured with falling edge only; and vice versa.
2102 gen0 = l & bank->saved_fallingdetect;
2103 gen0 &= bank->saved_datain;
2105 gen1 = l & bank->saved_risingdetect;
2106 gen1 &= ~(bank->saved_datain);
2108 /* FIXME: Consider GPIO IRQs with level detections properly! */
2109 gen = l & (~(bank->saved_fallingdetect) &
2110 ~(bank->saved_risingdetect));
2111 /* Consider all GPIO IRQs needed to be updated */
2116 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
2117 old0 = __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0);
2118 old1 = __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1);
2119 __raw_writel(old0 | gen, bank->base +
2120 OMAP24XX_GPIO_LEVELDETECT0);
2121 __raw_writel(old1 | gen, bank->base +
2122 OMAP24XX_GPIO_LEVELDETECT1);
2123 __raw_writel(old0, bank->base + OMAP24XX_GPIO_LEVELDETECT0);
2124 __raw_writel(old1, bank->base + OMAP24XX_GPIO_LEVELDETECT1);
2126 #ifdef CONFIG_ARCH_OMAP4
2127 old0 = __raw_readl(bank->base +
2128 OMAP4_GPIO_LEVELDETECT0);
2129 old1 = __raw_readl(bank->base +
2130 OMAP4_GPIO_LEVELDETECT1);
2131 __raw_writel(old0 | l, bank->base +
2132 OMAP4_GPIO_LEVELDETECT0);
2133 __raw_writel(old1 | l, bank->base +
2134 OMAP4_GPIO_LEVELDETECT1);
2135 __raw_writel(old0, bank->base +
2136 OMAP4_GPIO_LEVELDETECT0);
2137 __raw_writel(old1, bank->base +
2138 OMAP4_GPIO_LEVELDETECT1);
2147 #ifdef CONFIG_ARCH_OMAP34XX
2148 /* save the registers of bank 2-6 */
2149 void omap_gpio_save_context(void)
2153 /* saving banks from 2-6 only since GPIO1 is in WKUP */
2154 for (i = 1; i < gpio_bank_count; i++) {
2155 struct gpio_bank *bank = &gpio_bank[i];
2156 gpio_context[i].sysconfig =
2157 __raw_readl(bank->base + OMAP24XX_GPIO_SYSCONFIG);
2158 gpio_context[i].irqenable1 =
2159 __raw_readl(bank->base + OMAP24XX_GPIO_IRQENABLE1);
2160 gpio_context[i].irqenable2 =
2161 __raw_readl(bank->base + OMAP24XX_GPIO_IRQENABLE2);
2162 gpio_context[i].wake_en =
2163 __raw_readl(bank->base + OMAP24XX_GPIO_WAKE_EN);
2164 gpio_context[i].ctrl =
2165 __raw_readl(bank->base + OMAP24XX_GPIO_CTRL);
2166 gpio_context[i].oe =
2167 __raw_readl(bank->base + OMAP24XX_GPIO_OE);
2168 gpio_context[i].leveldetect0 =
2169 __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0);
2170 gpio_context[i].leveldetect1 =
2171 __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1);
2172 gpio_context[i].risingdetect =
2173 __raw_readl(bank->base + OMAP24XX_GPIO_RISINGDETECT);
2174 gpio_context[i].fallingdetect =
2175 __raw_readl(bank->base + OMAP24XX_GPIO_FALLINGDETECT);
2176 gpio_context[i].dataout =
2177 __raw_readl(bank->base + OMAP24XX_GPIO_DATAOUT);
2178 gpio_context[i].setwkuena =
2179 __raw_readl(bank->base + OMAP24XX_GPIO_SETWKUENA);
2180 gpio_context[i].setdataout =
2181 __raw_readl(bank->base + OMAP24XX_GPIO_SETDATAOUT);
2185 /* restore the required registers of bank 2-6 */
2186 void omap_gpio_restore_context(void)
2190 for (i = 1; i < gpio_bank_count; i++) {
2191 struct gpio_bank *bank = &gpio_bank[i];
2192 __raw_writel(gpio_context[i].sysconfig,
2193 bank->base + OMAP24XX_GPIO_SYSCONFIG);
2194 __raw_writel(gpio_context[i].irqenable1,
2195 bank->base + OMAP24XX_GPIO_IRQENABLE1);
2196 __raw_writel(gpio_context[i].irqenable2,
2197 bank->base + OMAP24XX_GPIO_IRQENABLE2);
2198 __raw_writel(gpio_context[i].wake_en,
2199 bank->base + OMAP24XX_GPIO_WAKE_EN);
2200 __raw_writel(gpio_context[i].ctrl,
2201 bank->base + OMAP24XX_GPIO_CTRL);
2202 __raw_writel(gpio_context[i].oe,
2203 bank->base + OMAP24XX_GPIO_OE);
2204 __raw_writel(gpio_context[i].leveldetect0,
2205 bank->base + OMAP24XX_GPIO_LEVELDETECT0);
2206 __raw_writel(gpio_context[i].leveldetect1,
2207 bank->base + OMAP24XX_GPIO_LEVELDETECT1);
2208 __raw_writel(gpio_context[i].risingdetect,
2209 bank->base + OMAP24XX_GPIO_RISINGDETECT);
2210 __raw_writel(gpio_context[i].fallingdetect,
2211 bank->base + OMAP24XX_GPIO_FALLINGDETECT);
2212 __raw_writel(gpio_context[i].dataout,
2213 bank->base + OMAP24XX_GPIO_DATAOUT);
2214 __raw_writel(gpio_context[i].setwkuena,
2215 bank->base + OMAP24XX_GPIO_SETWKUENA);
2216 __raw_writel(gpio_context[i].setdataout,
2217 bank->base + OMAP24XX_GPIO_SETDATAOUT);
2223 * This may get called early from board specific init
2224 * for boards that have interrupts routed via FPGA.
2226 int __init omap_gpio_init(void)
2229 return _omap_gpio_init();
2234 static int __init omap_gpio_sysinit(void)
2239 ret = _omap_gpio_init();
2243 #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP24XX) || \
2244 defined(CONFIG_ARCH_OMAP34XX) || defined(CONFIG_ARCH_OMAP4)
2245 if (cpu_is_omap16xx() || cpu_class_is_omap2()) {
2247 ret = sysdev_class_register(&omap_gpio_sysclass);
2249 ret = sysdev_register(&omap_gpio_device);
2257 arch_initcall(omap_gpio_sysinit);
2260 #ifdef CONFIG_DEBUG_FS
2262 #include <linux/debugfs.h>
2263 #include <linux/seq_file.h>
2265 static int dbg_gpio_show(struct seq_file *s, void *unused)
2267 unsigned i, j, gpio;
2269 for (i = 0, gpio = 0; i < gpio_bank_count; i++) {
2270 struct gpio_bank *bank = gpio_bank + i;
2271 unsigned bankwidth = 16;
2274 if (bank_is_mpuio(bank))
2275 gpio = OMAP_MPUIO(0);
2276 else if (cpu_class_is_omap2() || cpu_is_omap7xx())
2279 for (j = 0; j < bankwidth; j++, gpio++, mask <<= 1) {
2280 unsigned irq, value, is_in, irqstat;
2283 label = gpiochip_is_requested(&bank->chip, j);
2287 irq = bank->virtual_irq_start + j;
2288 value = gpio_get_value(gpio);
2289 is_in = gpio_is_input(bank, mask);
2291 if (bank_is_mpuio(bank))
2292 seq_printf(s, "MPUIO %2d ", j);
2294 seq_printf(s, "GPIO %3d ", gpio);
2295 seq_printf(s, "(%-20.20s): %s %s",
2297 is_in ? "in " : "out",
2298 value ? "hi" : "lo");
2300 /* FIXME for at least omap2, show pullup/pulldown state */
2302 irqstat = irq_desc[irq].status;
2303 #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP24XX) || \
2304 defined(CONFIG_ARCH_OMAP34XX) || defined(CONFIG_ARCH_OMAP4)
2305 if (is_in && ((bank->suspend_wakeup & mask)
2306 || irqstat & IRQ_TYPE_SENSE_MASK)) {
2307 char *trigger = NULL;
2309 switch (irqstat & IRQ_TYPE_SENSE_MASK) {
2310 case IRQ_TYPE_EDGE_FALLING:
2311 trigger = "falling";
2313 case IRQ_TYPE_EDGE_RISING:
2316 case IRQ_TYPE_EDGE_BOTH:
2317 trigger = "bothedge";
2319 case IRQ_TYPE_LEVEL_LOW:
2322 case IRQ_TYPE_LEVEL_HIGH:
2329 seq_printf(s, ", irq-%d %-8s%s",
2331 (bank->suspend_wakeup & mask)
2335 seq_printf(s, "\n");
2338 if (bank_is_mpuio(bank)) {
2339 seq_printf(s, "\n");
2346 static int dbg_gpio_open(struct inode *inode, struct file *file)
2348 return single_open(file, dbg_gpio_show, &inode->i_private);
2351 static const struct file_operations debug_fops = {
2352 .open = dbg_gpio_open,
2354 .llseek = seq_lseek,
2355 .release = single_release,
2358 static int __init omap_gpio_debuginit(void)
2360 (void) debugfs_create_file("omap_gpio", S_IRUGO,
2361 NULL, NULL, &debug_fops);
2364 late_initcall(omap_gpio_debuginit);