2 * linux/arch/arm/plat-omap/gpio.c
4 * Support functions for OMAP GPIO
6 * Copyright (C) 2003-2005 Nokia Corporation
7 * Written by Juha Yrjölä <juha.yrjola@nokia.com>
9 * Copyright (C) 2009 Texas Instruments
10 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation.
17 #include <linux/init.h>
18 #include <linux/module.h>
19 #include <linux/interrupt.h>
20 #include <linux/sysdev.h>
21 #include <linux/err.h>
22 #include <linux/clk.h>
25 #include <mach/hardware.h>
27 #include <mach/irqs.h>
28 #include <mach/gpio.h>
29 #include <asm/mach/irq.h>
32 * OMAP1510 GPIO registers
34 #define OMAP1510_GPIO_BASE IO_ADDRESS(0xfffce000)
35 #define OMAP1510_GPIO_DATA_INPUT 0x00
36 #define OMAP1510_GPIO_DATA_OUTPUT 0x04
37 #define OMAP1510_GPIO_DIR_CONTROL 0x08
38 #define OMAP1510_GPIO_INT_CONTROL 0x0c
39 #define OMAP1510_GPIO_INT_MASK 0x10
40 #define OMAP1510_GPIO_INT_STATUS 0x14
41 #define OMAP1510_GPIO_PIN_CONTROL 0x18
43 #define OMAP1510_IH_GPIO_BASE 64
46 * OMAP1610 specific GPIO registers
48 #define OMAP1610_GPIO1_BASE IO_ADDRESS(0xfffbe400)
49 #define OMAP1610_GPIO2_BASE IO_ADDRESS(0xfffbec00)
50 #define OMAP1610_GPIO3_BASE IO_ADDRESS(0xfffbb400)
51 #define OMAP1610_GPIO4_BASE IO_ADDRESS(0xfffbbc00)
52 #define OMAP1610_GPIO_REVISION 0x0000
53 #define OMAP1610_GPIO_SYSCONFIG 0x0010
54 #define OMAP1610_GPIO_SYSSTATUS 0x0014
55 #define OMAP1610_GPIO_IRQSTATUS1 0x0018
56 #define OMAP1610_GPIO_IRQENABLE1 0x001c
57 #define OMAP1610_GPIO_WAKEUPENABLE 0x0028
58 #define OMAP1610_GPIO_DATAIN 0x002c
59 #define OMAP1610_GPIO_DATAOUT 0x0030
60 #define OMAP1610_GPIO_DIRECTION 0x0034
61 #define OMAP1610_GPIO_EDGE_CTRL1 0x0038
62 #define OMAP1610_GPIO_EDGE_CTRL2 0x003c
63 #define OMAP1610_GPIO_CLEAR_IRQENABLE1 0x009c
64 #define OMAP1610_GPIO_CLEAR_WAKEUPENA 0x00a8
65 #define OMAP1610_GPIO_CLEAR_DATAOUT 0x00b0
66 #define OMAP1610_GPIO_SET_IRQENABLE1 0x00dc
67 #define OMAP1610_GPIO_SET_WAKEUPENA 0x00e8
68 #define OMAP1610_GPIO_SET_DATAOUT 0x00f0
71 * OMAP730 specific GPIO registers
73 #define OMAP730_GPIO1_BASE IO_ADDRESS(0xfffbc000)
74 #define OMAP730_GPIO2_BASE IO_ADDRESS(0xfffbc800)
75 #define OMAP730_GPIO3_BASE IO_ADDRESS(0xfffbd000)
76 #define OMAP730_GPIO4_BASE IO_ADDRESS(0xfffbd800)
77 #define OMAP730_GPIO5_BASE IO_ADDRESS(0xfffbe000)
78 #define OMAP730_GPIO6_BASE IO_ADDRESS(0xfffbe800)
79 #define OMAP730_GPIO_DATA_INPUT 0x00
80 #define OMAP730_GPIO_DATA_OUTPUT 0x04
81 #define OMAP730_GPIO_DIR_CONTROL 0x08
82 #define OMAP730_GPIO_INT_CONTROL 0x0c
83 #define OMAP730_GPIO_INT_MASK 0x10
84 #define OMAP730_GPIO_INT_STATUS 0x14
87 * OMAP850 specific GPIO registers
89 #define OMAP850_GPIO1_BASE IO_ADDRESS(0xfffbc000)
90 #define OMAP850_GPIO2_BASE IO_ADDRESS(0xfffbc800)
91 #define OMAP850_GPIO3_BASE IO_ADDRESS(0xfffbd000)
92 #define OMAP850_GPIO4_BASE IO_ADDRESS(0xfffbd800)
93 #define OMAP850_GPIO5_BASE IO_ADDRESS(0xfffbe000)
94 #define OMAP850_GPIO6_BASE IO_ADDRESS(0xfffbe800)
95 #define OMAP850_GPIO_DATA_INPUT 0x00
96 #define OMAP850_GPIO_DATA_OUTPUT 0x04
97 #define OMAP850_GPIO_DIR_CONTROL 0x08
98 #define OMAP850_GPIO_INT_CONTROL 0x0c
99 #define OMAP850_GPIO_INT_MASK 0x10
100 #define OMAP850_GPIO_INT_STATUS 0x14
103 * omap24xx specific GPIO registers
105 #define OMAP242X_GPIO1_BASE IO_ADDRESS(0x48018000)
106 #define OMAP242X_GPIO2_BASE IO_ADDRESS(0x4801a000)
107 #define OMAP242X_GPIO3_BASE IO_ADDRESS(0x4801c000)
108 #define OMAP242X_GPIO4_BASE IO_ADDRESS(0x4801e000)
110 #define OMAP243X_GPIO1_BASE IO_ADDRESS(0x4900C000)
111 #define OMAP243X_GPIO2_BASE IO_ADDRESS(0x4900E000)
112 #define OMAP243X_GPIO3_BASE IO_ADDRESS(0x49010000)
113 #define OMAP243X_GPIO4_BASE IO_ADDRESS(0x49012000)
114 #define OMAP243X_GPIO5_BASE IO_ADDRESS(0x480B6000)
116 #define OMAP24XX_GPIO_REVISION 0x0000
117 #define OMAP24XX_GPIO_SYSCONFIG 0x0010
118 #define OMAP24XX_GPIO_SYSSTATUS 0x0014
119 #define OMAP24XX_GPIO_IRQSTATUS1 0x0018
120 #define OMAP24XX_GPIO_IRQSTATUS2 0x0028
121 #define OMAP24XX_GPIO_IRQENABLE2 0x002c
122 #define OMAP24XX_GPIO_IRQENABLE1 0x001c
123 #define OMAP24XX_GPIO_WAKE_EN 0x0020
124 #define OMAP24XX_GPIO_CTRL 0x0030
125 #define OMAP24XX_GPIO_OE 0x0034
126 #define OMAP24XX_GPIO_DATAIN 0x0038
127 #define OMAP24XX_GPIO_DATAOUT 0x003c
128 #define OMAP24XX_GPIO_LEVELDETECT0 0x0040
129 #define OMAP24XX_GPIO_LEVELDETECT1 0x0044
130 #define OMAP24XX_GPIO_RISINGDETECT 0x0048
131 #define OMAP24XX_GPIO_FALLINGDETECT 0x004c
132 #define OMAP24XX_GPIO_DEBOUNCE_EN 0x0050
133 #define OMAP24XX_GPIO_DEBOUNCE_VAL 0x0054
134 #define OMAP24XX_GPIO_CLEARIRQENABLE1 0x0060
135 #define OMAP24XX_GPIO_SETIRQENABLE1 0x0064
136 #define OMAP24XX_GPIO_CLEARWKUENA 0x0080
137 #define OMAP24XX_GPIO_SETWKUENA 0x0084
138 #define OMAP24XX_GPIO_CLEARDATAOUT 0x0090
139 #define OMAP24XX_GPIO_SETDATAOUT 0x0094
142 * omap34xx specific GPIO registers
145 #define OMAP34XX_GPIO1_BASE IO_ADDRESS(0x48310000)
146 #define OMAP34XX_GPIO2_BASE IO_ADDRESS(0x49050000)
147 #define OMAP34XX_GPIO3_BASE IO_ADDRESS(0x49052000)
148 #define OMAP34XX_GPIO4_BASE IO_ADDRESS(0x49054000)
149 #define OMAP34XX_GPIO5_BASE IO_ADDRESS(0x49056000)
150 #define OMAP34XX_GPIO6_BASE IO_ADDRESS(0x49058000)
153 * OMAP44XX specific GPIO registers
155 #define OMAP44XX_GPIO1_BASE IO_ADDRESS(0x4a310000)
156 #define OMAP44XX_GPIO2_BASE IO_ADDRESS(0x48055000)
157 #define OMAP44XX_GPIO3_BASE IO_ADDRESS(0x48057000)
158 #define OMAP44XX_GPIO4_BASE IO_ADDRESS(0x48059000)
159 #define OMAP44XX_GPIO5_BASE IO_ADDRESS(0x4805B000)
160 #define OMAP44XX_GPIO6_BASE IO_ADDRESS(0x4805D000)
162 #define OMAP_MPUIO_VBASE IO_ADDRESS(OMAP_MPUIO_BASE)
167 u16 virtual_irq_start;
169 #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP24XX) || \
170 defined(CONFIG_ARCH_OMAP34XX) || defined(CONFIG_ARCH_OMAP4)
174 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
175 defined(CONFIG_ARCH_OMAP4)
176 u32 non_wakeup_gpios;
177 u32 enabled_non_wakeup_gpios;
180 u32 saved_fallingdetect;
181 u32 saved_risingdetect;
185 struct gpio_chip chip;
189 #define METHOD_MPUIO 0
190 #define METHOD_GPIO_1510 1
191 #define METHOD_GPIO_1610 2
192 #define METHOD_GPIO_730 3
193 #define METHOD_GPIO_850 4
194 #define METHOD_GPIO_24XX 5
196 #ifdef CONFIG_ARCH_OMAP16XX
197 static struct gpio_bank gpio_bank_1610[5] = {
198 { OMAP_MPUIO_VBASE, INT_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO},
199 { OMAP1610_GPIO1_BASE, INT_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_1610 },
200 { OMAP1610_GPIO2_BASE, INT_1610_GPIO_BANK2, IH_GPIO_BASE + 16, METHOD_GPIO_1610 },
201 { OMAP1610_GPIO3_BASE, INT_1610_GPIO_BANK3, IH_GPIO_BASE + 32, METHOD_GPIO_1610 },
202 { OMAP1610_GPIO4_BASE, INT_1610_GPIO_BANK4, IH_GPIO_BASE + 48, METHOD_GPIO_1610 },
206 #ifdef CONFIG_ARCH_OMAP15XX
207 static struct gpio_bank gpio_bank_1510[2] = {
208 { OMAP_MPUIO_VBASE, INT_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO },
209 { OMAP1510_GPIO_BASE, INT_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_1510 }
213 #ifdef CONFIG_ARCH_OMAP730
214 static struct gpio_bank gpio_bank_730[7] = {
215 { OMAP_MPUIO_VBASE, INT_730_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO },
216 { OMAP730_GPIO1_BASE, INT_730_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_730 },
217 { OMAP730_GPIO2_BASE, INT_730_GPIO_BANK2, IH_GPIO_BASE + 32, METHOD_GPIO_730 },
218 { OMAP730_GPIO3_BASE, INT_730_GPIO_BANK3, IH_GPIO_BASE + 64, METHOD_GPIO_730 },
219 { OMAP730_GPIO4_BASE, INT_730_GPIO_BANK4, IH_GPIO_BASE + 96, METHOD_GPIO_730 },
220 { OMAP730_GPIO5_BASE, INT_730_GPIO_BANK5, IH_GPIO_BASE + 128, METHOD_GPIO_730 },
221 { OMAP730_GPIO6_BASE, INT_730_GPIO_BANK6, IH_GPIO_BASE + 160, METHOD_GPIO_730 },
225 #ifdef CONFIG_ARCH_OMAP850
226 static struct gpio_bank gpio_bank_850[7] = {
227 { OMAP_MPUIO_BASE, INT_850_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO },
228 { OMAP850_GPIO1_BASE, INT_850_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_850 },
229 { OMAP850_GPIO2_BASE, INT_850_GPIO_BANK2, IH_GPIO_BASE + 32, METHOD_GPIO_850 },
230 { OMAP850_GPIO3_BASE, INT_850_GPIO_BANK3, IH_GPIO_BASE + 64, METHOD_GPIO_850 },
231 { OMAP850_GPIO4_BASE, INT_850_GPIO_BANK4, IH_GPIO_BASE + 96, METHOD_GPIO_850 },
232 { OMAP850_GPIO5_BASE, INT_850_GPIO_BANK5, IH_GPIO_BASE + 128, METHOD_GPIO_850 },
233 { OMAP850_GPIO6_BASE, INT_850_GPIO_BANK6, IH_GPIO_BASE + 160, METHOD_GPIO_850 },
238 #ifdef CONFIG_ARCH_OMAP24XX
240 static struct gpio_bank gpio_bank_242x[4] = {
241 { OMAP242X_GPIO1_BASE, INT_24XX_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_24XX },
242 { OMAP242X_GPIO2_BASE, INT_24XX_GPIO_BANK2, IH_GPIO_BASE + 32, METHOD_GPIO_24XX },
243 { OMAP242X_GPIO3_BASE, INT_24XX_GPIO_BANK3, IH_GPIO_BASE + 64, METHOD_GPIO_24XX },
244 { OMAP242X_GPIO4_BASE, INT_24XX_GPIO_BANK4, IH_GPIO_BASE + 96, METHOD_GPIO_24XX },
247 static struct gpio_bank gpio_bank_243x[5] = {
248 { OMAP243X_GPIO1_BASE, INT_24XX_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_24XX },
249 { OMAP243X_GPIO2_BASE, INT_24XX_GPIO_BANK2, IH_GPIO_BASE + 32, METHOD_GPIO_24XX },
250 { OMAP243X_GPIO3_BASE, INT_24XX_GPIO_BANK3, IH_GPIO_BASE + 64, METHOD_GPIO_24XX },
251 { OMAP243X_GPIO4_BASE, INT_24XX_GPIO_BANK4, IH_GPIO_BASE + 96, METHOD_GPIO_24XX },
252 { OMAP243X_GPIO5_BASE, INT_24XX_GPIO_BANK5, IH_GPIO_BASE + 128, METHOD_GPIO_24XX },
257 #ifdef CONFIG_ARCH_OMAP34XX
258 static struct gpio_bank gpio_bank_34xx[6] = {
259 { OMAP34XX_GPIO1_BASE, INT_34XX_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_24XX },
260 { OMAP34XX_GPIO2_BASE, INT_34XX_GPIO_BANK2, IH_GPIO_BASE + 32, METHOD_GPIO_24XX },
261 { OMAP34XX_GPIO3_BASE, INT_34XX_GPIO_BANK3, IH_GPIO_BASE + 64, METHOD_GPIO_24XX },
262 { OMAP34XX_GPIO4_BASE, INT_34XX_GPIO_BANK4, IH_GPIO_BASE + 96, METHOD_GPIO_24XX },
263 { OMAP34XX_GPIO5_BASE, INT_34XX_GPIO_BANK5, IH_GPIO_BASE + 128, METHOD_GPIO_24XX },
264 { OMAP34XX_GPIO6_BASE, INT_34XX_GPIO_BANK6, IH_GPIO_BASE + 160, METHOD_GPIO_24XX },
269 #ifdef CONFIG_ARCH_OMAP4
270 static struct gpio_bank gpio_bank_44xx[6] = {
271 { OMAP44XX_GPIO1_BASE, INT_44XX_GPIO_BANK1, IH_GPIO_BASE, \
273 { OMAP44XX_GPIO2_BASE, INT_44XX_GPIO_BANK2, IH_GPIO_BASE + 32, \
275 { OMAP44XX_GPIO3_BASE, INT_44XX_GPIO_BANK3, IH_GPIO_BASE + 64, \
277 { OMAP44XX_GPIO4_BASE, INT_44XX_GPIO_BANK4, IH_GPIO_BASE + 96, \
279 { OMAP44XX_GPIO5_BASE, INT_44XX_GPIO_BANK5, IH_GPIO_BASE + 128, \
281 { OMAP44XX_GPIO6_BASE, INT_44XX_GPIO_BANK6, IH_GPIO_BASE + 160, \
287 static struct gpio_bank *gpio_bank;
288 static int gpio_bank_count;
290 static inline struct gpio_bank *get_gpio_bank(int gpio)
292 if (cpu_is_omap15xx()) {
293 if (OMAP_GPIO_IS_MPUIO(gpio))
294 return &gpio_bank[0];
295 return &gpio_bank[1];
297 if (cpu_is_omap16xx()) {
298 if (OMAP_GPIO_IS_MPUIO(gpio))
299 return &gpio_bank[0];
300 return &gpio_bank[1 + (gpio >> 4)];
302 if (cpu_is_omap7xx()) {
303 if (OMAP_GPIO_IS_MPUIO(gpio))
304 return &gpio_bank[0];
305 return &gpio_bank[1 + (gpio >> 5)];
307 if (cpu_is_omap24xx())
308 return &gpio_bank[gpio >> 5];
309 if (cpu_is_omap34xx() || cpu_is_omap44xx())
310 return &gpio_bank[gpio >> 5];
315 static inline int get_gpio_index(int gpio)
317 if (cpu_is_omap7xx())
319 if (cpu_is_omap24xx())
321 if (cpu_is_omap34xx() || cpu_is_omap44xx())
326 static inline int gpio_valid(int gpio)
330 if (cpu_class_is_omap1() && OMAP_GPIO_IS_MPUIO(gpio)) {
331 if (gpio >= OMAP_MAX_GPIO_LINES + 16)
335 if (cpu_is_omap15xx() && gpio < 16)
337 if ((cpu_is_omap16xx()) && gpio < 64)
339 if (cpu_is_omap7xx() && gpio < 192)
341 if (cpu_is_omap24xx() && gpio < 128)
343 if ((cpu_is_omap34xx() || cpu_is_omap44xx()) && gpio < 192)
348 static int check_gpio(int gpio)
350 if (unlikely(gpio_valid(gpio)) < 0) {
351 printk(KERN_ERR "omap-gpio: invalid GPIO %d\n", gpio);
358 static void _set_gpio_direction(struct gpio_bank *bank, int gpio, int is_input)
360 void __iomem *reg = bank->base;
363 switch (bank->method) {
364 #ifdef CONFIG_ARCH_OMAP1
366 reg += OMAP_MPUIO_IO_CNTL;
369 #ifdef CONFIG_ARCH_OMAP15XX
370 case METHOD_GPIO_1510:
371 reg += OMAP1510_GPIO_DIR_CONTROL;
374 #ifdef CONFIG_ARCH_OMAP16XX
375 case METHOD_GPIO_1610:
376 reg += OMAP1610_GPIO_DIRECTION;
379 #ifdef CONFIG_ARCH_OMAP730
380 case METHOD_GPIO_730:
381 reg += OMAP730_GPIO_DIR_CONTROL;
384 #ifdef CONFIG_ARCH_OMAP850
385 case METHOD_GPIO_850:
386 reg += OMAP850_GPIO_DIR_CONTROL;
389 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
390 defined(CONFIG_ARCH_OMAP4)
391 case METHOD_GPIO_24XX:
392 reg += OMAP24XX_GPIO_OE;
399 l = __raw_readl(reg);
404 __raw_writel(l, reg);
407 static void _set_gpio_dataout(struct gpio_bank *bank, int gpio, int enable)
409 void __iomem *reg = bank->base;
412 switch (bank->method) {
413 #ifdef CONFIG_ARCH_OMAP1
415 reg += OMAP_MPUIO_OUTPUT;
416 l = __raw_readl(reg);
423 #ifdef CONFIG_ARCH_OMAP15XX
424 case METHOD_GPIO_1510:
425 reg += OMAP1510_GPIO_DATA_OUTPUT;
426 l = __raw_readl(reg);
433 #ifdef CONFIG_ARCH_OMAP16XX
434 case METHOD_GPIO_1610:
436 reg += OMAP1610_GPIO_SET_DATAOUT;
438 reg += OMAP1610_GPIO_CLEAR_DATAOUT;
442 #ifdef CONFIG_ARCH_OMAP730
443 case METHOD_GPIO_730:
444 reg += OMAP730_GPIO_DATA_OUTPUT;
445 l = __raw_readl(reg);
452 #ifdef CONFIG_ARCH_OMAP850
453 case METHOD_GPIO_850:
454 reg += OMAP850_GPIO_DATA_OUTPUT;
455 l = __raw_readl(reg);
462 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
463 defined(CONFIG_ARCH_OMAP4)
464 case METHOD_GPIO_24XX:
466 reg += OMAP24XX_GPIO_SETDATAOUT;
468 reg += OMAP24XX_GPIO_CLEARDATAOUT;
476 __raw_writel(l, reg);
479 static int _get_gpio_datain(struct gpio_bank *bank, int gpio)
483 if (check_gpio(gpio) < 0)
486 switch (bank->method) {
487 #ifdef CONFIG_ARCH_OMAP1
489 reg += OMAP_MPUIO_INPUT_LATCH;
492 #ifdef CONFIG_ARCH_OMAP15XX
493 case METHOD_GPIO_1510:
494 reg += OMAP1510_GPIO_DATA_INPUT;
497 #ifdef CONFIG_ARCH_OMAP16XX
498 case METHOD_GPIO_1610:
499 reg += OMAP1610_GPIO_DATAIN;
502 #ifdef CONFIG_ARCH_OMAP730
503 case METHOD_GPIO_730:
504 reg += OMAP730_GPIO_DATA_INPUT;
507 #ifdef CONFIG_ARCH_OMAP850
508 case METHOD_GPIO_850:
509 reg += OMAP850_GPIO_DATA_INPUT;
512 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
513 defined(CONFIG_ARCH_OMAP4)
514 case METHOD_GPIO_24XX:
515 reg += OMAP24XX_GPIO_DATAIN;
521 return (__raw_readl(reg)
522 & (1 << get_gpio_index(gpio))) != 0;
525 static int _get_gpio_dataout(struct gpio_bank *bank, int gpio)
529 if (check_gpio(gpio) < 0)
533 switch (bank->method) {
534 #ifdef CONFIG_ARCH_OMAP1
536 reg += OMAP_MPUIO_OUTPUT;
539 #ifdef CONFIG_ARCH_OMAP15XX
540 case METHOD_GPIO_1510:
541 reg += OMAP1510_GPIO_DATA_OUTPUT;
544 #ifdef CONFIG_ARCH_OMAP16XX
545 case METHOD_GPIO_1610:
546 reg += OMAP1610_GPIO_DATAOUT;
549 #ifdef CONFIG_ARCH_OMAP730
550 case METHOD_GPIO_730:
551 reg += OMAP730_GPIO_DATA_OUTPUT;
554 #ifdef CONFIG_ARCH_OMAP850
555 case METHOD_GPIO_850:
556 reg += OMAP850_GPIO_DATA_OUTPUT;
559 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
560 defined(CONFIG_ARCH_OMAP4)
561 case METHOD_GPIO_24XX:
562 reg += OMAP24XX_GPIO_DATAOUT;
569 return (__raw_readl(reg) & (1 << get_gpio_index(gpio))) != 0;
572 #define MOD_REG_BIT(reg, bit_mask, set) \
574 int l = __raw_readl(base + reg); \
575 if (set) l |= bit_mask; \
576 else l &= ~bit_mask; \
577 __raw_writel(l, base + reg); \
580 void omap_set_gpio_debounce(int gpio, int enable)
582 struct gpio_bank *bank;
585 u32 val, l = 1 << get_gpio_index(gpio);
587 if (cpu_class_is_omap1())
590 bank = get_gpio_bank(gpio);
592 reg += OMAP24XX_GPIO_DEBOUNCE_EN;
594 spin_lock_irqsave(&bank->lock, flags);
595 val = __raw_readl(reg);
597 if (enable && !(val & l))
599 else if (!enable && (val & l))
604 if (cpu_is_omap34xx() || cpu_is_omap44xx()) {
606 clk_enable(bank->dbck);
608 clk_disable(bank->dbck);
611 __raw_writel(val, reg);
613 spin_unlock_irqrestore(&bank->lock, flags);
615 EXPORT_SYMBOL(omap_set_gpio_debounce);
617 void omap_set_gpio_debounce_time(int gpio, int enc_time)
619 struct gpio_bank *bank;
622 if (cpu_class_is_omap1())
625 bank = get_gpio_bank(gpio);
629 reg += OMAP24XX_GPIO_DEBOUNCE_VAL;
630 __raw_writel(enc_time, reg);
632 EXPORT_SYMBOL(omap_set_gpio_debounce_time);
634 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
635 defined(CONFIG_ARCH_OMAP4)
636 static inline void set_24xx_gpio_triggering(struct gpio_bank *bank, int gpio,
639 void __iomem *base = bank->base;
640 u32 gpio_bit = 1 << gpio;
642 MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT0, gpio_bit,
643 trigger & IRQ_TYPE_LEVEL_LOW);
644 MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT1, gpio_bit,
645 trigger & IRQ_TYPE_LEVEL_HIGH);
646 MOD_REG_BIT(OMAP24XX_GPIO_RISINGDETECT, gpio_bit,
647 trigger & IRQ_TYPE_EDGE_RISING);
648 MOD_REG_BIT(OMAP24XX_GPIO_FALLINGDETECT, gpio_bit,
649 trigger & IRQ_TYPE_EDGE_FALLING);
651 if (likely(!(bank->non_wakeup_gpios & gpio_bit))) {
653 __raw_writel(1 << gpio, bank->base
654 + OMAP24XX_GPIO_SETWKUENA);
656 __raw_writel(1 << gpio, bank->base
657 + OMAP24XX_GPIO_CLEARWKUENA);
660 bank->enabled_non_wakeup_gpios |= gpio_bit;
662 bank->enabled_non_wakeup_gpios &= ~gpio_bit;
666 __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0) |
667 __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1);
671 static int _set_gpio_triggering(struct gpio_bank *bank, int gpio, int trigger)
673 void __iomem *reg = bank->base;
676 switch (bank->method) {
677 #ifdef CONFIG_ARCH_OMAP1
679 reg += OMAP_MPUIO_GPIO_INT_EDGE;
680 l = __raw_readl(reg);
681 if (trigger & IRQ_TYPE_EDGE_RISING)
683 else if (trigger & IRQ_TYPE_EDGE_FALLING)
689 #ifdef CONFIG_ARCH_OMAP15XX
690 case METHOD_GPIO_1510:
691 reg += OMAP1510_GPIO_INT_CONTROL;
692 l = __raw_readl(reg);
693 if (trigger & IRQ_TYPE_EDGE_RISING)
695 else if (trigger & IRQ_TYPE_EDGE_FALLING)
701 #ifdef CONFIG_ARCH_OMAP16XX
702 case METHOD_GPIO_1610:
704 reg += OMAP1610_GPIO_EDGE_CTRL2;
706 reg += OMAP1610_GPIO_EDGE_CTRL1;
708 l = __raw_readl(reg);
709 l &= ~(3 << (gpio << 1));
710 if (trigger & IRQ_TYPE_EDGE_RISING)
711 l |= 2 << (gpio << 1);
712 if (trigger & IRQ_TYPE_EDGE_FALLING)
713 l |= 1 << (gpio << 1);
715 /* Enable wake-up during idle for dynamic tick */
716 __raw_writel(1 << gpio, bank->base + OMAP1610_GPIO_SET_WAKEUPENA);
718 __raw_writel(1 << gpio, bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA);
721 #ifdef CONFIG_ARCH_OMAP730
722 case METHOD_GPIO_730:
723 reg += OMAP730_GPIO_INT_CONTROL;
724 l = __raw_readl(reg);
725 if (trigger & IRQ_TYPE_EDGE_RISING)
727 else if (trigger & IRQ_TYPE_EDGE_FALLING)
733 #ifdef CONFIG_ARCH_OMAP850
734 case METHOD_GPIO_850:
735 reg += OMAP850_GPIO_INT_CONTROL;
736 l = __raw_readl(reg);
737 if (trigger & IRQ_TYPE_EDGE_RISING)
739 else if (trigger & IRQ_TYPE_EDGE_FALLING)
745 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
746 defined(CONFIG_ARCH_OMAP4)
747 case METHOD_GPIO_24XX:
748 set_24xx_gpio_triggering(bank, gpio, trigger);
754 __raw_writel(l, reg);
760 static int gpio_irq_type(unsigned irq, unsigned type)
762 struct gpio_bank *bank;
767 if (!cpu_class_is_omap2() && irq > IH_MPUIO_BASE)
768 gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE);
770 gpio = irq - IH_GPIO_BASE;
772 if (check_gpio(gpio) < 0)
775 if (type & ~IRQ_TYPE_SENSE_MASK)
778 /* OMAP1 allows only only edge triggering */
779 if (!cpu_class_is_omap2()
780 && (type & (IRQ_TYPE_LEVEL_LOW|IRQ_TYPE_LEVEL_HIGH)))
783 bank = get_irq_chip_data(irq);
784 spin_lock_irqsave(&bank->lock, flags);
785 retval = _set_gpio_triggering(bank, get_gpio_index(gpio), type);
787 irq_desc[irq].status &= ~IRQ_TYPE_SENSE_MASK;
788 irq_desc[irq].status |= type;
790 spin_unlock_irqrestore(&bank->lock, flags);
792 if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
793 __set_irq_handler_unlocked(irq, handle_level_irq);
794 else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
795 __set_irq_handler_unlocked(irq, handle_edge_irq);
800 static void _clear_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
802 void __iomem *reg = bank->base;
804 switch (bank->method) {
805 #ifdef CONFIG_ARCH_OMAP1
807 /* MPUIO irqstatus is reset by reading the status register,
808 * so do nothing here */
811 #ifdef CONFIG_ARCH_OMAP15XX
812 case METHOD_GPIO_1510:
813 reg += OMAP1510_GPIO_INT_STATUS;
816 #ifdef CONFIG_ARCH_OMAP16XX
817 case METHOD_GPIO_1610:
818 reg += OMAP1610_GPIO_IRQSTATUS1;
821 #ifdef CONFIG_ARCH_OMAP730
822 case METHOD_GPIO_730:
823 reg += OMAP730_GPIO_INT_STATUS;
826 #ifdef CONFIG_ARCH_OMAP850
827 case METHOD_GPIO_850:
828 reg += OMAP850_GPIO_INT_STATUS;
831 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
832 defined(CONFIG_ARCH_OMAP4)
833 case METHOD_GPIO_24XX:
834 reg += OMAP24XX_GPIO_IRQSTATUS1;
841 __raw_writel(gpio_mask, reg);
843 /* Workaround for clearing DSP GPIO interrupts to allow retention */
844 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
845 reg = bank->base + OMAP24XX_GPIO_IRQSTATUS2;
846 if (cpu_is_omap24xx() || cpu_is_omap34xx())
847 __raw_writel(gpio_mask, reg);
849 /* Flush posted write for the irq status to avoid spurious interrupts */
854 static inline void _clear_gpio_irqstatus(struct gpio_bank *bank, int gpio)
856 _clear_gpio_irqbank(bank, 1 << get_gpio_index(gpio));
859 static u32 _get_gpio_irqbank_mask(struct gpio_bank *bank)
861 void __iomem *reg = bank->base;
866 switch (bank->method) {
867 #ifdef CONFIG_ARCH_OMAP1
869 reg += OMAP_MPUIO_GPIO_MASKIT;
874 #ifdef CONFIG_ARCH_OMAP15XX
875 case METHOD_GPIO_1510:
876 reg += OMAP1510_GPIO_INT_MASK;
881 #ifdef CONFIG_ARCH_OMAP16XX
882 case METHOD_GPIO_1610:
883 reg += OMAP1610_GPIO_IRQENABLE1;
887 #ifdef CONFIG_ARCH_OMAP730
888 case METHOD_GPIO_730:
889 reg += OMAP730_GPIO_INT_MASK;
894 #ifdef CONFIG_ARCH_OMAP850
895 case METHOD_GPIO_850:
896 reg += OMAP850_GPIO_INT_MASK;
901 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
902 defined(CONFIG_ARCH_OMAP4)
903 case METHOD_GPIO_24XX:
904 reg += OMAP24XX_GPIO_IRQENABLE1;
913 l = __raw_readl(reg);
920 static void _enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask, int enable)
922 void __iomem *reg = bank->base;
925 switch (bank->method) {
926 #ifdef CONFIG_ARCH_OMAP1
928 reg += OMAP_MPUIO_GPIO_MASKIT;
929 l = __raw_readl(reg);
936 #ifdef CONFIG_ARCH_OMAP15XX
937 case METHOD_GPIO_1510:
938 reg += OMAP1510_GPIO_INT_MASK;
939 l = __raw_readl(reg);
946 #ifdef CONFIG_ARCH_OMAP16XX
947 case METHOD_GPIO_1610:
949 reg += OMAP1610_GPIO_SET_IRQENABLE1;
951 reg += OMAP1610_GPIO_CLEAR_IRQENABLE1;
955 #ifdef CONFIG_ARCH_OMAP730
956 case METHOD_GPIO_730:
957 reg += OMAP730_GPIO_INT_MASK;
958 l = __raw_readl(reg);
965 #ifdef CONFIG_ARCH_OMAP850
966 case METHOD_GPIO_850:
967 reg += OMAP850_GPIO_INT_MASK;
968 l = __raw_readl(reg);
975 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
976 defined(CONFIG_ARCH_OMAP4)
977 case METHOD_GPIO_24XX:
979 reg += OMAP24XX_GPIO_SETIRQENABLE1;
981 reg += OMAP24XX_GPIO_CLEARIRQENABLE1;
989 __raw_writel(l, reg);
992 static inline void _set_gpio_irqenable(struct gpio_bank *bank, int gpio, int enable)
994 _enable_gpio_irqbank(bank, 1 << get_gpio_index(gpio), enable);
998 * Note that ENAWAKEUP needs to be enabled in GPIO_SYSCONFIG register.
999 * 1510 does not seem to have a wake-up register. If JTAG is connected
1000 * to the target, system will wake up always on GPIO events. While
1001 * system is running all registered GPIO interrupts need to have wake-up
1002 * enabled. When system is suspended, only selected GPIO interrupts need
1003 * to have wake-up enabled.
1005 static int _set_gpio_wakeup(struct gpio_bank *bank, int gpio, int enable)
1007 unsigned long flags;
1009 switch (bank->method) {
1010 #ifdef CONFIG_ARCH_OMAP16XX
1012 case METHOD_GPIO_1610:
1013 spin_lock_irqsave(&bank->lock, flags);
1015 bank->suspend_wakeup |= (1 << gpio);
1017 bank->suspend_wakeup &= ~(1 << gpio);
1018 spin_unlock_irqrestore(&bank->lock, flags);
1021 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
1022 defined(CONFIG_ARCH_OMAP4)
1023 case METHOD_GPIO_24XX:
1024 if (bank->non_wakeup_gpios & (1 << gpio)) {
1025 printk(KERN_ERR "Unable to modify wakeup on "
1026 "non-wakeup GPIO%d\n",
1027 (bank - gpio_bank) * 32 + gpio);
1030 spin_lock_irqsave(&bank->lock, flags);
1032 bank->suspend_wakeup |= (1 << gpio);
1034 bank->suspend_wakeup &= ~(1 << gpio);
1035 spin_unlock_irqrestore(&bank->lock, flags);
1039 printk(KERN_ERR "Can't enable GPIO wakeup for method %i\n",
1045 static void _reset_gpio(struct gpio_bank *bank, int gpio)
1047 _set_gpio_direction(bank, get_gpio_index(gpio), 1);
1048 _set_gpio_irqenable(bank, gpio, 0);
1049 _clear_gpio_irqstatus(bank, gpio);
1050 _set_gpio_triggering(bank, get_gpio_index(gpio), IRQ_TYPE_NONE);
1053 /* Use disable_irq_wake() and enable_irq_wake() functions from drivers */
1054 static int gpio_wake_enable(unsigned int irq, unsigned int enable)
1056 unsigned int gpio = irq - IH_GPIO_BASE;
1057 struct gpio_bank *bank;
1060 if (check_gpio(gpio) < 0)
1062 bank = get_irq_chip_data(irq);
1063 retval = _set_gpio_wakeup(bank, get_gpio_index(gpio), enable);
1068 static int omap_gpio_request(struct gpio_chip *chip, unsigned offset)
1070 struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip);
1071 unsigned long flags;
1073 spin_lock_irqsave(&bank->lock, flags);
1075 /* Set trigger to none. You need to enable the desired trigger with
1076 * request_irq() or set_irq_type().
1078 _set_gpio_triggering(bank, offset, IRQ_TYPE_NONE);
1080 #ifdef CONFIG_ARCH_OMAP15XX
1081 if (bank->method == METHOD_GPIO_1510) {
1084 /* Claim the pin for MPU */
1085 reg = bank->base + OMAP1510_GPIO_PIN_CONTROL;
1086 __raw_writel(__raw_readl(reg) | (1 << offset), reg);
1089 spin_unlock_irqrestore(&bank->lock, flags);
1094 static void omap_gpio_free(struct gpio_chip *chip, unsigned offset)
1096 struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip);
1097 unsigned long flags;
1099 spin_lock_irqsave(&bank->lock, flags);
1100 #ifdef CONFIG_ARCH_OMAP16XX
1101 if (bank->method == METHOD_GPIO_1610) {
1102 /* Disable wake-up during idle for dynamic tick */
1103 void __iomem *reg = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
1104 __raw_writel(1 << offset, reg);
1107 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
1108 defined(CONFIG_ARCH_OMAP4)
1109 if (bank->method == METHOD_GPIO_24XX) {
1110 /* Disable wake-up during idle for dynamic tick */
1111 void __iomem *reg = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
1112 __raw_writel(1 << offset, reg);
1115 _reset_gpio(bank, bank->chip.base + offset);
1116 spin_unlock_irqrestore(&bank->lock, flags);
1120 * We need to unmask the GPIO bank interrupt as soon as possible to
1121 * avoid missing GPIO interrupts for other lines in the bank.
1122 * Then we need to mask-read-clear-unmask the triggered GPIO lines
1123 * in the bank to avoid missing nested interrupts for a GPIO line.
1124 * If we wait to unmask individual GPIO lines in the bank after the
1125 * line's interrupt handler has been run, we may miss some nested
1128 static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
1130 void __iomem *isr_reg = NULL;
1132 unsigned int gpio_irq;
1133 struct gpio_bank *bank;
1137 desc->chip->ack(irq);
1139 bank = get_irq_data(irq);
1140 #ifdef CONFIG_ARCH_OMAP1
1141 if (bank->method == METHOD_MPUIO)
1142 isr_reg = bank->base + OMAP_MPUIO_GPIO_INT;
1144 #ifdef CONFIG_ARCH_OMAP15XX
1145 if (bank->method == METHOD_GPIO_1510)
1146 isr_reg = bank->base + OMAP1510_GPIO_INT_STATUS;
1148 #if defined(CONFIG_ARCH_OMAP16XX)
1149 if (bank->method == METHOD_GPIO_1610)
1150 isr_reg = bank->base + OMAP1610_GPIO_IRQSTATUS1;
1152 #ifdef CONFIG_ARCH_OMAP730
1153 if (bank->method == METHOD_GPIO_730)
1154 isr_reg = bank->base + OMAP730_GPIO_INT_STATUS;
1156 #ifdef CONFIG_ARCH_OMAP850
1157 if (bank->method == METHOD_GPIO_850)
1158 isr_reg = bank->base + OMAP850_GPIO_INT_STATUS;
1160 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
1161 defined(CONFIG_ARCH_OMAP4)
1162 if (bank->method == METHOD_GPIO_24XX)
1163 isr_reg = bank->base + OMAP24XX_GPIO_IRQSTATUS1;
1166 u32 isr_saved, level_mask = 0;
1169 enabled = _get_gpio_irqbank_mask(bank);
1170 isr_saved = isr = __raw_readl(isr_reg) & enabled;
1172 if (cpu_is_omap15xx() && (bank->method == METHOD_MPUIO))
1175 if (cpu_class_is_omap2()) {
1176 level_mask = bank->level_mask & enabled;
1179 /* clear edge sensitive interrupts before handler(s) are
1180 called so that we don't miss any interrupt occurred while
1182 _enable_gpio_irqbank(bank, isr_saved & ~level_mask, 0);
1183 _clear_gpio_irqbank(bank, isr_saved & ~level_mask);
1184 _enable_gpio_irqbank(bank, isr_saved & ~level_mask, 1);
1186 /* if there is only edge sensitive GPIO pin interrupts
1187 configured, we could unmask GPIO bank interrupt immediately */
1188 if (!level_mask && !unmasked) {
1190 desc->chip->unmask(irq);
1198 gpio_irq = bank->virtual_irq_start;
1199 for (; isr != 0; isr >>= 1, gpio_irq++) {
1203 generic_handle_irq(gpio_irq);
1206 /* if bank has any level sensitive GPIO pin interrupt
1207 configured, we must unmask the bank interrupt only after
1208 handler(s) are executed in order to avoid spurious bank
1211 desc->chip->unmask(irq);
1215 static void gpio_irq_shutdown(unsigned int irq)
1217 unsigned int gpio = irq - IH_GPIO_BASE;
1218 struct gpio_bank *bank = get_irq_chip_data(irq);
1220 _reset_gpio(bank, gpio);
1223 static void gpio_ack_irq(unsigned int irq)
1225 unsigned int gpio = irq - IH_GPIO_BASE;
1226 struct gpio_bank *bank = get_irq_chip_data(irq);
1228 _clear_gpio_irqstatus(bank, gpio);
1231 static void gpio_mask_irq(unsigned int irq)
1233 unsigned int gpio = irq - IH_GPIO_BASE;
1234 struct gpio_bank *bank = get_irq_chip_data(irq);
1236 _set_gpio_irqenable(bank, gpio, 0);
1237 _set_gpio_triggering(bank, get_gpio_index(gpio), IRQ_TYPE_NONE);
1240 static void gpio_unmask_irq(unsigned int irq)
1242 unsigned int gpio = irq - IH_GPIO_BASE;
1243 struct gpio_bank *bank = get_irq_chip_data(irq);
1244 unsigned int irq_mask = 1 << get_gpio_index(gpio);
1245 struct irq_desc *desc = irq_to_desc(irq);
1246 u32 trigger = desc->status & IRQ_TYPE_SENSE_MASK;
1249 _set_gpio_triggering(bank, get_gpio_index(gpio), trigger);
1251 /* For level-triggered GPIOs, the clearing must be done after
1252 * the HW source is cleared, thus after the handler has run */
1253 if (bank->level_mask & irq_mask) {
1254 _set_gpio_irqenable(bank, gpio, 0);
1255 _clear_gpio_irqstatus(bank, gpio);
1258 _set_gpio_irqenable(bank, gpio, 1);
1261 static struct irq_chip gpio_irq_chip = {
1263 .shutdown = gpio_irq_shutdown,
1264 .ack = gpio_ack_irq,
1265 .mask = gpio_mask_irq,
1266 .unmask = gpio_unmask_irq,
1267 .set_type = gpio_irq_type,
1268 .set_wake = gpio_wake_enable,
1271 /*---------------------------------------------------------------------*/
1273 #ifdef CONFIG_ARCH_OMAP1
1275 /* MPUIO uses the always-on 32k clock */
1277 static void mpuio_ack_irq(unsigned int irq)
1279 /* The ISR is reset automatically, so do nothing here. */
1282 static void mpuio_mask_irq(unsigned int irq)
1284 unsigned int gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE);
1285 struct gpio_bank *bank = get_irq_chip_data(irq);
1287 _set_gpio_irqenable(bank, gpio, 0);
1290 static void mpuio_unmask_irq(unsigned int irq)
1292 unsigned int gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE);
1293 struct gpio_bank *bank = get_irq_chip_data(irq);
1295 _set_gpio_irqenable(bank, gpio, 1);
1298 static struct irq_chip mpuio_irq_chip = {
1300 .ack = mpuio_ack_irq,
1301 .mask = mpuio_mask_irq,
1302 .unmask = mpuio_unmask_irq,
1303 .set_type = gpio_irq_type,
1304 #ifdef CONFIG_ARCH_OMAP16XX
1305 /* REVISIT: assuming only 16xx supports MPUIO wake events */
1306 .set_wake = gpio_wake_enable,
1311 #define bank_is_mpuio(bank) ((bank)->method == METHOD_MPUIO)
1314 #ifdef CONFIG_ARCH_OMAP16XX
1316 #include <linux/platform_device.h>
1318 static int omap_mpuio_suspend_late(struct platform_device *pdev, pm_message_t mesg)
1320 struct gpio_bank *bank = platform_get_drvdata(pdev);
1321 void __iomem *mask_reg = bank->base + OMAP_MPUIO_GPIO_MASKIT;
1322 unsigned long flags;
1324 spin_lock_irqsave(&bank->lock, flags);
1325 bank->saved_wakeup = __raw_readl(mask_reg);
1326 __raw_writel(0xffff & ~bank->suspend_wakeup, mask_reg);
1327 spin_unlock_irqrestore(&bank->lock, flags);
1332 static int omap_mpuio_resume_early(struct platform_device *pdev)
1334 struct gpio_bank *bank = platform_get_drvdata(pdev);
1335 void __iomem *mask_reg = bank->base + OMAP_MPUIO_GPIO_MASKIT;
1336 unsigned long flags;
1338 spin_lock_irqsave(&bank->lock, flags);
1339 __raw_writel(bank->saved_wakeup, mask_reg);
1340 spin_unlock_irqrestore(&bank->lock, flags);
1345 /* use platform_driver for this, now that there's no longer any
1346 * point to sys_device (other than not disturbing old code).
1348 static struct platform_driver omap_mpuio_driver = {
1349 .suspend_late = omap_mpuio_suspend_late,
1350 .resume_early = omap_mpuio_resume_early,
1356 static struct platform_device omap_mpuio_device = {
1360 .driver = &omap_mpuio_driver.driver,
1362 /* could list the /proc/iomem resources */
1365 static inline void mpuio_init(void)
1367 platform_set_drvdata(&omap_mpuio_device, &gpio_bank_1610[0]);
1369 if (platform_driver_register(&omap_mpuio_driver) == 0)
1370 (void) platform_device_register(&omap_mpuio_device);
1374 static inline void mpuio_init(void) {}
1379 extern struct irq_chip mpuio_irq_chip;
1381 #define bank_is_mpuio(bank) 0
1382 static inline void mpuio_init(void) {}
1386 /*---------------------------------------------------------------------*/
1388 /* REVISIT these are stupid implementations! replace by ones that
1389 * don't switch on METHOD_* and which mostly avoid spinlocks
1392 static int gpio_input(struct gpio_chip *chip, unsigned offset)
1394 struct gpio_bank *bank;
1395 unsigned long flags;
1397 bank = container_of(chip, struct gpio_bank, chip);
1398 spin_lock_irqsave(&bank->lock, flags);
1399 _set_gpio_direction(bank, offset, 1);
1400 spin_unlock_irqrestore(&bank->lock, flags);
1404 static int gpio_is_input(struct gpio_bank *bank, int mask)
1406 void __iomem *reg = bank->base;
1408 switch (bank->method) {
1410 reg += OMAP_MPUIO_IO_CNTL;
1412 case METHOD_GPIO_1510:
1413 reg += OMAP1510_GPIO_DIR_CONTROL;
1415 case METHOD_GPIO_1610:
1416 reg += OMAP1610_GPIO_DIRECTION;
1418 case METHOD_GPIO_730:
1419 reg += OMAP730_GPIO_DIR_CONTROL;
1421 case METHOD_GPIO_850:
1422 reg += OMAP850_GPIO_DIR_CONTROL;
1424 case METHOD_GPIO_24XX:
1425 reg += OMAP24XX_GPIO_OE;
1428 return __raw_readl(reg) & mask;
1431 static int gpio_get(struct gpio_chip *chip, unsigned offset)
1433 struct gpio_bank *bank;
1438 gpio = chip->base + offset;
1439 bank = get_gpio_bank(gpio);
1441 mask = 1 << get_gpio_index(gpio);
1443 if (gpio_is_input(bank, mask))
1444 return _get_gpio_datain(bank, gpio);
1446 return _get_gpio_dataout(bank, gpio);
1449 static int gpio_output(struct gpio_chip *chip, unsigned offset, int value)
1451 struct gpio_bank *bank;
1452 unsigned long flags;
1454 bank = container_of(chip, struct gpio_bank, chip);
1455 spin_lock_irqsave(&bank->lock, flags);
1456 _set_gpio_dataout(bank, offset, value);
1457 _set_gpio_direction(bank, offset, 0);
1458 spin_unlock_irqrestore(&bank->lock, flags);
1462 static void gpio_set(struct gpio_chip *chip, unsigned offset, int value)
1464 struct gpio_bank *bank;
1465 unsigned long flags;
1467 bank = container_of(chip, struct gpio_bank, chip);
1468 spin_lock_irqsave(&bank->lock, flags);
1469 _set_gpio_dataout(bank, offset, value);
1470 spin_unlock_irqrestore(&bank->lock, flags);
1473 static int gpio_2irq(struct gpio_chip *chip, unsigned offset)
1475 struct gpio_bank *bank;
1477 bank = container_of(chip, struct gpio_bank, chip);
1478 return bank->virtual_irq_start + offset;
1481 /*---------------------------------------------------------------------*/
1483 static int initialized;
1484 #if !(defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4))
1485 static struct clk * gpio_ick;
1488 #if defined(CONFIG_ARCH_OMAP2)
1489 static struct clk * gpio_fck;
1492 #if defined(CONFIG_ARCH_OMAP2430)
1493 static struct clk * gpio5_ick;
1494 static struct clk * gpio5_fck;
1497 #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
1498 static struct clk *gpio_iclks[OMAP34XX_NR_GPIOS];
1501 /* This lock class tells lockdep that GPIO irqs are in a different
1502 * category than their parents, so it won't report false recursion.
1504 static struct lock_class_key gpio_lock_class;
1506 static int __init _omap_gpio_init(void)
1510 struct gpio_bank *bank;
1515 #if defined(CONFIG_ARCH_OMAP1)
1516 if (cpu_is_omap15xx()) {
1517 gpio_ick = clk_get(NULL, "arm_gpio_ck");
1518 if (IS_ERR(gpio_ick))
1519 printk("Could not get arm_gpio_ck\n");
1521 clk_enable(gpio_ick);
1524 #if defined(CONFIG_ARCH_OMAP2)
1525 if (cpu_class_is_omap2()) {
1526 gpio_ick = clk_get(NULL, "gpios_ick");
1527 if (IS_ERR(gpio_ick))
1528 printk("Could not get gpios_ick\n");
1530 clk_enable(gpio_ick);
1531 gpio_fck = clk_get(NULL, "gpios_fck");
1532 if (IS_ERR(gpio_fck))
1533 printk("Could not get gpios_fck\n");
1535 clk_enable(gpio_fck);
1538 * On 2430 & 3430 GPIO 5 uses CORE L4 ICLK
1540 #if defined(CONFIG_ARCH_OMAP2430)
1541 if (cpu_is_omap2430()) {
1542 gpio5_ick = clk_get(NULL, "gpio5_ick");
1543 if (IS_ERR(gpio5_ick))
1544 printk("Could not get gpio5_ick\n");
1546 clk_enable(gpio5_ick);
1547 gpio5_fck = clk_get(NULL, "gpio5_fck");
1548 if (IS_ERR(gpio5_fck))
1549 printk("Could not get gpio5_fck\n");
1551 clk_enable(gpio5_fck);
1557 #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
1558 if (cpu_is_omap34xx() || cpu_is_omap44xx()) {
1559 for (i = 0; i < OMAP34XX_NR_GPIOS; i++) {
1560 sprintf(clk_name, "gpio%d_ick", i + 1);
1561 gpio_iclks[i] = clk_get(NULL, clk_name);
1562 if (IS_ERR(gpio_iclks[i]))
1563 printk(KERN_ERR "Could not get %s\n", clk_name);
1565 clk_enable(gpio_iclks[i]);
1571 #ifdef CONFIG_ARCH_OMAP15XX
1572 if (cpu_is_omap15xx()) {
1573 printk(KERN_INFO "OMAP1510 GPIO hardware\n");
1574 gpio_bank_count = 2;
1575 gpio_bank = gpio_bank_1510;
1578 #if defined(CONFIG_ARCH_OMAP16XX)
1579 if (cpu_is_omap16xx()) {
1582 gpio_bank_count = 5;
1583 gpio_bank = gpio_bank_1610;
1584 rev = __raw_readw(gpio_bank[1].base + OMAP1610_GPIO_REVISION);
1585 printk(KERN_INFO "OMAP GPIO hardware version %d.%d\n",
1586 (rev >> 4) & 0x0f, rev & 0x0f);
1589 #ifdef CONFIG_ARCH_OMAP730
1590 if (cpu_is_omap730()) {
1591 printk(KERN_INFO "OMAP730 GPIO hardware\n");
1592 gpio_bank_count = 7;
1593 gpio_bank = gpio_bank_730;
1596 #ifdef CONFIG_ARCH_OMAP850
1597 if (cpu_is_omap850()) {
1598 printk(KERN_INFO "OMAP850 GPIO hardware\n");
1599 gpio_bank_count = 7;
1600 gpio_bank = gpio_bank_850;
1604 #ifdef CONFIG_ARCH_OMAP24XX
1605 if (cpu_is_omap242x()) {
1608 gpio_bank_count = 4;
1609 gpio_bank = gpio_bank_242x;
1610 rev = __raw_readl(gpio_bank[0].base + OMAP24XX_GPIO_REVISION);
1611 printk(KERN_INFO "OMAP242x GPIO hardware version %d.%d\n",
1612 (rev >> 4) & 0x0f, rev & 0x0f);
1614 if (cpu_is_omap243x()) {
1617 gpio_bank_count = 5;
1618 gpio_bank = gpio_bank_243x;
1619 rev = __raw_readl(gpio_bank[0].base + OMAP24XX_GPIO_REVISION);
1620 printk(KERN_INFO "OMAP243x GPIO hardware version %d.%d\n",
1621 (rev >> 4) & 0x0f, rev & 0x0f);
1624 #ifdef CONFIG_ARCH_OMAP34XX
1625 if (cpu_is_omap34xx()) {
1628 gpio_bank_count = OMAP34XX_NR_GPIOS;
1629 gpio_bank = gpio_bank_34xx;
1630 rev = __raw_readl(gpio_bank[0].base + OMAP24XX_GPIO_REVISION);
1631 printk(KERN_INFO "OMAP34xx GPIO hardware version %d.%d\n",
1632 (rev >> 4) & 0x0f, rev & 0x0f);
1635 #ifdef CONFIG_ARCH_OMAP4
1636 if (cpu_is_omap44xx()) {
1639 gpio_bank_count = OMAP34XX_NR_GPIOS;
1640 gpio_bank = gpio_bank_44xx;
1641 rev = __raw_readl(gpio_bank[0].base + OMAP24XX_GPIO_REVISION);
1642 printk(KERN_INFO "OMAP44xx GPIO hardware version %d.%d\n",
1643 (rev >> 4) & 0x0f, rev & 0x0f);
1646 for (i = 0; i < gpio_bank_count; i++) {
1647 int j, gpio_count = 16;
1649 bank = &gpio_bank[i];
1650 spin_lock_init(&bank->lock);
1651 if (bank_is_mpuio(bank))
1652 __raw_writew(0xffff, bank->base + OMAP_MPUIO_GPIO_MASKIT);
1653 if (cpu_is_omap15xx() && bank->method == METHOD_GPIO_1510) {
1654 __raw_writew(0xffff, bank->base + OMAP1510_GPIO_INT_MASK);
1655 __raw_writew(0x0000, bank->base + OMAP1510_GPIO_INT_STATUS);
1657 if (cpu_is_omap16xx() && bank->method == METHOD_GPIO_1610) {
1658 __raw_writew(0x0000, bank->base + OMAP1610_GPIO_IRQENABLE1);
1659 __raw_writew(0xffff, bank->base + OMAP1610_GPIO_IRQSTATUS1);
1660 __raw_writew(0x0014, bank->base + OMAP1610_GPIO_SYSCONFIG);
1662 if (cpu_is_omap7xx() && bank->method == METHOD_GPIO_730) {
1663 __raw_writel(0xffffffff, bank->base + OMAP730_GPIO_INT_MASK);
1664 __raw_writel(0x00000000, bank->base + OMAP730_GPIO_INT_STATUS);
1666 gpio_count = 32; /* 730 has 32-bit GPIOs */
1669 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
1670 defined(CONFIG_ARCH_OMAP4)
1671 if (bank->method == METHOD_GPIO_24XX) {
1672 static const u32 non_wakeup_gpios[] = {
1673 0xe203ffc0, 0x08700040
1676 __raw_writel(0x00000000, bank->base + OMAP24XX_GPIO_IRQENABLE1);
1677 __raw_writel(0xffffffff, bank->base + OMAP24XX_GPIO_IRQSTATUS1);
1678 __raw_writew(0x0015, bank->base + OMAP24XX_GPIO_SYSCONFIG);
1679 __raw_writel(0x00000000, bank->base + OMAP24XX_GPIO_DEBOUNCE_EN);
1681 /* Initialize interface clock ungated, module enabled */
1682 __raw_writel(0, bank->base + OMAP24XX_GPIO_CTRL);
1683 if (i < ARRAY_SIZE(non_wakeup_gpios))
1684 bank->non_wakeup_gpios = non_wakeup_gpios[i];
1689 /* REVISIT eventually switch from OMAP-specific gpio structs
1690 * over to the generic ones
1692 bank->chip.request = omap_gpio_request;
1693 bank->chip.free = omap_gpio_free;
1694 bank->chip.direction_input = gpio_input;
1695 bank->chip.get = gpio_get;
1696 bank->chip.direction_output = gpio_output;
1697 bank->chip.set = gpio_set;
1698 bank->chip.to_irq = gpio_2irq;
1699 if (bank_is_mpuio(bank)) {
1700 bank->chip.label = "mpuio";
1701 #ifdef CONFIG_ARCH_OMAP16XX
1702 bank->chip.dev = &omap_mpuio_device.dev;
1704 bank->chip.base = OMAP_MPUIO(0);
1706 bank->chip.label = "gpio";
1707 bank->chip.base = gpio;
1710 bank->chip.ngpio = gpio_count;
1712 gpiochip_add(&bank->chip);
1714 for (j = bank->virtual_irq_start;
1715 j < bank->virtual_irq_start + gpio_count; j++) {
1716 lockdep_set_class(&irq_desc[j].lock, &gpio_lock_class);
1717 set_irq_chip_data(j, bank);
1718 if (bank_is_mpuio(bank))
1719 set_irq_chip(j, &mpuio_irq_chip);
1721 set_irq_chip(j, &gpio_irq_chip);
1722 set_irq_handler(j, handle_simple_irq);
1723 set_irq_flags(j, IRQF_VALID);
1725 set_irq_chained_handler(bank->irq, gpio_irq_handler);
1726 set_irq_data(bank->irq, bank);
1728 if (cpu_is_omap34xx() || cpu_is_omap44xx()) {
1729 sprintf(clk_name, "gpio%d_dbck", i + 1);
1730 bank->dbck = clk_get(NULL, clk_name);
1731 if (IS_ERR(bank->dbck))
1732 printk(KERN_ERR "Could not get %s\n", clk_name);
1736 /* Enable system clock for GPIO module.
1737 * The CAM_CLK_CTRL *is* really the right place. */
1738 if (cpu_is_omap16xx())
1739 omap_writel(omap_readl(ULPD_CAM_CLK_CTRL) | 0x04, ULPD_CAM_CLK_CTRL);
1741 /* Enable autoidle for the OCP interface */
1742 if (cpu_is_omap24xx())
1743 omap_writel(1 << 0, 0x48019010);
1744 if (cpu_is_omap34xx())
1745 omap_writel(1 << 0, 0x48306814);
1750 #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP24XX) || \
1751 defined(CONFIG_ARCH_OMAP34XX) || defined(CONFIG_ARCH_OMAP4)
1752 static int omap_gpio_suspend(struct sys_device *dev, pm_message_t mesg)
1756 if (!cpu_class_is_omap2() && !cpu_is_omap16xx())
1759 for (i = 0; i < gpio_bank_count; i++) {
1760 struct gpio_bank *bank = &gpio_bank[i];
1761 void __iomem *wake_status;
1762 void __iomem *wake_clear;
1763 void __iomem *wake_set;
1764 unsigned long flags;
1766 switch (bank->method) {
1767 #ifdef CONFIG_ARCH_OMAP16XX
1768 case METHOD_GPIO_1610:
1769 wake_status = bank->base + OMAP1610_GPIO_WAKEUPENABLE;
1770 wake_clear = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
1771 wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA;
1774 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
1775 defined(CONFIG_ARCH_OMAP4)
1776 case METHOD_GPIO_24XX:
1777 wake_status = bank->base + OMAP24XX_GPIO_WAKE_EN;
1778 wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
1779 wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA;
1786 spin_lock_irqsave(&bank->lock, flags);
1787 bank->saved_wakeup = __raw_readl(wake_status);
1788 __raw_writel(0xffffffff, wake_clear);
1789 __raw_writel(bank->suspend_wakeup, wake_set);
1790 spin_unlock_irqrestore(&bank->lock, flags);
1796 static int omap_gpio_resume(struct sys_device *dev)
1800 if (!cpu_class_is_omap2() && !cpu_is_omap16xx())
1803 for (i = 0; i < gpio_bank_count; i++) {
1804 struct gpio_bank *bank = &gpio_bank[i];
1805 void __iomem *wake_clear;
1806 void __iomem *wake_set;
1807 unsigned long flags;
1809 switch (bank->method) {
1810 #ifdef CONFIG_ARCH_OMAP16XX
1811 case METHOD_GPIO_1610:
1812 wake_clear = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
1813 wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA;
1816 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
1817 defined(CONFIG_ARCH_OMAP4)
1818 case METHOD_GPIO_24XX:
1819 wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
1820 wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA;
1827 spin_lock_irqsave(&bank->lock, flags);
1828 __raw_writel(0xffffffff, wake_clear);
1829 __raw_writel(bank->saved_wakeup, wake_set);
1830 spin_unlock_irqrestore(&bank->lock, flags);
1836 static struct sysdev_class omap_gpio_sysclass = {
1838 .suspend = omap_gpio_suspend,
1839 .resume = omap_gpio_resume,
1842 static struct sys_device omap_gpio_device = {
1844 .cls = &omap_gpio_sysclass,
1849 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
1850 defined(CONFIG_ARCH_OMAP4)
1852 static int workaround_enabled;
1854 void omap2_gpio_prepare_for_retention(void)
1858 /* Remove triggering for all non-wakeup GPIOs. Otherwise spurious
1859 * IRQs will be generated. See OMAP2420 Errata item 1.101. */
1860 for (i = 0; i < gpio_bank_count; i++) {
1861 struct gpio_bank *bank = &gpio_bank[i];
1864 if (!(bank->enabled_non_wakeup_gpios))
1866 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
1867 defined(CONFIG_ARCH_OMAP4)
1868 bank->saved_datain = __raw_readl(bank->base + OMAP24XX_GPIO_DATAIN);
1869 l1 = __raw_readl(bank->base + OMAP24XX_GPIO_FALLINGDETECT);
1870 l2 = __raw_readl(bank->base + OMAP24XX_GPIO_RISINGDETECT);
1872 bank->saved_fallingdetect = l1;
1873 bank->saved_risingdetect = l2;
1874 l1 &= ~bank->enabled_non_wakeup_gpios;
1875 l2 &= ~bank->enabled_non_wakeup_gpios;
1876 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
1877 defined(CONFIG_ARCH_OMAP4)
1878 __raw_writel(l1, bank->base + OMAP24XX_GPIO_FALLINGDETECT);
1879 __raw_writel(l2, bank->base + OMAP24XX_GPIO_RISINGDETECT);
1884 workaround_enabled = 0;
1887 workaround_enabled = 1;
1890 void omap2_gpio_resume_after_retention(void)
1894 if (!workaround_enabled)
1896 for (i = 0; i < gpio_bank_count; i++) {
1897 struct gpio_bank *bank = &gpio_bank[i];
1900 if (!(bank->enabled_non_wakeup_gpios))
1902 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
1903 defined(CONFIG_ARCH_OMAP4)
1904 __raw_writel(bank->saved_fallingdetect,
1905 bank->base + OMAP24XX_GPIO_FALLINGDETECT);
1906 __raw_writel(bank->saved_risingdetect,
1907 bank->base + OMAP24XX_GPIO_RISINGDETECT);
1909 /* Check if any of the non-wakeup interrupt GPIOs have changed
1910 * state. If so, generate an IRQ by software. This is
1911 * horribly racy, but it's the best we can do to work around
1912 * this silicon bug. */
1913 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
1914 defined(CONFIG_ARCH_OMAP4)
1915 l = __raw_readl(bank->base + OMAP24XX_GPIO_DATAIN);
1917 l ^= bank->saved_datain;
1918 l &= bank->non_wakeup_gpios;
1921 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
1922 defined(CONFIG_ARCH_OMAP4)
1923 old0 = __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0);
1924 old1 = __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1);
1925 __raw_writel(old0 | l, bank->base + OMAP24XX_GPIO_LEVELDETECT0);
1926 __raw_writel(old1 | l, bank->base + OMAP24XX_GPIO_LEVELDETECT1);
1927 __raw_writel(old0, bank->base + OMAP24XX_GPIO_LEVELDETECT0);
1928 __raw_writel(old1, bank->base + OMAP24XX_GPIO_LEVELDETECT1);
1938 * This may get called early from board specific init
1939 * for boards that have interrupts routed via FPGA.
1941 int __init omap_gpio_init(void)
1944 return _omap_gpio_init();
1949 static int __init omap_gpio_sysinit(void)
1954 ret = _omap_gpio_init();
1958 #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP24XX) || \
1959 defined(CONFIG_ARCH_OMAP34XX) || defined(CONFIG_ARCH_OMAP4)
1960 if (cpu_is_omap16xx() || cpu_class_is_omap2()) {
1962 ret = sysdev_class_register(&omap_gpio_sysclass);
1964 ret = sysdev_register(&omap_gpio_device);
1972 arch_initcall(omap_gpio_sysinit);
1975 #ifdef CONFIG_DEBUG_FS
1977 #include <linux/debugfs.h>
1978 #include <linux/seq_file.h>
1980 static int dbg_gpio_show(struct seq_file *s, void *unused)
1982 unsigned i, j, gpio;
1984 for (i = 0, gpio = 0; i < gpio_bank_count; i++) {
1985 struct gpio_bank *bank = gpio_bank + i;
1986 unsigned bankwidth = 16;
1989 if (bank_is_mpuio(bank))
1990 gpio = OMAP_MPUIO(0);
1991 else if (cpu_class_is_omap2() || cpu_is_omap730() ||
1995 for (j = 0; j < bankwidth; j++, gpio++, mask <<= 1) {
1996 unsigned irq, value, is_in, irqstat;
1999 label = gpiochip_is_requested(&bank->chip, j);
2003 irq = bank->virtual_irq_start + j;
2004 value = gpio_get_value(gpio);
2005 is_in = gpio_is_input(bank, mask);
2007 if (bank_is_mpuio(bank))
2008 seq_printf(s, "MPUIO %2d ", j);
2010 seq_printf(s, "GPIO %3d ", gpio);
2011 seq_printf(s, "(%-20.20s): %s %s",
2013 is_in ? "in " : "out",
2014 value ? "hi" : "lo");
2016 /* FIXME for at least omap2, show pullup/pulldown state */
2018 irqstat = irq_desc[irq].status;
2019 #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP24XX) || \
2020 defined(CONFIG_ARCH_OMAP34XX) || defined(CONFIG_ARCH_OMAP4)
2021 if (is_in && ((bank->suspend_wakeup & mask)
2022 || irqstat & IRQ_TYPE_SENSE_MASK)) {
2023 char *trigger = NULL;
2025 switch (irqstat & IRQ_TYPE_SENSE_MASK) {
2026 case IRQ_TYPE_EDGE_FALLING:
2027 trigger = "falling";
2029 case IRQ_TYPE_EDGE_RISING:
2032 case IRQ_TYPE_EDGE_BOTH:
2033 trigger = "bothedge";
2035 case IRQ_TYPE_LEVEL_LOW:
2038 case IRQ_TYPE_LEVEL_HIGH:
2045 seq_printf(s, ", irq-%d %-8s%s",
2047 (bank->suspend_wakeup & mask)
2051 seq_printf(s, "\n");
2054 if (bank_is_mpuio(bank)) {
2055 seq_printf(s, "\n");
2062 static int dbg_gpio_open(struct inode *inode, struct file *file)
2064 return single_open(file, dbg_gpio_show, &inode->i_private);
2067 static const struct file_operations debug_fops = {
2068 .open = dbg_gpio_open,
2070 .llseek = seq_lseek,
2071 .release = single_release,
2074 static int __init omap_gpio_debuginit(void)
2076 (void) debugfs_create_file("omap_gpio", S_IRUGO,
2077 NULL, NULL, &debug_fops);
2080 late_initcall(omap_gpio_debuginit);