arch/arm/plat-omap/dma.c

   1 /*
   2  * linux/arch/arm/plat-omap/dma.c
   3  *
   4  * Copyright (C) 2003 - 2008 Nokia Corporation
   5  * Author: Juha Yrjölä <juha.yrjola@nokia.com>
   6  * DMA channel linking for 1610 by Samuel Ortiz <samuel.ortiz@nokia.com>
   7  * Graphics DMA and LCD DMA graphics tranformations
   8  * by Imre Deak <imre.deak@nokia.com>
   9  * OMAP2/3 support Copyright (C) 2004-2007 Texas Instruments, Inc.
  10  * Merged to support both OMAP1 and OMAP2 by Tony Lindgren <tony@atomide.com>
  11  * Some functions based on earlier dma-omap.c Copyright (C) 2001 RidgeRun, Inc.
  12  *
  13  * Copyright (C) 2009 Texas Instruments
  14  * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
  15  *
  16  * Support functions for the OMAP internal DMA channels.
  17  *
  18  * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
  19  * Converted DMA library into DMA platform driver.
  20  *      - G, Manjunath Kondaiah <manjugk@ti.com>
  21  *
  22  * This program is free software; you can redistribute it and/or modify
  23  * it under the terms of the GNU General Public License version 2 as
  24  * published by the Free Software Foundation.
  25  *
  26  */
  27
  28 #include <linux/module.h>
  29 #include <linux/init.h>
  30 #include <linux/sched.h>
  31 #include <linux/spinlock.h>
  32 #include <linux/errno.h>
  33 #include <linux/interrupt.h>
  34 #include <linux/irq.h>
  35 #include <linux/io.h>
  36 #include <linux/slab.h>
  37 #include <linux/delay.h>
  38
  39 #include <plat/cpu.h>
  40 #include <plat/dma.h>
  41 #include <plat/tc.h>
  42
  43 /*
  44  * MAX_LOGICAL_DMA_CH_COUNT: the maximum number of logical DMA
  45  * channels that an instance of the SDMA IP block can support.  Used
  46  * to size arrays.  (The actual maximum on a particular SoC may be less
  47  * than this -- for example, OMAP1 SDMA instances only support 17 logical
  48  * DMA channels.)
  49  */
  50 #define MAX_LOGICAL_DMA_CH_COUNT                32
  51
  52 #undef DEBUG
  53
  54 #ifndef CONFIG_ARCH_OMAP1
  55 enum { DMA_CH_ALLOC_DONE, DMA_CH_PARAMS_SET_DONE, DMA_CH_STARTED,
  56         DMA_CH_QUEUED, DMA_CH_NOTSTARTED, DMA_CH_PAUSED, DMA_CH_LINK_ENABLED
  57 };
  58
  59 enum { DMA_CHAIN_STARTED, DMA_CHAIN_NOTSTARTED };
  60 #endif
  61
  62 #define OMAP_DMA_ACTIVE                 0x01
  63 #define OMAP2_DMA_CSR_CLEAR_MASK        0xffffffff
  64
  65 #define OMAP_FUNC_MUX_ARM_BASE          (0xfffe1000 + 0xec)
  66
  67 static struct omap_system_dma_plat_info *p;
  68 static struct omap_dma_dev_attr *d;
  69
  70 static int enable_1510_mode;
  71 static u32 errata;
  72
  73 static struct omap_dma_global_context_registers {
  74         u32 dma_irqenable_l0;
  75         u32 dma_ocp_sysconfig;
  76         u32 dma_gcr;
  77 } omap_dma_global_context;
  78
  79 struct dma_link_info {
  80         int *linked_dmach_q;
  81         int no_of_lchs_linked;
  82
  83         int q_count;
  84         int q_tail;
  85         int q_head;
  86
  87         int chain_state;
  88         int chain_mode;
  89
  90 };
  91
  92 static struct dma_link_info *dma_linked_lch;
  93
  94 #ifndef CONFIG_ARCH_OMAP1
  95
  96 /* Chain handling macros */
  97 #define OMAP_DMA_CHAIN_QINIT(chain_id)                                  \
  98         do {                                                            \
  99                 dma_linked_lch[chain_id].q_head =                       \
 100                 dma_linked_lch[chain_id].q_tail =                       \
 101                 dma_linked_lch[chain_id].q_count = 0;                   \
 102         } while (0)
 103 #define OMAP_DMA_CHAIN_QFULL(chain_id)                                  \
 104                 (dma_linked_lch[chain_id].no_of_lchs_linked ==          \
 105                 dma_linked_lch[chain_id].q_count)
 106 #define OMAP_DMA_CHAIN_QLAST(chain_id)                                  \
 107         do {                                                            \
 108                 ((dma_linked_lch[chain_id].no_of_lchs_linked-1) ==      \
 109                 dma_linked_lch[chain_id].q_count)                       \
 110         } while (0)
 111 #define OMAP_DMA_CHAIN_QEMPTY(chain_id)                                 \
 112                 (0 == dma_linked_lch[chain_id].q_count)
 113 #define __OMAP_DMA_CHAIN_INCQ(end)                                      \
 114         ((end) = ((end)+1) % dma_linked_lch[chain_id].no_of_lchs_linked)
 115 #define OMAP_DMA_CHAIN_INCQHEAD(chain_id)                               \
 116         do {                                                            \
 117                 __OMAP_DMA_CHAIN_INCQ(dma_linked_lch[chain_id].q_head); \
 118                 dma_linked_lch[chain_id].q_count--;                     \
 119         } while (0)
 120
 121 #define OMAP_DMA_CHAIN_INCQTAIL(chain_id)                               \
 122         do {                                                            \
 123                 __OMAP_DMA_CHAIN_INCQ(dma_linked_lch[chain_id].q_tail); \
 124                 dma_linked_lch[chain_id].q_count++; \
 125         } while (0)
 126 #endif
 127
 128 static int dma_lch_count;
 129 static int dma_chan_count;
 130 static int omap_dma_reserve_channels;
 131
 132 static spinlock_t dma_chan_lock;
 133 static struct omap_dma_lch *dma_chan;
 134
 135 static inline void disable_lnk(int lch);
 136 static void omap_disable_channel_irq(int lch);
 137 static inline void omap_enable_channel_irq(int lch);
 138
 139 #define REVISIT_24XX()          printk(KERN_ERR "FIXME: no %s on 24xx\n", \
 140                                                 __func__);
 141
 142 #ifdef CONFIG_ARCH_OMAP15XX
 143 /* Returns 1 if the DMA module is in OMAP1510-compatible mode, 0 otherwise */
 144 static int omap_dma_in_1510_mode(void)
 145 {
 146         return enable_1510_mode;
 147 }
 148 #else
 149 #define omap_dma_in_1510_mode()         0
 150 #endif
 151
 152 #ifdef CONFIG_ARCH_OMAP1
 153 static inline int get_gdma_dev(int req)
 154 {
 155         u32 reg = OMAP_FUNC_MUX_ARM_BASE + ((req - 1) / 5) * 4;
 156         int shift = ((req - 1) % 5) * 6;
 157
 158         return ((omap_readl(reg) >> shift) & 0x3f) + 1;
 159 }
 160
 161 static inline void set_gdma_dev(int req, int dev)
 162 {
 163         u32 reg = OMAP_FUNC_MUX_ARM_BASE + ((req - 1) / 5) * 4;
 164         int shift = ((req - 1) % 5) * 6;
 165         u32 l;
 166
 167         l = omap_readl(reg);
 168         l &= ~(0x3f << shift);
 169         l |= (dev - 1) << shift;
 170         omap_writel(l, reg);
 171 }
 172 #else
 173 #define set_gdma_dev(req, dev)  do {} while (0)
 174 #define omap_readl(reg)         0
 175 #define omap_writel(val, reg)   do {} while (0)
 176 #endif
 177
 178 void omap_set_dma_priority(int lch, int dst_port, int priority)
 179 {
 180         unsigned long reg;
 181         u32 l;
 182
 183         if (cpu_class_is_omap1()) {
 184                 switch (dst_port) {
 185                 case OMAP_DMA_PORT_OCP_T1:      /* FFFECC00 */
 186                         reg = OMAP_TC_OCPT1_PRIOR;
 187                         break;
 188                 case OMAP_DMA_PORT_OCP_T2:      /* FFFECCD0 */
 189                         reg = OMAP_TC_OCPT2_PRIOR;
 190                         break;
 191                 case OMAP_DMA_PORT_EMIFF:       /* FFFECC08 */
 192                         reg = OMAP_TC_EMIFF_PRIOR;
 193                         break;
 194                 case OMAP_DMA_PORT_EMIFS:       /* FFFECC04 */
 195                         reg = OMAP_TC_EMIFS_PRIOR;
 196                         break;
 197                 default:
 198                         BUG();
 199                         return;
 200                 }
 201                 l = omap_readl(reg);
 202                 l &= ~(0xf << 8);
 203                 l |= (priority & 0xf) << 8;
 204                 omap_writel(l, reg);
 205         }
 206
 207         if (cpu_class_is_omap2()) {
 208                 u32 ccr;
 209
 210                 ccr = p->dma_read(CCR, lch);
 211                 if (priority)
 212                         ccr |= (1 << 6);
 213                 else
 214                         ccr &= ~(1 << 6);
 215                 p->dma_write(ccr, CCR, lch);
 216         }
 217 }
 218 EXPORT_SYMBOL(omap_set_dma_priority);
 219
 220 void omap_set_dma_transfer_params(int lch, int data_type, int elem_count,
 221                                   int frame_count, int sync_mode,
 222                                   int dma_trigger, int src_or_dst_synch)
 223 {
 224         u32 l;
 225
 226         l = p->dma_read(CSDP, lch);
 227         l &= ~0x03;
 228         l |= data_type;
 229         p->dma_write(l, CSDP, lch);
 230
 231         if (cpu_class_is_omap1()) {
 232                 u16 ccr;
 233
 234                 ccr = p->dma_read(CCR, lch);
 235                 ccr &= ~(1 << 5);
 236                 if (sync_mode == OMAP_DMA_SYNC_FRAME)
 237                         ccr |= 1 << 5;
 238                 p->dma_write(ccr, CCR, lch);
 239
 240                 ccr = p->dma_read(CCR2, lch);
 241                 ccr &= ~(1 << 2);
 242                 if (sync_mode == OMAP_DMA_SYNC_BLOCK)
 243                         ccr |= 1 << 2;
 244                 p->dma_write(ccr, CCR2, lch);
 245         }
 246
 247         if (cpu_class_is_omap2() && dma_trigger) {
 248                 u32 val;
 249
 250                 val = p->dma_read(CCR, lch);
 251
 252                 /* DMA_SYNCHRO_CONTROL_UPPER depends on the channel number */
 253                 val &= ~((1 << 23) | (3 << 19) | 0x1f);
 254                 val |= (dma_trigger & ~0x1f) << 14;
 255                 val |= dma_trigger & 0x1f;
 256
 257                 if (sync_mode & OMAP_DMA_SYNC_FRAME)
 258                         val |= 1 << 5;
 259                 else
 260                         val &= ~(1 << 5);
 261
 262                 if (sync_mode & OMAP_DMA_SYNC_BLOCK)
 263                         val |= 1 << 18;
 264                 else
 265                         val &= ~(1 << 18);
 266
 267                 if (src_or_dst_synch == OMAP_DMA_DST_SYNC_PREFETCH) {
 268                         val &= ~(1 << 24);      /* dest synch */
 269                         val |= (1 << 23);       /* Prefetch */
 270                 } else if (src_or_dst_synch) {
 271                         val |= 1 << 24;         /* source synch */
 272                 } else {
 273                         val &= ~(1 << 24);      /* dest synch */
 274                 }
 275                 p->dma_write(val, CCR, lch);
 276         }
 277
 278         p->dma_write(elem_count, CEN, lch);
 279         p->dma_write(frame_count, CFN, lch);
 280 }
 281 EXPORT_SYMBOL(omap_set_dma_transfer_params);
 282
 283 void omap_set_dma_color_mode(int lch, enum omap_dma_color_mode mode, u32 color)
 284 {
 285         BUG_ON(omap_dma_in_1510_mode());
 286
 287         if (cpu_class_is_omap1()) {
 288                 u16 w;
 289
 290                 w = p->dma_read(CCR2, lch);
 291                 w &= ~0x03;
 292
 293                 switch (mode) {
 294                 case OMAP_DMA_CONSTANT_FILL:
 295                         w |= 0x01;
 296                         break;
 297                 case OMAP_DMA_TRANSPARENT_COPY:
 298                         w |= 0x02;
 299                         break;
 300                 case OMAP_DMA_COLOR_DIS:
 301                         break;
 302                 default:
 303                         BUG();
 304                 }
 305                 p->dma_write(w, CCR2, lch);
 306
 307                 w = p->dma_read(LCH_CTRL, lch);
 308                 w &= ~0x0f;
 309                 /* Default is channel type 2D */
 310                 if (mode) {
 311                         p->dma_write(color, COLOR, lch);
 312                         w |= 1;         /* Channel type G */
 313                 }
 314                 p->dma_write(w, LCH_CTRL, lch);
 315         }
 316
 317         if (cpu_class_is_omap2()) {
 318                 u32 val;
 319
 320                 val = p->dma_read(CCR, lch);
 321                 val &= ~((1 << 17) | (1 << 16));
 322
 323                 switch (mode) {
 324                 case OMAP_DMA_CONSTANT_FILL:
 325                         val |= 1 << 16;
 326                         break;
 327                 case OMAP_DMA_TRANSPARENT_COPY:
 328                         val |= 1 << 17;
 329                         break;
 330                 case OMAP_DMA_COLOR_DIS:
 331                         break;
 332                 default:
 333                         BUG();
 334                 }
 335                 p->dma_write(val, CCR, lch);
 336
 337                 color &= 0xffffff;
 338                 p->dma_write(color, COLOR, lch);
 339         }
 340 }
 341 EXPORT_SYMBOL(omap_set_dma_color_mode);
 342
 343 void omap_set_dma_write_mode(int lch, enum omap_dma_write_mode mode)
 344 {
 345         if (cpu_class_is_omap2()) {
 346                 u32 csdp;
 347
 348                 csdp = p->dma_read(CSDP, lch);
 349                 csdp &= ~(0x3 << 16);
 350                 csdp |= (mode << 16);
 351                 p->dma_write(csdp, CSDP, lch);
 352         }
 353 }
 354 EXPORT_SYMBOL(omap_set_dma_write_mode);
 355
 356 void omap_set_dma_channel_mode(int lch, enum omap_dma_channel_mode mode)
 357 {
 358         if (cpu_class_is_omap1() && !cpu_is_omap15xx()) {
 359                 u32 l;
 360
 361                 l = p->dma_read(LCH_CTRL, lch);
 362                 l &= ~0x7;
 363                 l |= mode;
 364                 p->dma_write(l, LCH_CTRL, lch);
 365         }
 366 }
 367 EXPORT_SYMBOL(omap_set_dma_channel_mode);
 368
 369 /* Note that src_port is only for omap1 */
 370 void omap_set_dma_src_params(int lch, int src_port, int src_amode,
 371                              unsigned long src_start,
 372                              int src_ei, int src_fi)
 373 {
 374         u32 l;
 375
 376         if (cpu_class_is_omap1()) {
 377                 u16 w;
 378
 379                 w = p->dma_read(CSDP, lch);
 380                 w &= ~(0x1f << 2);
 381                 w |= src_port << 2;
 382                 p->dma_write(w, CSDP, lch);
 383         }
 384
 385         l = p->dma_read(CCR, lch);
 386         l &= ~(0x03 << 12);
 387         l |= src_amode << 12;
 388         p->dma_write(l, CCR, lch);
 389
 390         p->dma_write(src_start, CSSA, lch);
 391
 392         p->dma_write(src_ei, CSEI, lch);
 393         p->dma_write(src_fi, CSFI, lch);
 394 }
 395 EXPORT_SYMBOL(omap_set_dma_src_params);
 396
 397 void omap_set_dma_params(int lch, struct omap_dma_channel_params *params)
 398 {
 399         omap_set_dma_transfer_params(lch, params->data_type,
 400                                      params->elem_count, params->frame_count,
 401                                      params->sync_mode, params->trigger,
 402                                      params->src_or_dst_synch);
 403         omap_set_dma_src_params(lch, params->src_port,
 404                                 params->src_amode, params->src_start,
 405                                 params->src_ei, params->src_fi);
 406
 407         omap_set_dma_dest_params(lch, params->dst_port,
 408                                  params->dst_amode, params->dst_start,
 409                                  params->dst_ei, params->dst_fi);
 410         if (params->read_prio || params->write_prio)
 411                 omap_dma_set_prio_lch(lch, params->read_prio,
 412                                       params->write_prio);
 413 }
 414 EXPORT_SYMBOL(omap_set_dma_params);
 415
 416 void omap_set_dma_src_index(int lch, int eidx, int fidx)
 417 {
 418         if (cpu_class_is_omap2())
 419                 return;
 420
 421         p->dma_write(eidx, CSEI, lch);
 422         p->dma_write(fidx, CSFI, lch);
 423 }
 424 EXPORT_SYMBOL(omap_set_dma_src_index);
 425
 426 void omap_set_dma_src_data_pack(int lch, int enable)
 427 {
 428         u32 l;
 429
 430         l = p->dma_read(CSDP, lch);
 431         l &= ~(1 << 6);
 432         if (enable)
 433                 l |= (1 << 6);
 434         p->dma_write(l, CSDP, lch);
 435 }
 436 EXPORT_SYMBOL(omap_set_dma_src_data_pack);
 437
 438 void omap_set_dma_src_burst_mode(int lch, enum omap_dma_burst_mode burst_mode)
 439 {
 440         unsigned int burst = 0;
 441         u32 l;
 442
 443         l = p->dma_read(CSDP, lch);
 444         l &= ~(0x03 << 7);
 445
 446         switch (burst_mode) {
 447         case OMAP_DMA_DATA_BURST_DIS:
 448                 break;
 449         case OMAP_DMA_DATA_BURST_4:
 450                 if (cpu_class_is_omap2())
 451                         burst = 0x1;
 452                 else
 453                         burst = 0x2;
 454                 break;
 455         case OMAP_DMA_DATA_BURST_8:
 456                 if (cpu_class_is_omap2()) {
 457                         burst = 0x2;
 458                         break;
 459                 }
 460                 /*
 461                  * not supported by current hardware on OMAP1
 462                  * w |= (0x03 << 7);
 463                  * fall through
 464                  */
 465         case OMAP_DMA_DATA_BURST_16:
 466                 if (cpu_class_is_omap2()) {
 467                         burst = 0x3;
 468                         break;
 469                 }
 470                 /*
 471                  * OMAP1 don't support burst 16
 472                  * fall through
 473                  */
 474         default:
 475                 BUG();
 476         }
 477
 478         l |= (burst << 7);
 479         p->dma_write(l, CSDP, lch);
 480 }
 481 EXPORT_SYMBOL(omap_set_dma_src_burst_mode);
 482
 483 /* Note that dest_port is only for OMAP1 */
 484 void omap_set_dma_dest_params(int lch, int dest_port, int dest_amode,
 485                               unsigned long dest_start,
 486                               int dst_ei, int dst_fi)
 487 {
 488         u32 l;
 489
 490         if (cpu_class_is_omap1()) {
 491                 l = p->dma_read(CSDP, lch);
 492                 l &= ~(0x1f << 9);
 493                 l |= dest_port << 9;
 494                 p->dma_write(l, CSDP, lch);
 495         }
 496
 497         l = p->dma_read(CCR, lch);
 498         l &= ~(0x03 << 14);
 499         l |= dest_amode << 14;
 500         p->dma_write(l, CCR, lch);
 501
 502         p->dma_write(dest_start, CDSA, lch);
 503
 504         p->dma_write(dst_ei, CDEI, lch);
 505         p->dma_write(dst_fi, CDFI, lch);
 506 }
 507 EXPORT_SYMBOL(omap_set_dma_dest_params);
 508
 509 void omap_set_dma_dest_index(int lch, int eidx, int fidx)
 510 {
 511         if (cpu_class_is_omap2())
 512                 return;
 513
 514         p->dma_write(eidx, CDEI, lch);
 515         p->dma_write(fidx, CDFI, lch);
 516 }
 517 EXPORT_SYMBOL(omap_set_dma_dest_index);
 518
 519 void omap_set_dma_dest_data_pack(int lch, int enable)
 520 {
 521         u32 l;
 522
 523         l = p->dma_read(CSDP, lch);
 524         l &= ~(1 << 13);
 525         if (enable)
 526                 l |= 1 << 13;
 527         p->dma_write(l, CSDP, lch);
 528 }
 529 EXPORT_SYMBOL(omap_set_dma_dest_data_pack);
 530
 531 void omap_set_dma_dest_burst_mode(int lch, enum omap_dma_burst_mode burst_mode)
 532 {
 533         unsigned int burst = 0;
 534         u32 l;
 535
 536         l = p->dma_read(CSDP, lch);
 537         l &= ~(0x03 << 14);
 538
 539         switch (burst_mode) {
 540         case OMAP_DMA_DATA_BURST_DIS:
 541                 break;
 542         case OMAP_DMA_DATA_BURST_4:
 543                 if (cpu_class_is_omap2())
 544                         burst = 0x1;
 545                 else
 546                         burst = 0x2;
 547                 break;
 548         case OMAP_DMA_DATA_BURST_8:
 549                 if (cpu_class_is_omap2())
 550                         burst = 0x2;
 551                 else
 552                         burst = 0x3;
 553                 break;
 554         case OMAP_DMA_DATA_BURST_16:
 555                 if (cpu_class_is_omap2()) {
 556                         burst = 0x3;
 557                         break;
 558                 }
 559                 /*
 560                  * OMAP1 don't support burst 16
 561                  * fall through
 562                  */
 563         default:
 564                 printk(KERN_ERR "Invalid DMA burst mode\n");
 565                 BUG();
 566                 return;
 567         }
 568         l |= (burst << 14);
 569         p->dma_write(l, CSDP, lch);
 570 }
 571 EXPORT_SYMBOL(omap_set_dma_dest_burst_mode);
 572
 573 static inline void omap_enable_channel_irq(int lch)
 574 {
 575         /* Clear CSR */
 576         if (cpu_class_is_omap1())
 577                 p->dma_read(CSR, lch);
 578         else
 579                 p->dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR, lch);
 580
 581         /* Enable some nice interrupts. */
 582         p->dma_write(dma_chan[lch].enabled_irqs, CICR, lch);
 583 }
 584
 585 static inline void omap_disable_channel_irq(int lch)
 586 {
 587         /* disable channel interrupts */
 588         p->dma_write(0, CICR, lch);
 589         /* Clear CSR */
 590         if (cpu_class_is_omap1())
 591                 p->dma_read(CSR, lch);
 592         else
 593                 p->dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR, lch);
 594 }
 595
 596 void omap_enable_dma_irq(int lch, u16 bits)
 597 {
 598         dma_chan[lch].enabled_irqs |= bits;
 599 }
 600 EXPORT_SYMBOL(omap_enable_dma_irq);
 601
 602 void omap_disable_dma_irq(int lch, u16 bits)
 603 {
 604         dma_chan[lch].enabled_irqs &= ~bits;
 605 }
 606 EXPORT_SYMBOL(omap_disable_dma_irq);
 607
 608 static inline void enable_lnk(int lch)
 609 {
 610         u32 l;
 611
 612         l = p->dma_read(CLNK_CTRL, lch);
 613
 614         if (cpu_class_is_omap1())
 615                 l &= ~(1 << 14);
 616
 617         /* Set the ENABLE_LNK bits */
 618         if (dma_chan[lch].next_lch != -1)
 619                 l = dma_chan[lch].next_lch | (1 << 15);
 620
 621 #ifndef CONFIG_ARCH_OMAP1
 622         if (cpu_class_is_omap2())
 623                 if (dma_chan[lch].next_linked_ch != -1)
 624                         l = dma_chan[lch].next_linked_ch | (1 << 15);
 625 #endif
 626
 627         p->dma_write(l, CLNK_CTRL, lch);
 628 }
 629
 630 static inline void disable_lnk(int lch)
 631 {
 632         u32 l;
 633
 634         l = p->dma_read(CLNK_CTRL, lch);
 635
 636         /* Disable interrupts */
 637         omap_disable_channel_irq(lch);
 638
 639         if (cpu_class_is_omap1()) {
 640                 /* Set the STOP_LNK bit */
 641                 l |= 1 << 14;
 642         }
 643
 644         if (cpu_class_is_omap2()) {
 645                 /* Clear the ENABLE_LNK bit */
 646                 l &= ~(1 << 15);
 647         }
 648
 649         p->dma_write(l, CLNK_CTRL, lch);
 650         dma_chan[lch].flags &= ~OMAP_DMA_ACTIVE;
 651 }
 652
 653 static inline void omap2_enable_irq_lch(int lch)
 654 {
 655         u32 val;
 656         unsigned long flags;
 657
 658         if (!cpu_class_is_omap2())
 659                 return;
 660
 661         spin_lock_irqsave(&dma_chan_lock, flags);
 662         /* clear IRQ STATUS */
 663         p->dma_write(1 << lch, IRQSTATUS_L0, lch);
 664         /* Enable interrupt */
 665         val = p->dma_read(IRQENABLE_L0, lch);
 666         val |= 1 << lch;
 667         p->dma_write(val, IRQENABLE_L0, lch);
 668         spin_unlock_irqrestore(&dma_chan_lock, flags);
 669 }
 670
 671 static inline void omap2_disable_irq_lch(int lch)
 672 {
 673         u32 val;
 674         unsigned long flags;
 675
 676         if (!cpu_class_is_omap2())
 677                 return;
 678
 679         spin_lock_irqsave(&dma_chan_lock, flags);
 680         /* Disable interrupt */
 681         val = p->dma_read(IRQENABLE_L0, lch);
 682         val &= ~(1 << lch);
 683         p->dma_write(val, IRQENABLE_L0, lch);
 684         /* clear IRQ STATUS */
 685         p->dma_write(1 << lch, IRQSTATUS_L0, lch);
 686         spin_unlock_irqrestore(&dma_chan_lock, flags);
 687 }
 688
 689 int omap_request_dma(int dev_id, const char *dev_name,
 690                      void (*callback)(int lch, u16 ch_status, void *data),
 691                      void *data, int *dma_ch_out)
 692 {
 693         int ch, free_ch = -1;
 694         unsigned long flags;
 695         struct omap_dma_lch *chan;
 696
 697         spin_lock_irqsave(&dma_chan_lock, flags);
 698         for (ch = 0; ch < dma_chan_count; ch++) {
 699                 if (free_ch == -1 && dma_chan[ch].dev_id == -1) {
 700                         free_ch = ch;
 701                         if (dev_id == 0)
 702                                 break;
 703                 }
 704         }
 705         if (free_ch == -1) {
 706                 spin_unlock_irqrestore(&dma_chan_lock, flags);
 707                 return -EBUSY;
 708         }
 709         chan = dma_chan + free_ch;
 710         chan->dev_id = dev_id;
 711
 712         if (p->clear_lch_regs)
 713                 p->clear_lch_regs(free_ch);
 714
 715         if (cpu_class_is_omap2())
 716                 omap_clear_dma(free_ch);
 717
 718         spin_unlock_irqrestore(&dma_chan_lock, flags);
 719
 720         chan->dev_name = dev_name;
 721         chan->callback = callback;
 722         chan->data = data;
 723         chan->flags = 0;
 724
 725 #ifndef CONFIG_ARCH_OMAP1
 726         if (cpu_class_is_omap2()) {
 727                 chan->chain_id = -1;
 728                 chan->next_linked_ch = -1;
 729         }
 730 #endif
 731
 732         chan->enabled_irqs = OMAP_DMA_DROP_IRQ | OMAP_DMA_BLOCK_IRQ;
 733
 734         if (cpu_class_is_omap1())
 735                 chan->enabled_irqs |= OMAP1_DMA_TOUT_IRQ;
 736         else if (cpu_class_is_omap2())
 737                 chan->enabled_irqs |= OMAP2_DMA_MISALIGNED_ERR_IRQ |
 738                         OMAP2_DMA_TRANS_ERR_IRQ;
 739
 740         if (cpu_is_omap16xx()) {
 741                 /* If the sync device is set, configure it dynamically. */
 742                 if (dev_id != 0) {
 743                         set_gdma_dev(free_ch + 1, dev_id);
 744                         dev_id = free_ch + 1;
 745                 }
 746                 /*
 747                  * Disable the 1510 compatibility mode and set the sync device
 748                  * id.
 749                  */
 750                 p->dma_write(dev_id | (1 << 10), CCR, free_ch);
 751         } else if (cpu_is_omap7xx() || cpu_is_omap15xx()) {
 752                 p->dma_write(dev_id, CCR, free_ch);
 753         }
 754
 755         if (cpu_class_is_omap2()) {
 756                 omap_enable_channel_irq(free_ch);
 757                 omap2_enable_irq_lch(free_ch);
 758         }
 759
 760         *dma_ch_out = free_ch;
 761
 762         return 0;
 763 }
 764 EXPORT_SYMBOL(omap_request_dma);
 765
 766 void omap_free_dma(int lch)
 767 {
 768         unsigned long flags;
 769
 770         if (dma_chan[lch].dev_id == -1) {
 771                 pr_err("omap_dma: trying to free unallocated DMA channel %d\n",
 772                        lch);
 773                 return;
 774         }
 775
 776         /* Disable interrupt for logical channel */
 777         if (cpu_class_is_omap2())
 778                 omap2_disable_irq_lch(lch);
 779
 780         /* Disable all DMA interrupts for the channel. */
 781         omap_disable_channel_irq(lch);
 782
 783         /* Make sure the DMA transfer is stopped. */
 784         p->dma_write(0, CCR, lch);
 785
 786         /* Clear registers */
 787         if (cpu_class_is_omap2())
 788                 omap_clear_dma(lch);
 789
 790         spin_lock_irqsave(&dma_chan_lock, flags);
 791         dma_chan[lch].dev_id = -1;
 792         dma_chan[lch].next_lch = -1;
 793         dma_chan[lch].callback = NULL;
 794         spin_unlock_irqrestore(&dma_chan_lock, flags);
 795 }
 796 EXPORT_SYMBOL(omap_free_dma);
 797
 798 /**
 799  * @brief omap_dma_set_global_params : Set global priority settings for dma
 800  *
 801  * @param arb_rate
 802  * @param max_fifo_depth
 803  * @param tparams - Number of threads to reserve : DMA_THREAD_RESERVE_NORM
 804  *                                                 DMA_THREAD_RESERVE_ONET
 805  *                                                 DMA_THREAD_RESERVE_TWOT
 806  *                                                 DMA_THREAD_RESERVE_THREET
 807  */
 808 void
 809 omap_dma_set_global_params(int arb_rate, int max_fifo_depth, int tparams)
 810 {
 811         u32 reg;
 812
 813         if (!cpu_class_is_omap2()) {
 814                 printk(KERN_ERR "FIXME: no %s on 15xx/16xx\n", __func__);
 815                 return;
 816         }
 817
 818         if (max_fifo_depth == 0)
 819                 max_fifo_depth = 1;
 820         if (arb_rate == 0)
 821                 arb_rate = 1;
 822
 823         reg = 0xff & max_fifo_depth;
 824         reg |= (0x3 & tparams) << 12;
 825         reg |= (arb_rate & 0xff) << 16;
 826
 827         p->dma_write(reg, GCR, 0);
 828 }
 829 EXPORT_SYMBOL(omap_dma_set_global_params);
 830
 831 /**
 832  * @brief omap_dma_set_prio_lch : Set channel wise priority settings
 833  *
 834  * @param lch
 835  * @param read_prio - Read priority
 836  * @param write_prio - Write priority
 837  * Both of the above can be set with one of the following values :
 838  *      DMA_CH_PRIO_HIGH/DMA_CH_PRIO_LOW
 839  */
 840 int
 841 omap_dma_set_prio_lch(int lch, unsigned char read_prio,
 842                       unsigned char write_prio)
 843 {
 844         u32 l;
 845
 846         if (unlikely((lch < 0 || lch >= dma_lch_count))) {
 847                 printk(KERN_ERR "Invalid channel id\n");
 848                 return -EINVAL;
 849         }
 850         l = p->dma_read(CCR, lch);
 851         l &= ~((1 << 6) | (1 << 26));
 852         if (cpu_class_is_omap2() && !cpu_is_omap242x())
 853                 l |= ((read_prio & 0x1) << 6) | ((write_prio & 0x1) << 26);
 854         else
 855                 l |= ((read_prio & 0x1) << 6);
 856
 857         p->dma_write(l, CCR, lch);
 858
 859         return 0;
 860 }
 861 EXPORT_SYMBOL(omap_dma_set_prio_lch);
 862
 863 /*
 864  * Clears any DMA state so the DMA engine is ready to restart with new buffers
 865  * through omap_start_dma(). Any buffers in flight are discarded.
 866  */
 867 void omap_clear_dma(int lch)
 868 {
 869         unsigned long flags;
 870
 871         local_irq_save(flags);
 872         p->clear_dma(lch);
 873         local_irq_restore(flags);
 874 }
 875 EXPORT_SYMBOL(omap_clear_dma);
 876
 877 void omap_start_dma(int lch)
 878 {
 879         u32 l;
 880
 881         /*
 882          * The CPC/CDAC register needs to be initialized to zero
 883          * before starting dma transfer.
 884          */
 885         if (cpu_is_omap15xx())
 886                 p->dma_write(0, CPC, lch);
 887         else
 888                 p->dma_write(0, CDAC, lch);
 889
 890         if (!omap_dma_in_1510_mode() && dma_chan[lch].next_lch != -1) {
 891                 int next_lch, cur_lch;
 892                 char dma_chan_link_map[MAX_LOGICAL_DMA_CH_COUNT];
 893
 894                 dma_chan_link_map[lch] = 1;
 895                 /* Set the link register of the first channel */
 896                 enable_lnk(lch);
 897
 898                 memset(dma_chan_link_map, 0, sizeof(dma_chan_link_map));
 899                 cur_lch = dma_chan[lch].next_lch;
 900                 do {
 901                         next_lch = dma_chan[cur_lch].next_lch;
 902
 903                         /* The loop case: we've been here already */
 904                         if (dma_chan_link_map[cur_lch])
 905                                 break;
 906                         /* Mark the current channel */
 907                         dma_chan_link_map[cur_lch] = 1;
 908
 909                         enable_lnk(cur_lch);
 910                         omap_enable_channel_irq(cur_lch);
 911
 912                         cur_lch = next_lch;
 913                 } while (next_lch != -1);
 914         } else if (IS_DMA_ERRATA(DMA_ERRATA_PARALLEL_CHANNELS))
 915                 p->dma_write(lch, CLNK_CTRL, lch);
 916
 917         omap_enable_channel_irq(lch);
 918
 919         l = p->dma_read(CCR, lch);
 920
 921         if (IS_DMA_ERRATA(DMA_ERRATA_IFRAME_BUFFERING))
 922                         l |= OMAP_DMA_CCR_BUFFERING_DISABLE;
 923         l |= OMAP_DMA_CCR_EN;
 924
 925         /*
 926          * As dma_write() uses IO accessors which are weakly ordered, there
 927          * is no guarantee that data in coherent DMA memory will be visible
 928          * to the DMA device.  Add a memory barrier here to ensure that any
 929          * such data is visible prior to enabling DMA.
 930          */
 931         mb();
 932         p->dma_write(l, CCR, lch);
 933
 934         dma_chan[lch].flags |= OMAP_DMA_ACTIVE;
 935 }
 936 EXPORT_SYMBOL(omap_start_dma);
 937
 938 void omap_stop_dma(int lch)
 939 {
 940         u32 l;
 941
 942         /* Disable all interrupts on the channel */
 943         omap_disable_channel_irq(lch);
 944
 945         l = p->dma_read(CCR, lch);
 946         if (IS_DMA_ERRATA(DMA_ERRATA_i541) &&
 947                         (l & OMAP_DMA_CCR_SEL_SRC_DST_SYNC)) {
 948                 int i = 0;
 949                 u32 sys_cf;
 950
 951                 /* Configure No-Standby */
 952                 l = p->dma_read(OCP_SYSCONFIG, lch);
 953                 sys_cf = l;
 954                 l &= ~DMA_SYSCONFIG_MIDLEMODE_MASK;
 955                 l |= DMA_SYSCONFIG_MIDLEMODE(DMA_IDLEMODE_NO_IDLE);
 956                 p->dma_write(l , OCP_SYSCONFIG, 0);
 957
 958                 l = p->dma_read(CCR, lch);
 959                 l &= ~OMAP_DMA_CCR_EN;
 960                 p->dma_write(l, CCR, lch);
 961
 962                 /* Wait for sDMA FIFO drain */
 963                 l = p->dma_read(CCR, lch);
 964                 while (i < 100 && (l & (OMAP_DMA_CCR_RD_ACTIVE |
 965                                         OMAP_DMA_CCR_WR_ACTIVE))) {
 966                         udelay(5);
 967                         i++;
 968                         l = p->dma_read(CCR, lch);
 969                 }
 970                 if (i >= 100)
 971                         printk(KERN_ERR "DMA drain did not complete on "
 972                                         "lch %d\n", lch);
 973                 /* Restore OCP_SYSCONFIG */
 974                 p->dma_write(sys_cf, OCP_SYSCONFIG, lch);
 975         } else {
 976                 l &= ~OMAP_DMA_CCR_EN;
 977                 p->dma_write(l, CCR, lch);
 978         }
 979
 980         /*
 981          * Ensure that data transferred by DMA is visible to any access
 982          * after DMA has been disabled.  This is important for coherent
 983          * DMA regions.
 984          */
 985         mb();
 986
 987         if (!omap_dma_in_1510_mode() && dma_chan[lch].next_lch != -1) {
 988                 int next_lch, cur_lch = lch;
 989                 char dma_chan_link_map[MAX_LOGICAL_DMA_CH_COUNT];
 990
 991                 memset(dma_chan_link_map, 0, sizeof(dma_chan_link_map));
 992                 do {
 993                         /* The loop case: we've been here already */
 994                         if (dma_chan_link_map[cur_lch])
 995                                 break;
 996                         /* Mark the current channel */
 997                         dma_chan_link_map[cur_lch] = 1;
 998
 999                         disable_lnk(cur_lch);
1000
1001                         next_lch = dma_chan[cur_lch].next_lch;
1002                         cur_lch = next_lch;
1003                 } while (next_lch != -1);
1004         }
1005
1006         dma_chan[lch].flags &= ~OMAP_DMA_ACTIVE;
1007 }
1008 EXPORT_SYMBOL(omap_stop_dma);
1009
1010 /*
1011  * Allows changing the DMA callback function or data. This may be needed if
1012  * the driver shares a single DMA channel for multiple dma triggers.
1013  */
1014 int omap_set_dma_callback(int lch,
1015                           void (*callback)(int lch, u16 ch_status, void *data),
1016                           void *data)
1017 {
1018         unsigned long flags;
1019
1020         if (lch < 0)
1021                 return -ENODEV;
1022
1023         spin_lock_irqsave(&dma_chan_lock, flags);
1024         if (dma_chan[lch].dev_id == -1) {
1025                 printk(KERN_ERR "DMA callback for not set for free channel\n");
1026                 spin_unlock_irqrestore(&dma_chan_lock, flags);
1027                 return -EINVAL;
1028         }
1029         dma_chan[lch].callback = callback;
1030         dma_chan[lch].data = data;
1031         spin_unlock_irqrestore(&dma_chan_lock, flags);
1032
1033         return 0;
1034 }
1035 EXPORT_SYMBOL(omap_set_dma_callback);
1036
1037 /*
1038  * Returns current physical source address for the given DMA channel.
1039  * If the channel is running the caller must disable interrupts prior calling
1040  * this function and process the returned value before re-enabling interrupt to
1041  * prevent races with the interrupt handler. Note that in continuous mode there
1042  * is a chance for CSSA_L register overflow between the two reads resulting
1043  * in incorrect return value.
1044  */
1045 dma_addr_t omap_get_dma_src_pos(int lch)
1046 {
1047         dma_addr_t offset = 0;
1048
1049         if (cpu_is_omap15xx())
1050                 offset = p->dma_read(CPC, lch);
1051         else
1052                 offset = p->dma_read(CSAC, lch);
1053
1054         if (IS_DMA_ERRATA(DMA_ERRATA_3_3) && offset == 0)
1055                 offset = p->dma_read(CSAC, lch);
1056
1057         if (!cpu_is_omap15xx()) {
1058                 /*
1059                  * CDAC == 0 indicates that the DMA transfer on the channel has
1060                  * not been started (no data has been transferred so far).
1061                  * Return the programmed source start address in this case.
1062                  */
1063                 if (likely(p->dma_read(CDAC, lch)))
1064                         offset = p->dma_read(CSAC, lch);
1065                 else
1066                         offset = p->dma_read(CSSA, lch);
1067         }
1068
1069         if (cpu_class_is_omap1())
1070                 offset |= (p->dma_read(CSSA, lch) & 0xFFFF0000);
1071
1072         return offset;
1073 }
1074 EXPORT_SYMBOL(omap_get_dma_src_pos);
1075
1076 /*
1077  * Returns current physical destination address for the given DMA channel.
1078  * If the channel is running the caller must disable interrupts prior calling
1079  * this function and process the returned value before re-enabling interrupt to
1080  * prevent races with the interrupt handler. Note that in continuous mode there
1081  * is a chance for CDSA_L register overflow between the two reads resulting
1082  * in incorrect return value.
1083  */
1084 dma_addr_t omap_get_dma_dst_pos(int lch)
1085 {
1086         dma_addr_t offset = 0;
1087
1088         if (cpu_is_omap15xx())
1089                 offset = p->dma_read(CPC, lch);
1090         else
1091                 offset = p->dma_read(CDAC, lch);
1092
1093         /*
1094          * omap 3.2/3.3 erratum: sometimes 0 is returned if CSAC/CDAC is
1095          * read before the DMA controller finished disabling the channel.
1096          */
1097         if (!cpu_is_omap15xx() && offset == 0) {
1098                 offset = p->dma_read(CDAC, lch);
1099                 /*
1100                  * CDAC == 0 indicates that the DMA transfer on the channel has
1101                  * not been started (no data has been transferred so far).
1102                  * Return the programmed destination start address in this case.
1103                  */
1104                 if (unlikely(!offset))
1105                         offset = p->dma_read(CDSA, lch);
1106         }
1107
1108         if (cpu_class_is_omap1())
1109                 offset |= (p->dma_read(CDSA, lch) & 0xFFFF0000);
1110
1111         return offset;
1112 }
1113 EXPORT_SYMBOL(omap_get_dma_dst_pos);
1114
1115 int omap_get_dma_active_status(int lch)
1116 {
1117         return (p->dma_read(CCR, lch) & OMAP_DMA_CCR_EN) != 0;
1118 }
1119 EXPORT_SYMBOL(omap_get_dma_active_status);
1120
1121 int omap_dma_running(void)
1122 {
1123         int lch;
1124
1125         if (cpu_class_is_omap1())
1126                 if (omap_lcd_dma_running())
1127                         return 1;
1128
1129         for (lch = 0; lch < dma_chan_count; lch++)
1130                 if (p->dma_read(CCR, lch) & OMAP_DMA_CCR_EN)
1131                         return 1;
1132
1133         return 0;
1134 }
1135
1136 /*
1137  * lch_queue DMA will start right after lch_head one is finished.
1138  * For this DMA link to start, you still need to start (see omap_start_dma)
1139  * the first one. That will fire up the entire queue.
1140  */
1141 void omap_dma_link_lch(int lch_head, int lch_queue)
1142 {
1143         if (omap_dma_in_1510_mode()) {
1144                 if (lch_head == lch_queue) {
1145                         p->dma_write(p->dma_read(CCR, lch_head) | (3 << 8),
1146                                                                 CCR, lch_head);
1147                         return;
1148                 }
1149                 printk(KERN_ERR "DMA linking is not supported in 1510 mode\n");
1150                 BUG();
1151                 return;
1152         }
1153
1154         if ((dma_chan[lch_head].dev_id == -1) ||
1155             (dma_chan[lch_queue].dev_id == -1)) {
1156                 printk(KERN_ERR "omap_dma: trying to link "
1157                        "non requested channels\n");
1158                 dump_stack();
1159         }
1160
1161         dma_chan[lch_head].next_lch = lch_queue;
1162 }
1163 EXPORT_SYMBOL(omap_dma_link_lch);
1164
1165 /*
1166  * Once the DMA queue is stopped, we can destroy it.
1167  */
1168 void omap_dma_unlink_lch(int lch_head, int lch_queue)
1169 {
1170         if (omap_dma_in_1510_mode()) {
1171                 if (lch_head == lch_queue) {
1172                         p->dma_write(p->dma_read(CCR, lch_head) & ~(3 << 8),
1173                                                                 CCR, lch_head);
1174                         return;
1175                 }
1176                 printk(KERN_ERR "DMA linking is not supported in 1510 mode\n");
1177                 BUG();
1178                 return;
1179         }
1180
1181         if (dma_chan[lch_head].next_lch != lch_queue ||
1182             dma_chan[lch_head].next_lch == -1) {
1183                 printk(KERN_ERR "omap_dma: trying to unlink "
1184                        "non linked channels\n");
1185                 dump_stack();
1186         }
1187
1188         if ((dma_chan[lch_head].flags & OMAP_DMA_ACTIVE) ||
1189             (dma_chan[lch_queue].flags & OMAP_DMA_ACTIVE)) {
1190                 printk(KERN_ERR "omap_dma: You need to stop the DMA channels "
1191                        "before unlinking\n");
1192                 dump_stack();
1193         }
1194
1195         dma_chan[lch_head].next_lch = -1;
1196 }
1197 EXPORT_SYMBOL(omap_dma_unlink_lch);
1198
1199 #ifndef CONFIG_ARCH_OMAP1
1200 /* Create chain of DMA channesls */
1201 static void create_dma_lch_chain(int lch_head, int lch_queue)
1202 {
1203         u32 l;
1204
1205         /* Check if this is the first link in chain */
1206         if (dma_chan[lch_head].next_linked_ch == -1) {
1207                 dma_chan[lch_head].next_linked_ch = lch_queue;
1208                 dma_chan[lch_head].prev_linked_ch = lch_queue;
1209                 dma_chan[lch_queue].next_linked_ch = lch_head;
1210                 dma_chan[lch_queue].prev_linked_ch = lch_head;
1211         }
1212
1213         /* a link exists, link the new channel in circular chain */
1214         else {
1215                 dma_chan[lch_queue].next_linked_ch =
1216                                         dma_chan[lch_head].next_linked_ch;
1217                 dma_chan[lch_queue].prev_linked_ch = lch_head;
1218                 dma_chan[lch_head].next_linked_ch = lch_queue;
1219                 dma_chan[dma_chan[lch_queue].next_linked_ch].prev_linked_ch =
1220                                         lch_queue;
1221         }
1222
1223         l = p->dma_read(CLNK_CTRL, lch_head);
1224         l &= ~(0x1f);
1225         l |= lch_queue;
1226         p->dma_write(l, CLNK_CTRL, lch_head);
1227
1228         l = p->dma_read(CLNK_CTRL, lch_queue);
1229         l &= ~(0x1f);
1230         l |= (dma_chan[lch_queue].next_linked_ch);
1231         p->dma_write(l, CLNK_CTRL, lch_queue);
1232 }
1233
1234 /**
1235  * @brief omap_request_dma_chain : Request a chain of DMA channels
1236  *
1237  * @param dev_id - Device id using the dma channel
1238  * @param dev_name - Device name
1239  * @param callback - Call back function
1240  * @chain_id -
1241  * @no_of_chans - Number of channels requested
1242  * @chain_mode - Dynamic or static chaining : OMAP_DMA_STATIC_CHAIN
1243  *                                            OMAP_DMA_DYNAMIC_CHAIN
1244  * @params - Channel parameters
1245  *
1246  * @return - Success : 0
1247  *           Failure: -EINVAL/-ENOMEM
1248  */
1249 int omap_request_dma_chain(int dev_id, const char *dev_name,
1250                            void (*callback) (int lch, u16 ch_status,
1251                                              void *data),
1252                            int *chain_id, int no_of_chans, int chain_mode,
1253                            struct omap_dma_channel_params params)
1254 {
1255         int *channels;
1256         int i, err;
1257
1258         /* Is the chain mode valid ? */
1259         if (chain_mode != OMAP_DMA_STATIC_CHAIN
1260                         && chain_mode != OMAP_DMA_DYNAMIC_CHAIN) {
1261                 printk(KERN_ERR "Invalid chain mode requested\n");
1262                 return -EINVAL;
1263         }
1264
1265         if (unlikely((no_of_chans < 1
1266                         || no_of_chans > dma_lch_count))) {
1267                 printk(KERN_ERR "Invalid Number of channels requested\n");
1268                 return -EINVAL;
1269         }
1270
1271         /*
1272          * Allocate a queue to maintain the status of the channels
1273          * in the chain
1274          */
1275         channels = kmalloc(sizeof(*channels) * no_of_chans, GFP_KERNEL);
1276         if (channels == NULL) {
1277                 printk(KERN_ERR "omap_dma: No memory for channel queue\n");
1278                 return -ENOMEM;
1279         }
1280
1281         /* request and reserve DMA channels for the chain */
1282         for (i = 0; i < no_of_chans; i++) {
1283                 err = omap_request_dma(dev_id, dev_name,
1284                                         callback, NULL, &channels[i]);
1285                 if (err < 0) {
1286                         int j;
1287                         for (j = 0; j < i; j++)
1288                                 omap_free_dma(channels[j]);
1289                         kfree(channels);
1290                         printk(KERN_ERR "omap_dma: Request failed %d\n", err);
1291                         return err;
1292                 }
1293                 dma_chan[channels[i]].prev_linked_ch = -1;
1294                 dma_chan[channels[i]].state = DMA_CH_NOTSTARTED;
1295
1296                 /*
1297                  * Allowing client drivers to set common parameters now,
1298                  * so that later only relevant (src_start, dest_start
1299                  * and element count) can be set
1300                  */
1301                 omap_set_dma_params(channels[i], &params);
1302         }
1303
1304         *chain_id = channels[0];
1305         dma_linked_lch[*chain_id].linked_dmach_q = channels;
1306         dma_linked_lch[*chain_id].chain_mode = chain_mode;
1307         dma_linked_lch[*chain_id].chain_state = DMA_CHAIN_NOTSTARTED;
1308         dma_linked_lch[*chain_id].no_of_lchs_linked = no_of_chans;
1309
1310         for (i = 0; i < no_of_chans; i++)
1311                 dma_chan[channels[i]].chain_id = *chain_id;
1312
1313         /* Reset the Queue pointers */
1314         OMAP_DMA_CHAIN_QINIT(*chain_id);
1315
1316         /* Set up the chain */
1317         if (no_of_chans == 1)
1318                 create_dma_lch_chain(channels[0], channels[0]);
1319         else {
1320                 for (i = 0; i < (no_of_chans - 1); i++)
1321                         create_dma_lch_chain(channels[i], channels[i + 1]);
1322         }
1323
1324         return 0;
1325 }
1326 EXPORT_SYMBOL(omap_request_dma_chain);
1327
1328 /**
1329  * @brief omap_modify_dma_chain_param : Modify the chain's params - Modify the
1330  * params after setting it. Dont do this while dma is running!!
1331  *
1332  * @param chain_id - Chained logical channel id.
1333  * @param params
1334  *
1335  * @return - Success : 0
1336  *           Failure : -EINVAL
1337  */
1338 int omap_modify_dma_chain_params(int chain_id,
1339                                 struct omap_dma_channel_params params)
1340 {
1341         int *channels;
1342         u32 i;
1343
1344         /* Check for input params */
1345         if (unlikely((chain_id < 0
1346                         || chain_id >= dma_lch_count))) {
1347                 printk(KERN_ERR "Invalid chain id\n");
1348                 return -EINVAL;
1349         }
1350
1351         /* Check if the chain exists */
1352         if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1353                 printk(KERN_ERR "Chain doesn't exists\n");
1354                 return -EINVAL;
1355         }
1356         channels = dma_linked_lch[chain_id].linked_dmach_q;
1357
1358         for (i = 0; i < dma_linked_lch[chain_id].no_of_lchs_linked; i++) {
1359                 /*
1360                  * Allowing client drivers to set common parameters now,
1361                  * so that later only relevant (src_start, dest_start
1362                  * and element count) can be set
1363                  */
1364                 omap_set_dma_params(channels[i], &params);
1365         }
1366
1367         return 0;
1368 }
1369 EXPORT_SYMBOL(omap_modify_dma_chain_params);
1370
1371 /**
1372  * @brief omap_free_dma_chain - Free all the logical channels in a chain.
1373  *
1374  * @param chain_id
1375  *
1376  * @return - Success : 0
1377  *           Failure : -EINVAL
1378  */
1379 int omap_free_dma_chain(int chain_id)
1380 {
1381         int *channels;
1382         u32 i;
1383
1384         /* Check for input params */
1385         if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1386                 printk(KERN_ERR "Invalid chain id\n");
1387                 return -EINVAL;
1388         }
1389
1390         /* Check if the chain exists */
1391         if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1392                 printk(KERN_ERR "Chain doesn't exists\n");
1393                 return -EINVAL;
1394         }
1395
1396         channels = dma_linked_lch[chain_id].linked_dmach_q;
1397         for (i = 0; i < dma_linked_lch[chain_id].no_of_lchs_linked; i++) {
1398                 dma_chan[channels[i]].next_linked_ch = -1;
1399                 dma_chan[channels[i]].prev_linked_ch = -1;
1400                 dma_chan[channels[i]].chain_id = -1;
1401                 dma_chan[channels[i]].state = DMA_CH_NOTSTARTED;
1402                 omap_free_dma(channels[i]);
1403         }
1404
1405         kfree(channels);
1406
1407         dma_linked_lch[chain_id].linked_dmach_q = NULL;
1408         dma_linked_lch[chain_id].chain_mode = -1;
1409         dma_linked_lch[chain_id].chain_state = -1;
1410
1411         return (0);
1412 }
1413 EXPORT_SYMBOL(omap_free_dma_chain);
1414
1415 /**
1416  * @brief omap_dma_chain_status - Check if the chain is in
1417  * active / inactive state.
1418  * @param chain_id
1419  *
1420  * @return - Success : OMAP_DMA_CHAIN_ACTIVE/OMAP_DMA_CHAIN_INACTIVE
1421  *           Failure : -EINVAL
1422  */
1423 int omap_dma_chain_status(int chain_id)
1424 {
1425         /* Check for input params */
1426         if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1427                 printk(KERN_ERR "Invalid chain id\n");
1428                 return -EINVAL;
1429         }
1430
1431         /* Check if the chain exists */
1432         if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1433                 printk(KERN_ERR "Chain doesn't exists\n");
1434                 return -EINVAL;
1435         }
1436         pr_debug("CHAINID=%d, qcnt=%d\n", chain_id,
1437                         dma_linked_lch[chain_id].q_count);
1438
1439         if (OMAP_DMA_CHAIN_QEMPTY(chain_id))
1440                 return OMAP_DMA_CHAIN_INACTIVE;
1441
1442         return OMAP_DMA_CHAIN_ACTIVE;
1443 }
1444 EXPORT_SYMBOL(omap_dma_chain_status);
1445
1446 /**
1447  * @brief omap_dma_chain_a_transfer - Get a free channel from a chain,
1448  * set the params and start the transfer.
1449  *
1450  * @param chain_id
1451  * @param src_start - buffer start address
1452  * @param dest_start - Dest address
1453  * @param elem_count
1454  * @param frame_count
1455  * @param callbk_data - channel callback parameter data.
1456  *
1457  * @return  - Success : 0
1458  *            Failure: -EINVAL/-EBUSY
1459  */
1460 int omap_dma_chain_a_transfer(int chain_id, int src_start, int dest_start,
1461                         int elem_count, int frame_count, void *callbk_data)
1462 {
1463         int *channels;
1464         u32 l, lch;
1465         int start_dma = 0;
1466
1467         /*
1468          * if buffer size is less than 1 then there is
1469          * no use of starting the chain
1470          */
1471         if (elem_count < 1) {
1472                 printk(KERN_ERR "Invalid buffer size\n");
1473                 return -EINVAL;
1474         }
1475
1476         /* Check for input params */
1477         if (unlikely((chain_id < 0
1478                         || chain_id >= dma_lch_count))) {
1479                 printk(KERN_ERR "Invalid chain id\n");
1480                 return -EINVAL;
1481         }
1482
1483         /* Check if the chain exists */
1484         if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1485                 printk(KERN_ERR "Chain doesn't exist\n");
1486                 return -EINVAL;
1487         }
1488
1489         /* Check if all the channels in chain are in use */
1490         if (OMAP_DMA_CHAIN_QFULL(chain_id))
1491                 return -EBUSY;
1492
1493         /* Frame count may be negative in case of indexed transfers */
1494         channels = dma_linked_lch[chain_id].linked_dmach_q;
1495
1496         /* Get a free channel */
1497         lch = channels[dma_linked_lch[chain_id].q_tail];
1498
1499         /* Store the callback data */
1500         dma_chan[lch].data = callbk_data;
1501
1502         /* Increment the q_tail */
1503         OMAP_DMA_CHAIN_INCQTAIL(chain_id);
1504
1505         /* Set the params to the free channel */
1506         if (src_start != 0)
1507                 p->dma_write(src_start, CSSA, lch);
1508         if (dest_start != 0)
1509                 p->dma_write(dest_start, CDSA, lch);
1510
1511         /* Write the buffer size */
1512         p->dma_write(elem_count, CEN, lch);
1513         p->dma_write(frame_count, CFN, lch);
1514
1515         /*
1516          * If the chain is dynamically linked,
1517          * then we may have to start the chain if its not active
1518          */
1519         if (dma_linked_lch[chain_id].chain_mode == OMAP_DMA_DYNAMIC_CHAIN) {
1520
1521                 /*
1522                  * In Dynamic chain, if the chain is not started,
1523                  * queue the channel
1524                  */
1525                 if (dma_linked_lch[chain_id].chain_state ==
1526                                                 DMA_CHAIN_NOTSTARTED) {
1527                         /* Enable the link in previous channel */
1528                         if (dma_chan[dma_chan[lch].prev_linked_ch].state ==
1529                                                                 DMA_CH_QUEUED)
1530                                 enable_lnk(dma_chan[lch].prev_linked_ch);
1531                         dma_chan[lch].state = DMA_CH_QUEUED;
1532                 }
1533
1534                 /*
1535                  * Chain is already started, make sure its active,
1536                  * if not then start the chain
1537                  */
1538                 else {
1539                         start_dma = 1;
1540
1541                         if (dma_chan[dma_chan[lch].prev_linked_ch].state ==
1542                                                         DMA_CH_STARTED) {
1543                                 enable_lnk(dma_chan[lch].prev_linked_ch);
1544                                 dma_chan[lch].state = DMA_CH_QUEUED;
1545                                 start_dma = 0;
1546                                 if (0 == ((1 << 7) & p->dma_read(
1547                                         CCR, dma_chan[lch].prev_linked_ch))) {
1548                                         disable_lnk(dma_chan[lch].
1549                                                     prev_linked_ch);
1550                                         pr_debug("\n prev ch is stopped\n");
1551                                         start_dma = 1;
1552                                 }
1553                         }
1554
1555                         else if (dma_chan[dma_chan[lch].prev_linked_ch].state
1556                                                         == DMA_CH_QUEUED) {
1557                                 enable_lnk(dma_chan[lch].prev_linked_ch);
1558                                 dma_chan[lch].state = DMA_CH_QUEUED;
1559                                 start_dma = 0;
1560                         }
1561                         omap_enable_channel_irq(lch);
1562
1563                         l = p->dma_read(CCR, lch);
1564
1565                         if ((0 == (l & (1 << 24))))
1566                                 l &= ~(1 << 25);
1567                         else
1568                                 l |= (1 << 25);
1569                         if (start_dma == 1) {
1570                                 if (0 == (l & (1 << 7))) {
1571                                         l |= (1 << 7);
1572                                         dma_chan[lch].state = DMA_CH_STARTED;
1573                                         pr_debug("starting %d\n", lch);
1574                                         p->dma_write(l, CCR, lch);
1575                                 } else
1576                                         start_dma = 0;
1577                         } else {
1578                                 if (0 == (l & (1 << 7)))
1579                                         p->dma_write(l, CCR, lch);
1580                         }
1581                         dma_chan[lch].flags |= OMAP_DMA_ACTIVE;
1582                 }
1583         }
1584
1585         return 0;
1586 }
1587 EXPORT_SYMBOL(omap_dma_chain_a_transfer);
1588
1589 /**
1590  * @brief omap_start_dma_chain_transfers - Start the chain
1591  *
1592  * @param chain_id
1593  *
1594  * @return - Success : 0
1595  *           Failure : -EINVAL/-EBUSY
1596  */
1597 int omap_start_dma_chain_transfers(int chain_id)
1598 {
1599         int *channels;
1600         u32 l, i;
1601
1602         if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1603                 printk(KERN_ERR "Invalid chain id\n");
1604                 return -EINVAL;
1605         }
1606
1607         channels = dma_linked_lch[chain_id].linked_dmach_q;
1608
1609         if (dma_linked_lch[channels[0]].chain_state == DMA_CHAIN_STARTED) {
1610                 printk(KERN_ERR "Chain is already started\n");
1611                 return -EBUSY;
1612         }
1613
1614         if (dma_linked_lch[chain_id].chain_mode == OMAP_DMA_STATIC_CHAIN) {
1615                 for (i = 0; i < dma_linked_lch[chain_id].no_of_lchs_linked;
1616                                                                         i++) {
1617                         enable_lnk(channels[i]);
1618                         omap_enable_channel_irq(channels[i]);
1619                 }
1620         } else {
1621                 omap_enable_channel_irq(channels[0]);
1622         }
1623
1624         l = p->dma_read(CCR, channels[0]);
1625         l |= (1 << 7);
1626         dma_linked_lch[chain_id].chain_state = DMA_CHAIN_STARTED;
1627         dma_chan[channels[0]].state = DMA_CH_STARTED;
1628
1629         if ((0 == (l & (1 << 24))))
1630                 l &= ~(1 << 25);
1631         else
1632                 l |= (1 << 25);
1633         p->dma_write(l, CCR, channels[0]);
1634
1635         dma_chan[channels[0]].flags |= OMAP_DMA_ACTIVE;
1636
1637         return 0;
1638 }
1639 EXPORT_SYMBOL(omap_start_dma_chain_transfers);
1640
1641 /**
1642  * @brief omap_stop_dma_chain_transfers - Stop the dma transfer of a chain.
1643  *
1644  * @param chain_id
1645  *
1646  * @return - Success : 0
1647  *           Failure : EINVAL
1648  */
1649 int omap_stop_dma_chain_transfers(int chain_id)
1650 {
1651         int *channels;
1652         u32 l, i;
1653         u32 sys_cf = 0;
1654
1655         /* Check for input params */
1656         if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1657                 printk(KERN_ERR "Invalid chain id\n");
1658                 return -EINVAL;
1659         }
1660
1661         /* Check if the chain exists */
1662         if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1663                 printk(KERN_ERR "Chain doesn't exists\n");
1664                 return -EINVAL;
1665         }
1666         channels = dma_linked_lch[chain_id].linked_dmach_q;
1667
1668         if (IS_DMA_ERRATA(DMA_ERRATA_i88)) {
1669                 sys_cf = p->dma_read(OCP_SYSCONFIG, 0);
1670                 l = sys_cf;
1671                 /* Middle mode reg set no Standby */
1672                 l &= ~((1 << 12)|(1 << 13));
1673                 p->dma_write(l, OCP_SYSCONFIG, 0);
1674         }
1675
1676         for (i = 0; i < dma_linked_lch[chain_id].no_of_lchs_linked; i++) {
1677
1678                 /* Stop the Channel transmission */
1679                 l = p->dma_read(CCR, channels[i]);
1680                 l &= ~(1 << 7);
1681                 p->dma_write(l, CCR, channels[i]);
1682
1683                 /* Disable the link in all the channels */
1684                 disable_lnk(channels[i]);
1685                 dma_chan[channels[i]].state = DMA_CH_NOTSTARTED;
1686
1687         }
1688         dma_linked_lch[chain_id].chain_state = DMA_CHAIN_NOTSTARTED;
1689
1690         /* Reset the Queue pointers */
1691         OMAP_DMA_CHAIN_QINIT(chain_id);
1692
1693         if (IS_DMA_ERRATA(DMA_ERRATA_i88))
1694                 p->dma_write(sys_cf, OCP_SYSCONFIG, 0);
1695
1696         return 0;
1697 }
1698 EXPORT_SYMBOL(omap_stop_dma_chain_transfers);
1699
1700 /* Get the index of the ongoing DMA in chain */
1701 /**
1702  * @brief omap_get_dma_chain_index - Get the element and frame index
1703  * of the ongoing DMA in chain
1704  *
1705  * @param chain_id
1706  * @param ei - Element index
1707  * @param fi - Frame index
1708  *
1709  * @return - Success : 0
1710  *           Failure : -EINVAL
1711  */
1712 int omap_get_dma_chain_index(int chain_id, int *ei, int *fi)
1713 {
1714         int lch;
1715         int *channels;
1716
1717         /* Check for input params */
1718         if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1719                 printk(KERN_ERR "Invalid chain id\n");
1720                 return -EINVAL;
1721         }
1722
1723         /* Check if the chain exists */
1724         if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1725                 printk(KERN_ERR "Chain doesn't exists\n");
1726                 return -EINVAL;
1727         }
1728         if ((!ei) || (!fi))
1729                 return -EINVAL;
1730
1731         channels = dma_linked_lch[chain_id].linked_dmach_q;
1732
1733         /* Get the current channel */
1734         lch = channels[dma_linked_lch[chain_id].q_head];
1735
1736         *ei = p->dma_read(CCEN, lch);
1737         *fi = p->dma_read(CCFN, lch);
1738
1739         return 0;
1740 }
1741 EXPORT_SYMBOL(omap_get_dma_chain_index);
1742
1743 /**
1744  * @brief omap_get_dma_chain_dst_pos - Get the destination position of the
1745  * ongoing DMA in chain
1746  *
1747  * @param chain_id
1748  *
1749  * @return - Success : Destination position
1750  *           Failure : -EINVAL
1751  */
1752 int omap_get_dma_chain_dst_pos(int chain_id)
1753 {
1754         int lch;
1755         int *channels;
1756
1757         /* Check for input params */
1758         if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1759                 printk(KERN_ERR "Invalid chain id\n");
1760                 return -EINVAL;
1761         }
1762
1763         /* Check if the chain exists */
1764         if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1765                 printk(KERN_ERR "Chain doesn't exists\n");
1766                 return -EINVAL;
1767         }
1768
1769         channels = dma_linked_lch[chain_id].linked_dmach_q;
1770
1771         /* Get the current channel */
1772         lch = channels[dma_linked_lch[chain_id].q_head];
1773
1774         return p->dma_read(CDAC, lch);
1775 }
1776 EXPORT_SYMBOL(omap_get_dma_chain_dst_pos);
1777
1778 /**
1779  * @brief omap_get_dma_chain_src_pos - Get the source position
1780  * of the ongoing DMA in chain
1781  * @param chain_id
1782  *
1783  * @return - Success : Destination position
1784  *           Failure : -EINVAL
1785  */
1786 int omap_get_dma_chain_src_pos(int chain_id)
1787 {
1788         int lch;
1789         int *channels;
1790
1791         /* Check for input params */
1792         if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1793                 printk(KERN_ERR "Invalid chain id\n");
1794                 return -EINVAL;
1795         }
1796
1797         /* Check if the chain exists */
1798         if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1799                 printk(KERN_ERR "Chain doesn't exists\n");
1800                 return -EINVAL;
1801         }
1802
1803         channels = dma_linked_lch[chain_id].linked_dmach_q;
1804
1805         /* Get the current channel */
1806         lch = channels[dma_linked_lch[chain_id].q_head];
1807
1808         return p->dma_read(CSAC, lch);
1809 }
1810 EXPORT_SYMBOL(omap_get_dma_chain_src_pos);
1811 #endif  /* ifndef CONFIG_ARCH_OMAP1 */
1812
1813 /*----------------------------------------------------------------------------*/
1814
1815 #ifdef CONFIG_ARCH_OMAP1
1816
1817 static int omap1_dma_handle_ch(int ch)
1818 {
1819         u32 csr;
1820
1821         if (enable_1510_mode && ch >= 6) {
1822                 csr = dma_chan[ch].saved_csr;
1823                 dma_chan[ch].saved_csr = 0;
1824         } else
1825                 csr = p->dma_read(CSR, ch);
1826         if (enable_1510_mode && ch <= 2 && (csr >> 7) != 0) {
1827                 dma_chan[ch + 6].saved_csr = csr >> 7;
1828                 csr &= 0x7f;
1829         }
1830         if ((csr & 0x3f) == 0)
1831                 return 0;
1832         if (unlikely(dma_chan[ch].dev_id == -1)) {
1833                 printk(KERN_WARNING "Spurious interrupt from DMA channel "
1834                        "%d (CSR %04x)\n", ch, csr);
1835                 return 0;
1836         }
1837         if (unlikely(csr & OMAP1_DMA_TOUT_IRQ))
1838                 printk(KERN_WARNING "DMA timeout with device %d\n",
1839                        dma_chan[ch].dev_id);
1840         if (unlikely(csr & OMAP_DMA_DROP_IRQ))
1841                 printk(KERN_WARNING "DMA synchronization event drop occurred "
1842                        "with device %d\n", dma_chan[ch].dev_id);
1843         if (likely(csr & OMAP_DMA_BLOCK_IRQ))
1844                 dma_chan[ch].flags &= ~OMAP_DMA_ACTIVE;
1845         if (likely(dma_chan[ch].callback != NULL))
1846                 dma_chan[ch].callback(ch, csr, dma_chan[ch].data);
1847
1848         return 1;
1849 }
1850
1851 static irqreturn_t omap1_dma_irq_handler(int irq, void *dev_id)
1852 {
1853         int ch = ((int) dev_id) - 1;
1854         int handled = 0;
1855
1856         for (;;) {
1857                 int handled_now = 0;
1858
1859                 handled_now += omap1_dma_handle_ch(ch);
1860                 if (enable_1510_mode && dma_chan[ch + 6].saved_csr)
1861                         handled_now += omap1_dma_handle_ch(ch + 6);
1862                 if (!handled_now)
1863                         break;
1864                 handled += handled_now;
1865         }
1866
1867         return handled ? IRQ_HANDLED : IRQ_NONE;
1868 }
1869
1870 #else
1871 #define omap1_dma_irq_handler   NULL
1872 #endif
1873
1874 #ifdef CONFIG_ARCH_OMAP2PLUS
1875
1876 static int omap2_dma_handle_ch(int ch)
1877 {
1878         u32 status = p->dma_read(CSR, ch);
1879
1880         if (!status) {
1881                 if (printk_ratelimit())
1882                         printk(KERN_WARNING "Spurious DMA IRQ for lch %d\n",
1883                                 ch);
1884                 p->dma_write(1 << ch, IRQSTATUS_L0, ch);
1885                 return 0;
1886         }
1887         if (unlikely(dma_chan[ch].dev_id == -1)) {
1888                 if (printk_ratelimit())
1889                         printk(KERN_WARNING "IRQ %04x for non-allocated DMA"
1890                                         "channel %d\n", status, ch);
1891                 return 0;
1892         }
1893         if (unlikely(status & OMAP_DMA_DROP_IRQ))
1894                 printk(KERN_INFO
1895                        "DMA synchronization event drop occurred with device "
1896                        "%d\n", dma_chan[ch].dev_id);
1897         if (unlikely(status & OMAP2_DMA_TRANS_ERR_IRQ)) {
1898                 printk(KERN_INFO "DMA transaction error with device %d\n",
1899                        dma_chan[ch].dev_id);
1900                 if (IS_DMA_ERRATA(DMA_ERRATA_i378)) {
1901                         u32 ccr;
1902
1903                         ccr = p->dma_read(CCR, ch);
1904                         ccr &= ~OMAP_DMA_CCR_EN;
1905                         p->dma_write(ccr, CCR, ch);
1906                         dma_chan[ch].flags &= ~OMAP_DMA_ACTIVE;
1907                 }
1908         }
1909         if (unlikely(status & OMAP2_DMA_SECURE_ERR_IRQ))
1910                 printk(KERN_INFO "DMA secure error with device %d\n",
1911                        dma_chan[ch].dev_id);
1912         if (unlikely(status & OMAP2_DMA_MISALIGNED_ERR_IRQ))
1913                 printk(KERN_INFO "DMA misaligned error with device %d\n",
1914                        dma_chan[ch].dev_id);
1915
1916         p->dma_write(status, CSR, ch);
1917         p->dma_write(1 << ch, IRQSTATUS_L0, ch);
1918         /* read back the register to flush the write */
1919         p->dma_read(IRQSTATUS_L0, ch);
1920
1921         /* If the ch is not chained then chain_id will be -1 */
1922         if (dma_chan[ch].chain_id != -1) {
1923                 int chain_id = dma_chan[ch].chain_id;
1924                 dma_chan[ch].state = DMA_CH_NOTSTARTED;
1925                 if (p->dma_read(CLNK_CTRL, ch) & (1 << 15))
1926                         dma_chan[dma_chan[ch].next_linked_ch].state =
1927                                                         DMA_CH_STARTED;
1928                 if (dma_linked_lch[chain_id].chain_mode ==
1929                                                 OMAP_DMA_DYNAMIC_CHAIN)
1930                         disable_lnk(ch);
1931
1932                 if (!OMAP_DMA_CHAIN_QEMPTY(chain_id))
1933                         OMAP_DMA_CHAIN_INCQHEAD(chain_id);
1934
1935                 status = p->dma_read(CSR, ch);
1936                 p->dma_write(status, CSR, ch);
1937         }
1938
1939         if (likely(dma_chan[ch].callback != NULL))
1940                 dma_chan[ch].callback(ch, status, dma_chan[ch].data);
1941
1942         return 0;
1943 }
1944
1945 /* STATUS register count is from 1-32 while our is 0-31 */
1946 static irqreturn_t omap2_dma_irq_handler(int irq, void *dev_id)
1947 {
1948         u32 val, enable_reg;
1949         int i;
1950
1951         val = p->dma_read(IRQSTATUS_L0, 0);
1952         if (val == 0) {
1953                 if (printk_ratelimit())
1954                         printk(KERN_WARNING "Spurious DMA IRQ\n");
1955                 return IRQ_HANDLED;
1956         }
1957         enable_reg = p->dma_read(IRQENABLE_L0, 0);
1958         val &= enable_reg; /* Dispatch only relevant interrupts */
1959         for (i = 0; i < dma_lch_count && val != 0; i++) {
1960                 if (val & 1)
1961                         omap2_dma_handle_ch(i);
1962                 val >>= 1;
1963         }
1964
1965         return IRQ_HANDLED;
1966 }
1967
1968 static struct irqaction omap24xx_dma_irq = {
1969         .name = "DMA",
1970         .handler = omap2_dma_irq_handler,
1971         .flags = IRQF_DISABLED
1972 };
1973
1974 #else
1975 static struct irqaction omap24xx_dma_irq;
1976 #endif
1977
1978 /*----------------------------------------------------------------------------*/
1979
1980 void omap_dma_global_context_save(void)
1981 {
1982         omap_dma_global_context.dma_irqenable_l0 =
1983                 p->dma_read(IRQENABLE_L0, 0);
1984         omap_dma_global_context.dma_ocp_sysconfig =
1985                 p->dma_read(OCP_SYSCONFIG, 0);
1986         omap_dma_global_context.dma_gcr = p->dma_read(GCR, 0);
1987 }
1988
1989 void omap_dma_global_context_restore(void)
1990 {
1991         int ch;
1992
1993         p->dma_write(omap_dma_global_context.dma_gcr, GCR, 0);
1994         p->dma_write(omap_dma_global_context.dma_ocp_sysconfig,
1995                 OCP_SYSCONFIG, 0);
1996         p->dma_write(omap_dma_global_context.dma_irqenable_l0,
1997                 IRQENABLE_L0, 0);
1998
1999         if (IS_DMA_ERRATA(DMA_ROMCODE_BUG))
2000                 p->dma_write(0x3 , IRQSTATUS_L0, 0);
2001
2002         for (ch = 0; ch < dma_chan_count; ch++)
2003                 if (dma_chan[ch].dev_id != -1)
2004                         omap_clear_dma(ch);
2005 }
2006
2007 static int __devinit omap_system_dma_probe(struct platform_device *pdev)
2008 {
2009         int ch, ret = 0;
2010         int dma_irq;
2011         char irq_name[4];
2012         int irq_rel;
2013
2014         p = pdev->dev.platform_data;
2015         if (!p) {
2016                 dev_err(&pdev->dev, "%s: System DMA initialized without"
2017                         "platform data\n", __func__);
2018                 return -EINVAL;
2019         }
2020
2021         d                       = p->dma_attr;
2022         errata                  = p->errata;
2023
2024         if ((d->dev_caps & RESERVE_CHANNEL) && omap_dma_reserve_channels
2025                         && (omap_dma_reserve_channels <= dma_lch_count))
2026                 d->lch_count    = omap_dma_reserve_channels;
2027
2028         dma_lch_count           = d->lch_count;
2029         dma_chan_count          = dma_lch_count;
2030         dma_chan                = d->chan;
2031         enable_1510_mode        = d->dev_caps & ENABLE_1510_MODE;
2032
2033         if (cpu_class_is_omap2()) {
2034                 dma_linked_lch = kzalloc(sizeof(struct dma_link_info) *
2035                                                 dma_lch_count, GFP_KERNEL);
2036                 if (!dma_linked_lch) {
2037                         ret = -ENOMEM;
2038                         goto exit_dma_lch_fail;
2039                 }
2040         }
2041
2042         spin_lock_init(&dma_chan_lock);
2043         for (ch = 0; ch < dma_chan_count; ch++) {
2044                 omap_clear_dma(ch);
2045                 if (cpu_class_is_omap2())
2046                         omap2_disable_irq_lch(ch);
2047
2048                 dma_chan[ch].dev_id = -1;
2049                 dma_chan[ch].next_lch = -1;
2050
2051                 if (ch >= 6 && enable_1510_mode)
2052                         continue;
2053
2054                 if (cpu_class_is_omap1()) {
2055                         /*
2056                          * request_irq() doesn't like dev_id (ie. ch) being
2057                          * zero, so we have to kludge around this.
2058                          */
2059                         sprintf(&irq_name[0], "%d", ch);
2060                         dma_irq = platform_get_irq_byname(pdev, irq_name);
2061
2062                         if (dma_irq < 0) {
2063                                 ret = dma_irq;
2064                                 goto exit_dma_irq_fail;
2065                         }
2066
2067                         /* INT_DMA_LCD is handled in lcd_dma.c */
2068                         if (dma_irq == INT_DMA_LCD)
2069                                 continue;
2070
2071                         ret = request_irq(dma_irq,
2072                                         omap1_dma_irq_handler, 0, "DMA",
2073                                         (void *) (ch + 1));
2074                         if (ret != 0)
2075                                 goto exit_dma_irq_fail;
2076                 }
2077         }
2078
2079         if (cpu_class_is_omap2() && !cpu_is_omap242x())
2080                 omap_dma_set_global_params(DMA_DEFAULT_ARB_RATE,
2081                                 DMA_DEFAULT_FIFO_DEPTH, 0);
2082
2083         if (cpu_class_is_omap2()) {
2084                 strcpy(irq_name, "0");
2085                 dma_irq = platform_get_irq_byname(pdev, irq_name);
2086                 if (dma_irq < 0) {
2087                         dev_err(&pdev->dev, "failed: request IRQ %d", dma_irq);
2088                         goto exit_dma_lch_fail;
2089                 }
2090                 ret = setup_irq(dma_irq, &omap24xx_dma_irq);
2091                 if (ret) {
2092                         dev_err(&pdev->dev, "set_up failed for IRQ %d"
2093                                 "for DMA (error %d)\n", dma_irq, ret);
2094                         goto exit_dma_lch_fail;
2095                 }
2096         }
2097
2098         /* reserve dma channels 0 and 1 in high security devices */
2099         if (cpu_is_omap34xx() &&
2100                 (omap_type() != OMAP2_DEVICE_TYPE_GP)) {
2101                 printk(KERN_INFO "Reserving DMA channels 0 and 1 for "
2102                                 "HS ROM code\n");
2103                 dma_chan[0].dev_id = 0;
2104                 dma_chan[1].dev_id = 1;
2105         }
2106         p->show_dma_caps();
2107         return 0;
2108
2109 exit_dma_irq_fail:
2110         dev_err(&pdev->dev, "unable to request IRQ %d"
2111                         "for DMA (error %d)\n", dma_irq, ret);
2112         for (irq_rel = 0; irq_rel < ch; irq_rel++) {
2113                 dma_irq = platform_get_irq(pdev, irq_rel);
2114                 free_irq(dma_irq, (void *)(irq_rel + 1));
2115         }
2116
2117 exit_dma_lch_fail:
2118         kfree(p);
2119         kfree(d);
2120         kfree(dma_chan);
2121         return ret;
2122 }
2123
2124 static int __devexit omap_system_dma_remove(struct platform_device *pdev)
2125 {
2126         int dma_irq;
2127
2128         if (cpu_class_is_omap2()) {
2129                 char irq_name[4];
2130                 strcpy(irq_name, "0");
2131                 dma_irq = platform_get_irq_byname(pdev, irq_name);
2132                 remove_irq(dma_irq, &omap24xx_dma_irq);
2133         } else {
2134                 int irq_rel = 0;
2135                 for ( ; irq_rel < dma_chan_count; irq_rel++) {
2136                         dma_irq = platform_get_irq(pdev, irq_rel);
2137                         free_irq(dma_irq, (void *)(irq_rel + 1));
2138                 }
2139         }
2140         kfree(p);
2141         kfree(d);
2142         kfree(dma_chan);
2143         return 0;
2144 }
2145
2146 static struct platform_driver omap_system_dma_driver = {
2147         .probe          = omap_system_dma_probe,
2148         .remove         = __devexit_p(omap_system_dma_remove),
2149         .driver         = {
2150                 .name   = "omap_dma_system"
2151         },
2152 };
2153
2154 static int __init omap_system_dma_init(void)
2155 {
2156         return platform_driver_register(&omap_system_dma_driver);
2157 }
2158 arch_initcall(omap_system_dma_init);
2159
2160 static void __exit omap_system_dma_exit(void)
2161 {
2162         platform_driver_unregister(&omap_system_dma_driver);
2163 }
2164
2165 MODULE_DESCRIPTION("OMAP SYSTEM DMA DRIVER");
2166 MODULE_LICENSE("GPL");
2167 MODULE_ALIAS("platform:" DRIVER_NAME);
2168 MODULE_AUTHOR("Texas Instruments Inc");
2169
2170 /*
2171  * Reserve the omap SDMA channels using cmdline bootarg
2172  * "omap_dma_reserve_ch=". The valid range is 1 to 32
2173  */
2174 static int __init omap_dma_cmdline_reserve_ch(char *str)
2175 {
2176         if (get_option(&str, &omap_dma_reserve_channels) != 1)
2177                 omap_dma_reserve_channels = 0;
2178         return 1;
2179 }
2180
2181 __setup("omap_dma_reserve_ch=", omap_dma_cmdline_reserve_ch);
2182
2183