2 * linux/arch/arm/plat-omap/dma.c
4 * Copyright (C) 2003 - 2008 Nokia Corporation
5 * Author: Juha Yrjölä <juha.yrjola@nokia.com>
6 * DMA channel linking for 1610 by Samuel Ortiz <samuel.ortiz@nokia.com>
7 * Graphics DMA and LCD DMA graphics tranformations
8 * by Imre Deak <imre.deak@nokia.com>
9 * OMAP2/3 support Copyright (C) 2004-2007 Texas Instruments, Inc.
10 * Merged to support both OMAP1 and OMAP2 by Tony Lindgren <tony@atomide.com>
11 * Some functions based on earlier dma-omap.c Copyright (C) 2001 RidgeRun, Inc.
13 * Copyright (C) 2009 Texas Instruments
14 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
16 * Support functions for the OMAP internal DMA channels.
18 * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
19 * Converted DMA library into DMA platform driver.
20 * - G, Manjunath Kondaiah <manjugk@ti.com>
22 * This program is free software; you can redistribute it and/or modify
23 * it under the terms of the GNU General Public License version 2 as
24 * published by the Free Software Foundation.
28 #include <linux/module.h>
29 #include <linux/init.h>
30 #include <linux/sched.h>
31 #include <linux/spinlock.h>
32 #include <linux/errno.h>
33 #include <linux/interrupt.h>
34 #include <linux/irq.h>
36 #include <linux/slab.h>
37 #include <linux/delay.h>
39 #include <linux/omap-dma.h>
42 * MAX_LOGICAL_DMA_CH_COUNT: the maximum number of logical DMA
43 * channels that an instance of the SDMA IP block can support. Used
44 * to size arrays. (The actual maximum on a particular SoC may be less
45 * than this -- for example, OMAP1 SDMA instances only support 17 logical
48 #define MAX_LOGICAL_DMA_CH_COUNT 32
52 #ifndef CONFIG_ARCH_OMAP1
53 enum { DMA_CH_ALLOC_DONE, DMA_CH_PARAMS_SET_DONE, DMA_CH_STARTED,
54 DMA_CH_QUEUED, DMA_CH_NOTSTARTED, DMA_CH_PAUSED, DMA_CH_LINK_ENABLED
57 enum { DMA_CHAIN_STARTED, DMA_CHAIN_NOTSTARTED };
60 #define OMAP_DMA_ACTIVE 0x01
61 #define OMAP2_DMA_CSR_CLEAR_MASK 0xffffffff
63 #define OMAP_FUNC_MUX_ARM_BASE (0xfffe1000 + 0xec)
65 static struct omap_system_dma_plat_info *p;
66 static struct omap_dma_dev_attr *d;
67 static void omap_clear_dma(int lch);
68 static int omap_dma_set_prio_lch(int lch, unsigned char read_prio,
69 unsigned char write_prio);
70 static int enable_1510_mode;
73 static struct omap_dma_global_context_registers {
76 u32 dma_ocp_sysconfig;
78 } omap_dma_global_context;
80 struct dma_link_info {
82 int no_of_lchs_linked;
93 static struct dma_link_info *dma_linked_lch;
95 #ifndef CONFIG_ARCH_OMAP1
97 /* Chain handling macros */
98 #define OMAP_DMA_CHAIN_QINIT(chain_id) \
100 dma_linked_lch[chain_id].q_head = \
101 dma_linked_lch[chain_id].q_tail = \
102 dma_linked_lch[chain_id].q_count = 0; \
104 #define OMAP_DMA_CHAIN_QFULL(chain_id) \
105 (dma_linked_lch[chain_id].no_of_lchs_linked == \
106 dma_linked_lch[chain_id].q_count)
107 #define OMAP_DMA_CHAIN_QLAST(chain_id) \
109 ((dma_linked_lch[chain_id].no_of_lchs_linked-1) == \
110 dma_linked_lch[chain_id].q_count) \
112 #define OMAP_DMA_CHAIN_QEMPTY(chain_id) \
113 (0 == dma_linked_lch[chain_id].q_count)
114 #define __OMAP_DMA_CHAIN_INCQ(end) \
115 ((end) = ((end)+1) % dma_linked_lch[chain_id].no_of_lchs_linked)
116 #define OMAP_DMA_CHAIN_INCQHEAD(chain_id) \
118 __OMAP_DMA_CHAIN_INCQ(dma_linked_lch[chain_id].q_head); \
119 dma_linked_lch[chain_id].q_count--; \
122 #define OMAP_DMA_CHAIN_INCQTAIL(chain_id) \
124 __OMAP_DMA_CHAIN_INCQ(dma_linked_lch[chain_id].q_tail); \
125 dma_linked_lch[chain_id].q_count++; \
129 static int dma_lch_count;
130 static int dma_chan_count;
131 static int omap_dma_reserve_channels;
133 static spinlock_t dma_chan_lock;
134 static struct omap_dma_lch *dma_chan;
136 static inline void disable_lnk(int lch);
137 static void omap_disable_channel_irq(int lch);
138 static inline void omap_enable_channel_irq(int lch);
140 #define REVISIT_24XX() printk(KERN_ERR "FIXME: no %s on 24xx\n", \
143 #ifdef CONFIG_ARCH_OMAP15XX
144 /* Returns 1 if the DMA module is in OMAP1510-compatible mode, 0 otherwise */
145 static int omap_dma_in_1510_mode(void)
147 return enable_1510_mode;
150 #define omap_dma_in_1510_mode() 0
153 #ifdef CONFIG_ARCH_OMAP1
154 static inline int get_gdma_dev(int req)
156 u32 reg = OMAP_FUNC_MUX_ARM_BASE + ((req - 1) / 5) * 4;
157 int shift = ((req - 1) % 5) * 6;
159 return ((omap_readl(reg) >> shift) & 0x3f) + 1;
162 static inline void set_gdma_dev(int req, int dev)
164 u32 reg = OMAP_FUNC_MUX_ARM_BASE + ((req - 1) / 5) * 4;
165 int shift = ((req - 1) % 5) * 6;
169 l &= ~(0x3f << shift);
170 l |= (dev - 1) << shift;
174 #define set_gdma_dev(req, dev) do {} while (0)
175 #define omap_readl(reg) 0
176 #define omap_writel(val, reg) do {} while (0)
179 #ifdef CONFIG_ARCH_OMAP1
180 void omap_set_dma_priority(int lch, int dst_port, int priority)
187 case OMAP_DMA_PORT_OCP_T1: /* FFFECC00 */
188 reg = OMAP_TC_OCPT1_PRIOR;
190 case OMAP_DMA_PORT_OCP_T2: /* FFFECCD0 */
191 reg = OMAP_TC_OCPT2_PRIOR;
193 case OMAP_DMA_PORT_EMIFF: /* FFFECC08 */
194 reg = OMAP_TC_EMIFF_PRIOR;
196 case OMAP_DMA_PORT_EMIFS: /* FFFECC04 */
197 reg = OMAP_TC_EMIFS_PRIOR;
205 l |= (priority & 0xf) << 8;
211 #ifdef CONFIG_ARCH_OMAP2PLUS
212 void omap_set_dma_priority(int lch, int dst_port, int priority)
216 ccr = p->dma_read(CCR, lch);
221 p->dma_write(ccr, CCR, lch);
224 EXPORT_SYMBOL(omap_set_dma_priority);
226 void omap_set_dma_transfer_params(int lch, int data_type, int elem_count,
227 int frame_count, int sync_mode,
228 int dma_trigger, int src_or_dst_synch)
232 l = p->dma_read(CSDP, lch);
235 p->dma_write(l, CSDP, lch);
240 ccr = p->dma_read(CCR, lch);
242 if (sync_mode == OMAP_DMA_SYNC_FRAME)
244 p->dma_write(ccr, CCR, lch);
246 ccr = p->dma_read(CCR2, lch);
248 if (sync_mode == OMAP_DMA_SYNC_BLOCK)
250 p->dma_write(ccr, CCR2, lch);
253 if (dma_omap2plus() && dma_trigger) {
256 val = p->dma_read(CCR, lch);
258 /* DMA_SYNCHRO_CONTROL_UPPER depends on the channel number */
259 val &= ~((1 << 23) | (3 << 19) | 0x1f);
260 val |= (dma_trigger & ~0x1f) << 14;
261 val |= dma_trigger & 0x1f;
263 if (sync_mode & OMAP_DMA_SYNC_FRAME)
268 if (sync_mode & OMAP_DMA_SYNC_BLOCK)
273 if (src_or_dst_synch == OMAP_DMA_DST_SYNC_PREFETCH) {
274 val &= ~(1 << 24); /* dest synch */
275 val |= (1 << 23); /* Prefetch */
276 } else if (src_or_dst_synch) {
277 val |= 1 << 24; /* source synch */
279 val &= ~(1 << 24); /* dest synch */
281 p->dma_write(val, CCR, lch);
284 p->dma_write(elem_count, CEN, lch);
285 p->dma_write(frame_count, CFN, lch);
287 EXPORT_SYMBOL(omap_set_dma_transfer_params);
289 void omap_set_dma_write_mode(int lch, enum omap_dma_write_mode mode)
291 if (dma_omap2plus()) {
294 csdp = p->dma_read(CSDP, lch);
295 csdp &= ~(0x3 << 16);
296 csdp |= (mode << 16);
297 p->dma_write(csdp, CSDP, lch);
300 EXPORT_SYMBOL(omap_set_dma_write_mode);
302 void omap_set_dma_channel_mode(int lch, enum omap_dma_channel_mode mode)
304 if (dma_omap1() && !dma_omap15xx()) {
307 l = p->dma_read(LCH_CTRL, lch);
310 p->dma_write(l, LCH_CTRL, lch);
313 EXPORT_SYMBOL(omap_set_dma_channel_mode);
315 /* Note that src_port is only for omap1 */
316 void omap_set_dma_src_params(int lch, int src_port, int src_amode,
317 unsigned long src_start,
318 int src_ei, int src_fi)
325 w = p->dma_read(CSDP, lch);
328 p->dma_write(w, CSDP, lch);
331 l = p->dma_read(CCR, lch);
333 l |= src_amode << 12;
334 p->dma_write(l, CCR, lch);
336 p->dma_write(src_start, CSSA, lch);
338 p->dma_write(src_ei, CSEI, lch);
339 p->dma_write(src_fi, CSFI, lch);
341 EXPORT_SYMBOL(omap_set_dma_src_params);
343 void omap_set_dma_params(int lch, struct omap_dma_channel_params *params)
345 omap_set_dma_transfer_params(lch, params->data_type,
346 params->elem_count, params->frame_count,
347 params->sync_mode, params->trigger,
348 params->src_or_dst_synch);
349 omap_set_dma_src_params(lch, params->src_port,
350 params->src_amode, params->src_start,
351 params->src_ei, params->src_fi);
353 omap_set_dma_dest_params(lch, params->dst_port,
354 params->dst_amode, params->dst_start,
355 params->dst_ei, params->dst_fi);
356 if (params->read_prio || params->write_prio)
357 omap_dma_set_prio_lch(lch, params->read_prio,
360 EXPORT_SYMBOL(omap_set_dma_params);
362 void omap_set_dma_src_data_pack(int lch, int enable)
366 l = p->dma_read(CSDP, lch);
370 p->dma_write(l, CSDP, lch);
372 EXPORT_SYMBOL(omap_set_dma_src_data_pack);
374 void omap_set_dma_src_burst_mode(int lch, enum omap_dma_burst_mode burst_mode)
376 unsigned int burst = 0;
379 l = p->dma_read(CSDP, lch);
382 switch (burst_mode) {
383 case OMAP_DMA_DATA_BURST_DIS:
385 case OMAP_DMA_DATA_BURST_4:
391 case OMAP_DMA_DATA_BURST_8:
392 if (dma_omap2plus()) {
397 * not supported by current hardware on OMAP1
401 case OMAP_DMA_DATA_BURST_16:
402 if (dma_omap2plus()) {
407 * OMAP1 don't support burst 16
415 p->dma_write(l, CSDP, lch);
417 EXPORT_SYMBOL(omap_set_dma_src_burst_mode);
419 /* Note that dest_port is only for OMAP1 */
420 void omap_set_dma_dest_params(int lch, int dest_port, int dest_amode,
421 unsigned long dest_start,
422 int dst_ei, int dst_fi)
427 l = p->dma_read(CSDP, lch);
430 p->dma_write(l, CSDP, lch);
433 l = p->dma_read(CCR, lch);
435 l |= dest_amode << 14;
436 p->dma_write(l, CCR, lch);
438 p->dma_write(dest_start, CDSA, lch);
440 p->dma_write(dst_ei, CDEI, lch);
441 p->dma_write(dst_fi, CDFI, lch);
443 EXPORT_SYMBOL(omap_set_dma_dest_params);
445 void omap_set_dma_dest_data_pack(int lch, int enable)
449 l = p->dma_read(CSDP, lch);
453 p->dma_write(l, CSDP, lch);
455 EXPORT_SYMBOL(omap_set_dma_dest_data_pack);
457 void omap_set_dma_dest_burst_mode(int lch, enum omap_dma_burst_mode burst_mode)
459 unsigned int burst = 0;
462 l = p->dma_read(CSDP, lch);
465 switch (burst_mode) {
466 case OMAP_DMA_DATA_BURST_DIS:
468 case OMAP_DMA_DATA_BURST_4:
474 case OMAP_DMA_DATA_BURST_8:
480 case OMAP_DMA_DATA_BURST_16:
481 if (dma_omap2plus()) {
486 * OMAP1 don't support burst 16
490 printk(KERN_ERR "Invalid DMA burst mode\n");
495 p->dma_write(l, CSDP, lch);
497 EXPORT_SYMBOL(omap_set_dma_dest_burst_mode);
499 static inline void omap_enable_channel_irq(int lch)
503 p->dma_read(CSR, lch);
505 p->dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR, lch);
507 /* Enable some nice interrupts. */
508 p->dma_write(dma_chan[lch].enabled_irqs, CICR, lch);
511 static inline void omap_disable_channel_irq(int lch)
513 /* disable channel interrupts */
514 p->dma_write(0, CICR, lch);
517 p->dma_read(CSR, lch);
519 p->dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR, lch);
522 void omap_enable_dma_irq(int lch, u16 bits)
524 dma_chan[lch].enabled_irqs |= bits;
526 EXPORT_SYMBOL(omap_enable_dma_irq);
528 void omap_disable_dma_irq(int lch, u16 bits)
530 dma_chan[lch].enabled_irqs &= ~bits;
532 EXPORT_SYMBOL(omap_disable_dma_irq);
534 static inline void enable_lnk(int lch)
538 l = p->dma_read(CLNK_CTRL, lch);
543 /* Set the ENABLE_LNK bits */
544 if (dma_chan[lch].next_lch != -1)
545 l = dma_chan[lch].next_lch | (1 << 15);
547 #ifndef CONFIG_ARCH_OMAP1
549 if (dma_chan[lch].next_linked_ch != -1)
550 l = dma_chan[lch].next_linked_ch | (1 << 15);
553 p->dma_write(l, CLNK_CTRL, lch);
556 static inline void disable_lnk(int lch)
560 l = p->dma_read(CLNK_CTRL, lch);
562 /* Disable interrupts */
563 omap_disable_channel_irq(lch);
566 /* Set the STOP_LNK bit */
570 if (dma_omap2plus()) {
571 /* Clear the ENABLE_LNK bit */
575 p->dma_write(l, CLNK_CTRL, lch);
576 dma_chan[lch].flags &= ~OMAP_DMA_ACTIVE;
579 static inline void omap2_enable_irq_lch(int lch)
587 spin_lock_irqsave(&dma_chan_lock, flags);
588 /* clear IRQ STATUS */
589 p->dma_write(1 << lch, IRQSTATUS_L0, lch);
590 /* Enable interrupt */
591 val = p->dma_read(IRQENABLE_L0, lch);
593 p->dma_write(val, IRQENABLE_L0, lch);
594 spin_unlock_irqrestore(&dma_chan_lock, flags);
597 static inline void omap2_disable_irq_lch(int lch)
605 spin_lock_irqsave(&dma_chan_lock, flags);
606 /* Disable interrupt */
607 val = p->dma_read(IRQENABLE_L0, lch);
609 p->dma_write(val, IRQENABLE_L0, lch);
610 /* clear IRQ STATUS */
611 p->dma_write(1 << lch, IRQSTATUS_L0, lch);
612 spin_unlock_irqrestore(&dma_chan_lock, flags);
615 int omap_request_dma(int dev_id, const char *dev_name,
616 void (*callback)(int lch, u16 ch_status, void *data),
617 void *data, int *dma_ch_out)
619 int ch, free_ch = -1;
621 struct omap_dma_lch *chan;
623 WARN(strcmp(dev_name, "DMA engine"), "Using deprecated platform DMA API - please update to DMA engine");
625 spin_lock_irqsave(&dma_chan_lock, flags);
626 for (ch = 0; ch < dma_chan_count; ch++) {
627 if (free_ch == -1 && dma_chan[ch].dev_id == -1) {
629 /* Exit after first free channel found */
634 spin_unlock_irqrestore(&dma_chan_lock, flags);
637 chan = dma_chan + free_ch;
638 chan->dev_id = dev_id;
640 if (p->clear_lch_regs)
641 p->clear_lch_regs(free_ch);
644 omap_clear_dma(free_ch);
646 spin_unlock_irqrestore(&dma_chan_lock, flags);
648 chan->dev_name = dev_name;
649 chan->callback = callback;
653 #ifndef CONFIG_ARCH_OMAP1
654 if (dma_omap2plus()) {
656 chan->next_linked_ch = -1;
660 chan->enabled_irqs = OMAP_DMA_DROP_IRQ | OMAP_DMA_BLOCK_IRQ;
663 chan->enabled_irqs |= OMAP1_DMA_TOUT_IRQ;
664 else if (dma_omap2plus())
665 chan->enabled_irqs |= OMAP2_DMA_MISALIGNED_ERR_IRQ |
666 OMAP2_DMA_TRANS_ERR_IRQ;
668 if (dma_omap16xx()) {
669 /* If the sync device is set, configure it dynamically. */
671 set_gdma_dev(free_ch + 1, dev_id);
672 dev_id = free_ch + 1;
675 * Disable the 1510 compatibility mode and set the sync device
678 p->dma_write(dev_id | (1 << 10), CCR, free_ch);
679 } else if (dma_omap1()) {
680 p->dma_write(dev_id, CCR, free_ch);
683 if (dma_omap2plus()) {
684 omap_enable_channel_irq(free_ch);
685 omap2_enable_irq_lch(free_ch);
688 *dma_ch_out = free_ch;
692 EXPORT_SYMBOL(omap_request_dma);
694 void omap_free_dma(int lch)
698 if (dma_chan[lch].dev_id == -1) {
699 pr_err("omap_dma: trying to free unallocated DMA channel %d\n",
704 /* Disable interrupt for logical channel */
706 omap2_disable_irq_lch(lch);
708 /* Disable all DMA interrupts for the channel. */
709 omap_disable_channel_irq(lch);
711 /* Make sure the DMA transfer is stopped. */
712 p->dma_write(0, CCR, lch);
714 /* Clear registers */
718 spin_lock_irqsave(&dma_chan_lock, flags);
719 dma_chan[lch].dev_id = -1;
720 dma_chan[lch].next_lch = -1;
721 dma_chan[lch].callback = NULL;
722 spin_unlock_irqrestore(&dma_chan_lock, flags);
724 EXPORT_SYMBOL(omap_free_dma);
727 * @brief omap_dma_set_global_params : Set global priority settings for dma
730 * @param max_fifo_depth
731 * @param tparams - Number of threads to reserve : DMA_THREAD_RESERVE_NORM
732 * DMA_THREAD_RESERVE_ONET
733 * DMA_THREAD_RESERVE_TWOT
734 * DMA_THREAD_RESERVE_THREET
737 omap_dma_set_global_params(int arb_rate, int max_fifo_depth, int tparams)
742 printk(KERN_ERR "FIXME: no %s on 15xx/16xx\n", __func__);
746 if (max_fifo_depth == 0)
751 reg = 0xff & max_fifo_depth;
752 reg |= (0x3 & tparams) << 12;
753 reg |= (arb_rate & 0xff) << 16;
755 p->dma_write(reg, GCR, 0);
757 EXPORT_SYMBOL(omap_dma_set_global_params);
760 * @brief omap_dma_set_prio_lch : Set channel wise priority settings
763 * @param read_prio - Read priority
764 * @param write_prio - Write priority
765 * Both of the above can be set with one of the following values :
766 * DMA_CH_PRIO_HIGH/DMA_CH_PRIO_LOW
769 omap_dma_set_prio_lch(int lch, unsigned char read_prio,
770 unsigned char write_prio)
774 if (unlikely((lch < 0 || lch >= dma_lch_count))) {
775 printk(KERN_ERR "Invalid channel id\n");
778 l = p->dma_read(CCR, lch);
779 l &= ~((1 << 6) | (1 << 26));
780 if (d->dev_caps & IS_RW_PRIORITY)
781 l |= ((read_prio & 0x1) << 6) | ((write_prio & 0x1) << 26);
783 l |= ((read_prio & 0x1) << 6);
785 p->dma_write(l, CCR, lch);
792 * Clears any DMA state so the DMA engine is ready to restart with new buffers
793 * through omap_start_dma(). Any buffers in flight are discarded.
795 static void omap_clear_dma(int lch)
799 local_irq_save(flags);
801 local_irq_restore(flags);
804 void omap_start_dma(int lch)
809 * The CPC/CDAC register needs to be initialized to zero
810 * before starting dma transfer.
813 p->dma_write(0, CPC, lch);
815 p->dma_write(0, CDAC, lch);
817 if (!omap_dma_in_1510_mode() && dma_chan[lch].next_lch != -1) {
818 int next_lch, cur_lch;
819 char dma_chan_link_map[MAX_LOGICAL_DMA_CH_COUNT];
821 /* Set the link register of the first channel */
824 memset(dma_chan_link_map, 0, sizeof(dma_chan_link_map));
825 dma_chan_link_map[lch] = 1;
827 cur_lch = dma_chan[lch].next_lch;
829 next_lch = dma_chan[cur_lch].next_lch;
831 /* The loop case: we've been here already */
832 if (dma_chan_link_map[cur_lch])
834 /* Mark the current channel */
835 dma_chan_link_map[cur_lch] = 1;
838 omap_enable_channel_irq(cur_lch);
841 } while (next_lch != -1);
842 } else if (IS_DMA_ERRATA(DMA_ERRATA_PARALLEL_CHANNELS))
843 p->dma_write(lch, CLNK_CTRL, lch);
845 omap_enable_channel_irq(lch);
847 l = p->dma_read(CCR, lch);
849 if (IS_DMA_ERRATA(DMA_ERRATA_IFRAME_BUFFERING))
850 l |= OMAP_DMA_CCR_BUFFERING_DISABLE;
851 l |= OMAP_DMA_CCR_EN;
854 * As dma_write() uses IO accessors which are weakly ordered, there
855 * is no guarantee that data in coherent DMA memory will be visible
856 * to the DMA device. Add a memory barrier here to ensure that any
857 * such data is visible prior to enabling DMA.
860 p->dma_write(l, CCR, lch);
862 dma_chan[lch].flags |= OMAP_DMA_ACTIVE;
864 EXPORT_SYMBOL(omap_start_dma);
866 void omap_stop_dma(int lch)
870 /* Disable all interrupts on the channel */
871 omap_disable_channel_irq(lch);
873 l = p->dma_read(CCR, lch);
874 if (IS_DMA_ERRATA(DMA_ERRATA_i541) &&
875 (l & OMAP_DMA_CCR_SEL_SRC_DST_SYNC)) {
879 /* Configure No-Standby */
880 l = p->dma_read(OCP_SYSCONFIG, lch);
882 l &= ~DMA_SYSCONFIG_MIDLEMODE_MASK;
883 l |= DMA_SYSCONFIG_MIDLEMODE(DMA_IDLEMODE_NO_IDLE);
884 p->dma_write(l , OCP_SYSCONFIG, 0);
886 l = p->dma_read(CCR, lch);
887 l &= ~OMAP_DMA_CCR_EN;
888 p->dma_write(l, CCR, lch);
890 /* Wait for sDMA FIFO drain */
891 l = p->dma_read(CCR, lch);
892 while (i < 100 && (l & (OMAP_DMA_CCR_RD_ACTIVE |
893 OMAP_DMA_CCR_WR_ACTIVE))) {
896 l = p->dma_read(CCR, lch);
899 pr_err("DMA drain did not complete on lch %d\n", lch);
900 /* Restore OCP_SYSCONFIG */
901 p->dma_write(sys_cf, OCP_SYSCONFIG, lch);
903 l &= ~OMAP_DMA_CCR_EN;
904 p->dma_write(l, CCR, lch);
908 * Ensure that data transferred by DMA is visible to any access
909 * after DMA has been disabled. This is important for coherent
914 if (!omap_dma_in_1510_mode() && dma_chan[lch].next_lch != -1) {
915 int next_lch, cur_lch = lch;
916 char dma_chan_link_map[MAX_LOGICAL_DMA_CH_COUNT];
918 memset(dma_chan_link_map, 0, sizeof(dma_chan_link_map));
920 /* The loop case: we've been here already */
921 if (dma_chan_link_map[cur_lch])
923 /* Mark the current channel */
924 dma_chan_link_map[cur_lch] = 1;
926 disable_lnk(cur_lch);
928 next_lch = dma_chan[cur_lch].next_lch;
930 } while (next_lch != -1);
933 dma_chan[lch].flags &= ~OMAP_DMA_ACTIVE;
935 EXPORT_SYMBOL(omap_stop_dma);
938 * Allows changing the DMA callback function or data. This may be needed if
939 * the driver shares a single DMA channel for multiple dma triggers.
941 int omap_set_dma_callback(int lch,
942 void (*callback)(int lch, u16 ch_status, void *data),
950 spin_lock_irqsave(&dma_chan_lock, flags);
951 if (dma_chan[lch].dev_id == -1) {
952 printk(KERN_ERR "DMA callback for not set for free channel\n");
953 spin_unlock_irqrestore(&dma_chan_lock, flags);
956 dma_chan[lch].callback = callback;
957 dma_chan[lch].data = data;
958 spin_unlock_irqrestore(&dma_chan_lock, flags);
962 EXPORT_SYMBOL(omap_set_dma_callback);
965 * Returns current physical source address for the given DMA channel.
966 * If the channel is running the caller must disable interrupts prior calling
967 * this function and process the returned value before re-enabling interrupt to
968 * prevent races with the interrupt handler. Note that in continuous mode there
969 * is a chance for CSSA_L register overflow between the two reads resulting
970 * in incorrect return value.
972 dma_addr_t omap_get_dma_src_pos(int lch)
974 dma_addr_t offset = 0;
977 offset = p->dma_read(CPC, lch);
979 offset = p->dma_read(CSAC, lch);
981 if (IS_DMA_ERRATA(DMA_ERRATA_3_3) && offset == 0)
982 offset = p->dma_read(CSAC, lch);
984 if (!dma_omap15xx()) {
986 * CDAC == 0 indicates that the DMA transfer on the channel has
987 * not been started (no data has been transferred so far).
988 * Return the programmed source start address in this case.
990 if (likely(p->dma_read(CDAC, lch)))
991 offset = p->dma_read(CSAC, lch);
993 offset = p->dma_read(CSSA, lch);
997 offset |= (p->dma_read(CSSA, lch) & 0xFFFF0000);
1001 EXPORT_SYMBOL(omap_get_dma_src_pos);
1004 * Returns current physical destination address for the given DMA channel.
1005 * If the channel is running the caller must disable interrupts prior calling
1006 * this function and process the returned value before re-enabling interrupt to
1007 * prevent races with the interrupt handler. Note that in continuous mode there
1008 * is a chance for CDSA_L register overflow between the two reads resulting
1009 * in incorrect return value.
1011 dma_addr_t omap_get_dma_dst_pos(int lch)
1013 dma_addr_t offset = 0;
1016 offset = p->dma_read(CPC, lch);
1018 offset = p->dma_read(CDAC, lch);
1021 * omap 3.2/3.3 erratum: sometimes 0 is returned if CSAC/CDAC is
1022 * read before the DMA controller finished disabling the channel.
1024 if (!dma_omap15xx() && offset == 0) {
1025 offset = p->dma_read(CDAC, lch);
1027 * CDAC == 0 indicates that the DMA transfer on the channel has
1028 * not been started (no data has been transferred so far).
1029 * Return the programmed destination start address in this case.
1031 if (unlikely(!offset))
1032 offset = p->dma_read(CDSA, lch);
1036 offset |= (p->dma_read(CDSA, lch) & 0xFFFF0000);
1040 EXPORT_SYMBOL(omap_get_dma_dst_pos);
1042 int omap_get_dma_active_status(int lch)
1044 return (p->dma_read(CCR, lch) & OMAP_DMA_CCR_EN) != 0;
1046 EXPORT_SYMBOL(omap_get_dma_active_status);
1048 int omap_dma_running(void)
1053 if (omap_lcd_dma_running())
1056 for (lch = 0; lch < dma_chan_count; lch++)
1057 if (p->dma_read(CCR, lch) & OMAP_DMA_CCR_EN)
1064 * lch_queue DMA will start right after lch_head one is finished.
1065 * For this DMA link to start, you still need to start (see omap_start_dma)
1066 * the first one. That will fire up the entire queue.
1068 void omap_dma_link_lch(int lch_head, int lch_queue)
1070 if (omap_dma_in_1510_mode()) {
1071 if (lch_head == lch_queue) {
1072 p->dma_write(p->dma_read(CCR, lch_head) | (3 << 8),
1076 printk(KERN_ERR "DMA linking is not supported in 1510 mode\n");
1081 if ((dma_chan[lch_head].dev_id == -1) ||
1082 (dma_chan[lch_queue].dev_id == -1)) {
1083 pr_err("omap_dma: trying to link non requested channels\n");
1087 dma_chan[lch_head].next_lch = lch_queue;
1089 EXPORT_SYMBOL(omap_dma_link_lch);
1091 /*----------------------------------------------------------------------------*/
1093 #ifdef CONFIG_ARCH_OMAP1
1095 static int omap1_dma_handle_ch(int ch)
1099 if (enable_1510_mode && ch >= 6) {
1100 csr = dma_chan[ch].saved_csr;
1101 dma_chan[ch].saved_csr = 0;
1103 csr = p->dma_read(CSR, ch);
1104 if (enable_1510_mode && ch <= 2 && (csr >> 7) != 0) {
1105 dma_chan[ch + 6].saved_csr = csr >> 7;
1108 if ((csr & 0x3f) == 0)
1110 if (unlikely(dma_chan[ch].dev_id == -1)) {
1111 pr_warn("Spurious interrupt from DMA channel %d (CSR %04x)\n",
1115 if (unlikely(csr & OMAP1_DMA_TOUT_IRQ))
1116 pr_warn("DMA timeout with device %d\n", dma_chan[ch].dev_id);
1117 if (unlikely(csr & OMAP_DMA_DROP_IRQ))
1118 pr_warn("DMA synchronization event drop occurred with device %d\n",
1119 dma_chan[ch].dev_id);
1120 if (likely(csr & OMAP_DMA_BLOCK_IRQ))
1121 dma_chan[ch].flags &= ~OMAP_DMA_ACTIVE;
1122 if (likely(dma_chan[ch].callback != NULL))
1123 dma_chan[ch].callback(ch, csr, dma_chan[ch].data);
1128 static irqreturn_t omap1_dma_irq_handler(int irq, void *dev_id)
1130 int ch = ((int) dev_id) - 1;
1134 int handled_now = 0;
1136 handled_now += omap1_dma_handle_ch(ch);
1137 if (enable_1510_mode && dma_chan[ch + 6].saved_csr)
1138 handled_now += omap1_dma_handle_ch(ch + 6);
1141 handled += handled_now;
1144 return handled ? IRQ_HANDLED : IRQ_NONE;
1148 #define omap1_dma_irq_handler NULL
1151 #ifdef CONFIG_ARCH_OMAP2PLUS
1153 static int omap2_dma_handle_ch(int ch)
1155 u32 status = p->dma_read(CSR, ch);
1158 if (printk_ratelimit())
1159 pr_warn("Spurious DMA IRQ for lch %d\n", ch);
1160 p->dma_write(1 << ch, IRQSTATUS_L0, ch);
1163 if (unlikely(dma_chan[ch].dev_id == -1)) {
1164 if (printk_ratelimit())
1165 pr_warn("IRQ %04x for non-allocated DMA channel %d\n",
1169 if (unlikely(status & OMAP_DMA_DROP_IRQ))
1170 pr_info("DMA synchronization event drop occurred with device %d\n",
1171 dma_chan[ch].dev_id);
1172 if (unlikely(status & OMAP2_DMA_TRANS_ERR_IRQ)) {
1173 printk(KERN_INFO "DMA transaction error with device %d\n",
1174 dma_chan[ch].dev_id);
1175 if (IS_DMA_ERRATA(DMA_ERRATA_i378)) {
1178 ccr = p->dma_read(CCR, ch);
1179 ccr &= ~OMAP_DMA_CCR_EN;
1180 p->dma_write(ccr, CCR, ch);
1181 dma_chan[ch].flags &= ~OMAP_DMA_ACTIVE;
1184 if (unlikely(status & OMAP2_DMA_SECURE_ERR_IRQ))
1185 printk(KERN_INFO "DMA secure error with device %d\n",
1186 dma_chan[ch].dev_id);
1187 if (unlikely(status & OMAP2_DMA_MISALIGNED_ERR_IRQ))
1188 printk(KERN_INFO "DMA misaligned error with device %d\n",
1189 dma_chan[ch].dev_id);
1191 p->dma_write(status, CSR, ch);
1192 p->dma_write(1 << ch, IRQSTATUS_L0, ch);
1193 /* read back the register to flush the write */
1194 p->dma_read(IRQSTATUS_L0, ch);
1196 /* If the ch is not chained then chain_id will be -1 */
1197 if (dma_chan[ch].chain_id != -1) {
1198 int chain_id = dma_chan[ch].chain_id;
1199 dma_chan[ch].state = DMA_CH_NOTSTARTED;
1200 if (p->dma_read(CLNK_CTRL, ch) & (1 << 15))
1201 dma_chan[dma_chan[ch].next_linked_ch].state =
1203 if (dma_linked_lch[chain_id].chain_mode ==
1204 OMAP_DMA_DYNAMIC_CHAIN)
1207 if (!OMAP_DMA_CHAIN_QEMPTY(chain_id))
1208 OMAP_DMA_CHAIN_INCQHEAD(chain_id);
1210 status = p->dma_read(CSR, ch);
1211 p->dma_write(status, CSR, ch);
1214 if (likely(dma_chan[ch].callback != NULL))
1215 dma_chan[ch].callback(ch, status, dma_chan[ch].data);
1220 /* STATUS register count is from 1-32 while our is 0-31 */
1221 static irqreturn_t omap2_dma_irq_handler(int irq, void *dev_id)
1223 u32 val, enable_reg;
1226 val = p->dma_read(IRQSTATUS_L0, 0);
1228 if (printk_ratelimit())
1229 printk(KERN_WARNING "Spurious DMA IRQ\n");
1232 enable_reg = p->dma_read(IRQENABLE_L0, 0);
1233 val &= enable_reg; /* Dispatch only relevant interrupts */
1234 for (i = 0; i < dma_lch_count && val != 0; i++) {
1236 omap2_dma_handle_ch(i);
1243 static struct irqaction omap24xx_dma_irq = {
1245 .handler = omap2_dma_irq_handler,
1249 static struct irqaction omap24xx_dma_irq;
1252 /*----------------------------------------------------------------------------*/
1255 * Note that we are currently using only IRQENABLE_L0 and L1.
1256 * As the DSP may be using IRQENABLE_L2 and L3, let's not
1257 * touch those for now.
1259 void omap_dma_global_context_save(void)
1261 omap_dma_global_context.dma_irqenable_l0 =
1262 p->dma_read(IRQENABLE_L0, 0);
1263 omap_dma_global_context.dma_irqenable_l1 =
1264 p->dma_read(IRQENABLE_L1, 0);
1265 omap_dma_global_context.dma_ocp_sysconfig =
1266 p->dma_read(OCP_SYSCONFIG, 0);
1267 omap_dma_global_context.dma_gcr = p->dma_read(GCR, 0);
1270 void omap_dma_global_context_restore(void)
1274 p->dma_write(omap_dma_global_context.dma_gcr, GCR, 0);
1275 p->dma_write(omap_dma_global_context.dma_ocp_sysconfig,
1277 p->dma_write(omap_dma_global_context.dma_irqenable_l0,
1279 p->dma_write(omap_dma_global_context.dma_irqenable_l1,
1282 if (IS_DMA_ERRATA(DMA_ROMCODE_BUG))
1283 p->dma_write(0x3 , IRQSTATUS_L0, 0);
1285 for (ch = 0; ch < dma_chan_count; ch++)
1286 if (dma_chan[ch].dev_id != -1)
1290 struct omap_system_dma_plat_info *omap_get_plat_info(void)
1294 EXPORT_SYMBOL_GPL(omap_get_plat_info);
1296 static int omap_system_dma_probe(struct platform_device *pdev)
1303 p = pdev->dev.platform_data;
1306 "%s: System DMA initialized without platform data\n",
1314 if ((d->dev_caps & RESERVE_CHANNEL) && omap_dma_reserve_channels
1315 && (omap_dma_reserve_channels < d->lch_count))
1316 d->lch_count = omap_dma_reserve_channels;
1318 dma_lch_count = d->lch_count;
1319 dma_chan_count = dma_lch_count;
1320 enable_1510_mode = d->dev_caps & ENABLE_1510_MODE;
1322 dma_chan = devm_kcalloc(&pdev->dev, dma_lch_count,
1323 sizeof(struct omap_dma_lch), GFP_KERNEL);
1325 dev_err(&pdev->dev, "%s: kzalloc fail\n", __func__);
1330 if (dma_omap2plus()) {
1331 dma_linked_lch = kzalloc(sizeof(struct dma_link_info) *
1332 dma_lch_count, GFP_KERNEL);
1333 if (!dma_linked_lch) {
1335 goto exit_dma_lch_fail;
1339 spin_lock_init(&dma_chan_lock);
1340 for (ch = 0; ch < dma_chan_count; ch++) {
1342 if (dma_omap2plus())
1343 omap2_disable_irq_lch(ch);
1345 dma_chan[ch].dev_id = -1;
1346 dma_chan[ch].next_lch = -1;
1348 if (ch >= 6 && enable_1510_mode)
1353 * request_irq() doesn't like dev_id (ie. ch) being
1354 * zero, so we have to kludge around this.
1356 sprintf(&irq_name[0], "%d", ch);
1357 dma_irq = platform_get_irq_byname(pdev, irq_name);
1361 goto exit_dma_irq_fail;
1364 /* INT_DMA_LCD is handled in lcd_dma.c */
1365 if (dma_irq == INT_DMA_LCD)
1368 ret = request_irq(dma_irq,
1369 omap1_dma_irq_handler, 0, "DMA",
1372 goto exit_dma_irq_fail;
1376 if (d->dev_caps & IS_RW_PRIORITY)
1377 omap_dma_set_global_params(DMA_DEFAULT_ARB_RATE,
1378 DMA_DEFAULT_FIFO_DEPTH, 0);
1380 if (dma_omap2plus() && !(d->dev_caps & DMA_ENGINE_HANDLE_IRQ)) {
1381 strcpy(irq_name, "0");
1382 dma_irq = platform_get_irq_byname(pdev, irq_name);
1384 dev_err(&pdev->dev, "failed: request IRQ %d", dma_irq);
1386 goto exit_dma_lch_fail;
1388 ret = setup_irq(dma_irq, &omap24xx_dma_irq);
1390 dev_err(&pdev->dev, "set_up failed for IRQ %d for DMA (error %d)\n",
1392 goto exit_dma_lch_fail;
1396 /* reserve dma channels 0 and 1 in high security devices on 34xx */
1397 if (d->dev_caps & HS_CHANNELS_RESERVED) {
1398 pr_info("Reserving DMA channels 0 and 1 for HS ROM code\n");
1399 dma_chan[0].dev_id = 0;
1400 dma_chan[1].dev_id = 1;
1406 dev_err(&pdev->dev, "unable to request IRQ %d for DMA (error %d)\n",
1408 for (irq_rel = 0; irq_rel < ch; irq_rel++) {
1409 dma_irq = platform_get_irq(pdev, irq_rel);
1410 free_irq(dma_irq, (void *)(irq_rel + 1));
1417 static int omap_system_dma_remove(struct platform_device *pdev)
1421 if (dma_omap2plus()) {
1423 strcpy(irq_name, "0");
1424 dma_irq = platform_get_irq_byname(pdev, irq_name);
1426 remove_irq(dma_irq, &omap24xx_dma_irq);
1429 for ( ; irq_rel < dma_chan_count; irq_rel++) {
1430 dma_irq = platform_get_irq(pdev, irq_rel);
1431 free_irq(dma_irq, (void *)(irq_rel + 1));
1437 static struct platform_driver omap_system_dma_driver = {
1438 .probe = omap_system_dma_probe,
1439 .remove = omap_system_dma_remove,
1441 .name = "omap_dma_system"
1445 static int __init omap_system_dma_init(void)
1447 return platform_driver_register(&omap_system_dma_driver);
1449 arch_initcall(omap_system_dma_init);
1451 static void __exit omap_system_dma_exit(void)
1453 platform_driver_unregister(&omap_system_dma_driver);
1456 MODULE_DESCRIPTION("OMAP SYSTEM DMA DRIVER");
1457 MODULE_LICENSE("GPL");
1458 MODULE_ALIAS("platform:" DRIVER_NAME);
1459 MODULE_AUTHOR("Texas Instruments Inc");
1462 * Reserve the omap SDMA channels using cmdline bootarg
1463 * "omap_dma_reserve_ch=". The valid range is 1 to 32
1465 static int __init omap_dma_cmdline_reserve_ch(char *str)
1467 if (get_option(&str, &omap_dma_reserve_channels) != 1)
1468 omap_dma_reserve_channels = 0;
1472 __setup("omap_dma_reserve_ch=", omap_dma_cmdline_reserve_ch);