arch/arm/plat-omap/dma.c

   1 /*
   2  * linux/arch/arm/plat-omap/dma.c
   3  *
   4  * Copyright (C) 2003 - 2008 Nokia Corporation
   5  * Author: Juha Yrjölä <juha.yrjola@nokia.com>
   6  * DMA channel linking for 1610 by Samuel Ortiz <samuel.ortiz@nokia.com>
   7  * Graphics DMA and LCD DMA graphics tranformations
   8  * by Imre Deak <imre.deak@nokia.com>
   9  * OMAP2/3 support Copyright (C) 2004-2007 Texas Instruments, Inc.
  10  * Merged to support both OMAP1 and OMAP2 by Tony Lindgren <tony@atomide.com>
  11  * Some functions based on earlier dma-omap.c Copyright (C) 2001 RidgeRun, Inc.
  12  *
  13  * Copyright (C) 2009 Texas Instruments
  14  * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
  15  *
  16  * Support functions for the OMAP internal DMA channels.
  17  *
  18  * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
  19  * Converted DMA library into DMA platform driver.
  20  *      - G, Manjunath Kondaiah <manjugk@ti.com>
  21  *
  22  * This program is free software; you can redistribute it and/or modify
  23  * it under the terms of the GNU General Public License version 2 as
  24  * published by the Free Software Foundation.
  25  *
  26  */
  27
  28 #include <linux/module.h>
  29 #include <linux/init.h>
  30 #include <linux/sched.h>
  31 #include <linux/spinlock.h>
  32 #include <linux/errno.h>
  33 #include <linux/interrupt.h>
  34 #include <linux/irq.h>
  35 #include <linux/io.h>
  36 #include <linux/slab.h>
  37 #include <linux/delay.h>
  38
  39 #include <linux/omap-dma.h>
  40
  41 /*
  42  * MAX_LOGICAL_DMA_CH_COUNT: the maximum number of logical DMA
  43  * channels that an instance of the SDMA IP block can support.  Used
  44  * to size arrays.  (The actual maximum on a particular SoC may be less
  45  * than this -- for example, OMAP1 SDMA instances only support 17 logical
  46  * DMA channels.)
  47  */
  48 #define MAX_LOGICAL_DMA_CH_COUNT                32
  49
  50 #undef DEBUG
  51
  52 #ifndef CONFIG_ARCH_OMAP1
  53 enum { DMA_CH_ALLOC_DONE, DMA_CH_PARAMS_SET_DONE, DMA_CH_STARTED,
  54         DMA_CH_QUEUED, DMA_CH_NOTSTARTED, DMA_CH_PAUSED, DMA_CH_LINK_ENABLED
  55 };
  56
  57 enum { DMA_CHAIN_STARTED, DMA_CHAIN_NOTSTARTED };
  58 #endif
  59
  60 #define OMAP_DMA_ACTIVE                 0x01
  61 #define OMAP2_DMA_CSR_CLEAR_MASK        0xffffffff
  62
  63 #define OMAP_FUNC_MUX_ARM_BASE          (0xfffe1000 + 0xec)
  64
  65 static struct omap_system_dma_plat_info *p;
  66 static struct omap_dma_dev_attr *d;
  67 static void omap_clear_dma(int lch);
  68 static int omap_dma_set_prio_lch(int lch, unsigned char read_prio,
  69                                  unsigned char write_prio);
  70 static int enable_1510_mode;
  71 static u32 errata;
  72
  73 static struct omap_dma_global_context_registers {
  74         u32 dma_irqenable_l0;
  75         u32 dma_irqenable_l1;
  76         u32 dma_ocp_sysconfig;
  77         u32 dma_gcr;
  78 } omap_dma_global_context;
  79
  80 struct dma_link_info {
  81         int *linked_dmach_q;
  82         int no_of_lchs_linked;
  83
  84         int q_count;
  85         int q_tail;
  86         int q_head;
  87
  88         int chain_state;
  89         int chain_mode;
  90
  91 };
  92
  93 static struct dma_link_info *dma_linked_lch;
  94
  95 #ifndef CONFIG_ARCH_OMAP1
  96
  97 /* Chain handling macros */
  98 #define OMAP_DMA_CHAIN_QINIT(chain_id)                                  \
  99         do {                                                            \
 100                 dma_linked_lch[chain_id].q_head =                       \
 101                 dma_linked_lch[chain_id].q_tail =                       \
 102                 dma_linked_lch[chain_id].q_count = 0;                   \
 103         } while (0)
 104 #define OMAP_DMA_CHAIN_QFULL(chain_id)                                  \
 105                 (dma_linked_lch[chain_id].no_of_lchs_linked ==          \
 106                 dma_linked_lch[chain_id].q_count)
 107 #define OMAP_DMA_CHAIN_QLAST(chain_id)                                  \
 108         do {                                                            \
 109                 ((dma_linked_lch[chain_id].no_of_lchs_linked-1) ==      \
 110                 dma_linked_lch[chain_id].q_count)                       \
 111         } while (0)
 112 #define OMAP_DMA_CHAIN_QEMPTY(chain_id)                                 \
 113                 (0 == dma_linked_lch[chain_id].q_count)
 114 #define __OMAP_DMA_CHAIN_INCQ(end)                                      \
 115         ((end) = ((end)+1) % dma_linked_lch[chain_id].no_of_lchs_linked)
 116 #define OMAP_DMA_CHAIN_INCQHEAD(chain_id)                               \
 117         do {                                                            \
 118                 __OMAP_DMA_CHAIN_INCQ(dma_linked_lch[chain_id].q_head); \
 119                 dma_linked_lch[chain_id].q_count--;                     \
 120         } while (0)
 121
 122 #define OMAP_DMA_CHAIN_INCQTAIL(chain_id)                               \
 123         do {                                                            \
 124                 __OMAP_DMA_CHAIN_INCQ(dma_linked_lch[chain_id].q_tail); \
 125                 dma_linked_lch[chain_id].q_count++; \
 126         } while (0)
 127 #endif
 128
 129 static int dma_lch_count;
 130 static int dma_chan_count;
 131 static int omap_dma_reserve_channels;
 132
 133 static spinlock_t dma_chan_lock;
 134 static struct omap_dma_lch *dma_chan;
 135
 136 static inline void disable_lnk(int lch);
 137 static void omap_disable_channel_irq(int lch);
 138 static inline void omap_enable_channel_irq(int lch);
 139
 140 #define REVISIT_24XX()          printk(KERN_ERR "FIXME: no %s on 24xx\n", \
 141                                                 __func__);
 142
 143 #ifdef CONFIG_ARCH_OMAP15XX
 144 /* Returns 1 if the DMA module is in OMAP1510-compatible mode, 0 otherwise */
 145 static int omap_dma_in_1510_mode(void)
 146 {
 147         return enable_1510_mode;
 148 }
 149 #else
 150 #define omap_dma_in_1510_mode()         0
 151 #endif
 152
 153 #ifdef CONFIG_ARCH_OMAP1
 154 static inline int get_gdma_dev(int req)
 155 {
 156         u32 reg = OMAP_FUNC_MUX_ARM_BASE + ((req - 1) / 5) * 4;
 157         int shift = ((req - 1) % 5) * 6;
 158
 159         return ((omap_readl(reg) >> shift) & 0x3f) + 1;
 160 }
 161
 162 static inline void set_gdma_dev(int req, int dev)
 163 {
 164         u32 reg = OMAP_FUNC_MUX_ARM_BASE + ((req - 1) / 5) * 4;
 165         int shift = ((req - 1) % 5) * 6;
 166         u32 l;
 167
 168         l = omap_readl(reg);
 169         l &= ~(0x3f << shift);
 170         l |= (dev - 1) << shift;
 171         omap_writel(l, reg);
 172 }
 173 #else
 174 #define set_gdma_dev(req, dev)  do {} while (0)
 175 #define omap_readl(reg)         0
 176 #define omap_writel(val, reg)   do {} while (0)
 177 #endif
 178
 179 #ifdef CONFIG_ARCH_OMAP1
 180 void omap_set_dma_priority(int lch, int dst_port, int priority)
 181 {
 182         unsigned long reg;
 183         u32 l;
 184
 185         if (dma_omap1()) {
 186                 switch (dst_port) {
 187                 case OMAP_DMA_PORT_OCP_T1:      /* FFFECC00 */
 188                         reg = OMAP_TC_OCPT1_PRIOR;
 189                         break;
 190                 case OMAP_DMA_PORT_OCP_T2:      /* FFFECCD0 */
 191                         reg = OMAP_TC_OCPT2_PRIOR;
 192                         break;
 193                 case OMAP_DMA_PORT_EMIFF:       /* FFFECC08 */
 194                         reg = OMAP_TC_EMIFF_PRIOR;
 195                         break;
 196                 case OMAP_DMA_PORT_EMIFS:       /* FFFECC04 */
 197                         reg = OMAP_TC_EMIFS_PRIOR;
 198                         break;
 199                 default:
 200                         BUG();
 201                         return;
 202                 }
 203                 l = omap_readl(reg);
 204                 l &= ~(0xf << 8);
 205                 l |= (priority & 0xf) << 8;
 206                 omap_writel(l, reg);
 207         }
 208 }
 209 #endif
 210
 211 #ifdef CONFIG_ARCH_OMAP2PLUS
 212 void omap_set_dma_priority(int lch, int dst_port, int priority)
 213 {
 214         u32 ccr;
 215
 216         ccr = p->dma_read(CCR, lch);
 217         if (priority)
 218                 ccr |= (1 << 6);
 219         else
 220                 ccr &= ~(1 << 6);
 221         p->dma_write(ccr, CCR, lch);
 222 }
 223 #endif
 224 EXPORT_SYMBOL(omap_set_dma_priority);
 225
 226 void omap_set_dma_transfer_params(int lch, int data_type, int elem_count,
 227                                   int frame_count, int sync_mode,
 228                                   int dma_trigger, int src_or_dst_synch)
 229 {
 230         u32 l;
 231
 232         l = p->dma_read(CSDP, lch);
 233         l &= ~0x03;
 234         l |= data_type;
 235         p->dma_write(l, CSDP, lch);
 236
 237         if (dma_omap1()) {
 238                 u16 ccr;
 239
 240                 ccr = p->dma_read(CCR, lch);
 241                 ccr &= ~(1 << 5);
 242                 if (sync_mode == OMAP_DMA_SYNC_FRAME)
 243                         ccr |= 1 << 5;
 244                 p->dma_write(ccr, CCR, lch);
 245
 246                 ccr = p->dma_read(CCR2, lch);
 247                 ccr &= ~(1 << 2);
 248                 if (sync_mode == OMAP_DMA_SYNC_BLOCK)
 249                         ccr |= 1 << 2;
 250                 p->dma_write(ccr, CCR2, lch);
 251         }
 252
 253         if (dma_omap2plus() && dma_trigger) {
 254                 u32 val;
 255
 256                 val = p->dma_read(CCR, lch);
 257
 258                 /* DMA_SYNCHRO_CONTROL_UPPER depends on the channel number */
 259                 val &= ~((1 << 23) | (3 << 19) | 0x1f);
 260                 val |= (dma_trigger & ~0x1f) << 14;
 261                 val |= dma_trigger & 0x1f;
 262
 263                 if (sync_mode & OMAP_DMA_SYNC_FRAME)
 264                         val |= 1 << 5;
 265                 else
 266                         val &= ~(1 << 5);
 267
 268                 if (sync_mode & OMAP_DMA_SYNC_BLOCK)
 269                         val |= 1 << 18;
 270                 else
 271                         val &= ~(1 << 18);
 272
 273                 if (src_or_dst_synch == OMAP_DMA_DST_SYNC_PREFETCH) {
 274                         val &= ~(1 << 24);      /* dest synch */
 275                         val |= (1 << 23);       /* Prefetch */
 276                 } else if (src_or_dst_synch) {
 277                         val |= 1 << 24;         /* source synch */
 278                 } else {
 279                         val &= ~(1 << 24);      /* dest synch */
 280                 }
 281                 p->dma_write(val, CCR, lch);
 282         }
 283
 284         p->dma_write(elem_count, CEN, lch);
 285         p->dma_write(frame_count, CFN, lch);
 286 }
 287 EXPORT_SYMBOL(omap_set_dma_transfer_params);
 288
 289 void omap_set_dma_write_mode(int lch, enum omap_dma_write_mode mode)
 290 {
 291         if (dma_omap2plus()) {
 292                 u32 csdp;
 293
 294                 csdp = p->dma_read(CSDP, lch);
 295                 csdp &= ~(0x3 << 16);
 296                 csdp |= (mode << 16);
 297                 p->dma_write(csdp, CSDP, lch);
 298         }
 299 }
 300 EXPORT_SYMBOL(omap_set_dma_write_mode);
 301
 302 void omap_set_dma_channel_mode(int lch, enum omap_dma_channel_mode mode)
 303 {
 304         if (dma_omap1() && !dma_omap15xx()) {
 305                 u32 l;
 306
 307                 l = p->dma_read(LCH_CTRL, lch);
 308                 l &= ~0x7;
 309                 l |= mode;
 310                 p->dma_write(l, LCH_CTRL, lch);
 311         }
 312 }
 313 EXPORT_SYMBOL(omap_set_dma_channel_mode);
 314
 315 /* Note that src_port is only for omap1 */
 316 void omap_set_dma_src_params(int lch, int src_port, int src_amode,
 317                              unsigned long src_start,
 318                              int src_ei, int src_fi)
 319 {
 320         u32 l;
 321
 322         if (dma_omap1()) {
 323                 u16 w;
 324
 325                 w = p->dma_read(CSDP, lch);
 326                 w &= ~(0x1f << 2);
 327                 w |= src_port << 2;
 328                 p->dma_write(w, CSDP, lch);
 329         }
 330
 331         l = p->dma_read(CCR, lch);
 332         l &= ~(0x03 << 12);
 333         l |= src_amode << 12;
 334         p->dma_write(l, CCR, lch);
 335
 336         p->dma_write(src_start, CSSA, lch);
 337
 338         p->dma_write(src_ei, CSEI, lch);
 339         p->dma_write(src_fi, CSFI, lch);
 340 }
 341 EXPORT_SYMBOL(omap_set_dma_src_params);
 342
 343 void omap_set_dma_params(int lch, struct omap_dma_channel_params *params)
 344 {
 345         omap_set_dma_transfer_params(lch, params->data_type,
 346                                      params->elem_count, params->frame_count,
 347                                      params->sync_mode, params->trigger,
 348                                      params->src_or_dst_synch);
 349         omap_set_dma_src_params(lch, params->src_port,
 350                                 params->src_amode, params->src_start,
 351                                 params->src_ei, params->src_fi);
 352
 353         omap_set_dma_dest_params(lch, params->dst_port,
 354                                  params->dst_amode, params->dst_start,
 355                                  params->dst_ei, params->dst_fi);
 356         if (params->read_prio || params->write_prio)
 357                 omap_dma_set_prio_lch(lch, params->read_prio,
 358                                       params->write_prio);
 359 }
 360 EXPORT_SYMBOL(omap_set_dma_params);
 361
 362 void omap_set_dma_src_data_pack(int lch, int enable)
 363 {
 364         u32 l;
 365
 366         l = p->dma_read(CSDP, lch);
 367         l &= ~(1 << 6);
 368         if (enable)
 369                 l |= (1 << 6);
 370         p->dma_write(l, CSDP, lch);
 371 }
 372 EXPORT_SYMBOL(omap_set_dma_src_data_pack);
 373
 374 void omap_set_dma_src_burst_mode(int lch, enum omap_dma_burst_mode burst_mode)
 375 {
 376         unsigned int burst = 0;
 377         u32 l;
 378
 379         l = p->dma_read(CSDP, lch);
 380         l &= ~(0x03 << 7);
 381
 382         switch (burst_mode) {
 383         case OMAP_DMA_DATA_BURST_DIS:
 384                 break;
 385         case OMAP_DMA_DATA_BURST_4:
 386                 if (dma_omap2plus())
 387                         burst = 0x1;
 388                 else
 389                         burst = 0x2;
 390                 break;
 391         case OMAP_DMA_DATA_BURST_8:
 392                 if (dma_omap2plus()) {
 393                         burst = 0x2;
 394                         break;
 395                 }
 396                 /*
 397                  * not supported by current hardware on OMAP1
 398                  * w |= (0x03 << 7);
 399                  * fall through
 400                  */
 401         case OMAP_DMA_DATA_BURST_16:
 402                 if (dma_omap2plus()) {
 403                         burst = 0x3;
 404                         break;
 405                 }
 406                 /*
 407                  * OMAP1 don't support burst 16
 408                  * fall through
 409                  */
 410         default:
 411                 BUG();
 412         }
 413
 414         l |= (burst << 7);
 415         p->dma_write(l, CSDP, lch);
 416 }
 417 EXPORT_SYMBOL(omap_set_dma_src_burst_mode);
 418
 419 /* Note that dest_port is only for OMAP1 */
 420 void omap_set_dma_dest_params(int lch, int dest_port, int dest_amode,
 421                               unsigned long dest_start,
 422                               int dst_ei, int dst_fi)
 423 {
 424         u32 l;
 425
 426         if (dma_omap1()) {
 427                 l = p->dma_read(CSDP, lch);
 428                 l &= ~(0x1f << 9);
 429                 l |= dest_port << 9;
 430                 p->dma_write(l, CSDP, lch);
 431         }
 432
 433         l = p->dma_read(CCR, lch);
 434         l &= ~(0x03 << 14);
 435         l |= dest_amode << 14;
 436         p->dma_write(l, CCR, lch);
 437
 438         p->dma_write(dest_start, CDSA, lch);
 439
 440         p->dma_write(dst_ei, CDEI, lch);
 441         p->dma_write(dst_fi, CDFI, lch);
 442 }
 443 EXPORT_SYMBOL(omap_set_dma_dest_params);
 444
 445 void omap_set_dma_dest_data_pack(int lch, int enable)
 446 {
 447         u32 l;
 448
 449         l = p->dma_read(CSDP, lch);
 450         l &= ~(1 << 13);
 451         if (enable)
 452                 l |= 1 << 13;
 453         p->dma_write(l, CSDP, lch);
 454 }
 455 EXPORT_SYMBOL(omap_set_dma_dest_data_pack);
 456
 457 void omap_set_dma_dest_burst_mode(int lch, enum omap_dma_burst_mode burst_mode)
 458 {
 459         unsigned int burst = 0;
 460         u32 l;
 461
 462         l = p->dma_read(CSDP, lch);
 463         l &= ~(0x03 << 14);
 464
 465         switch (burst_mode) {
 466         case OMAP_DMA_DATA_BURST_DIS:
 467                 break;
 468         case OMAP_DMA_DATA_BURST_4:
 469                 if (dma_omap2plus())
 470                         burst = 0x1;
 471                 else
 472                         burst = 0x2;
 473                 break;
 474         case OMAP_DMA_DATA_BURST_8:
 475                 if (dma_omap2plus())
 476                         burst = 0x2;
 477                 else
 478                         burst = 0x3;
 479                 break;
 480         case OMAP_DMA_DATA_BURST_16:
 481                 if (dma_omap2plus()) {
 482                         burst = 0x3;
 483                         break;
 484                 }
 485                 /*
 486                  * OMAP1 don't support burst 16
 487                  * fall through
 488                  */
 489         default:
 490                 printk(KERN_ERR "Invalid DMA burst mode\n");
 491                 BUG();
 492                 return;
 493         }
 494         l |= (burst << 14);
 495         p->dma_write(l, CSDP, lch);
 496 }
 497 EXPORT_SYMBOL(omap_set_dma_dest_burst_mode);
 498
 499 static inline void omap_enable_channel_irq(int lch)
 500 {
 501         /* Clear CSR */
 502         if (dma_omap1())
 503                 p->dma_read(CSR, lch);
 504         else
 505                 p->dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR, lch);
 506
 507         /* Enable some nice interrupts. */
 508         p->dma_write(dma_chan[lch].enabled_irqs, CICR, lch);
 509 }
 510
 511 static inline void omap_disable_channel_irq(int lch)
 512 {
 513         /* disable channel interrupts */
 514         p->dma_write(0, CICR, lch);
 515         /* Clear CSR */
 516         if (dma_omap1())
 517                 p->dma_read(CSR, lch);
 518         else
 519                 p->dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR, lch);
 520 }
 521
 522 void omap_enable_dma_irq(int lch, u16 bits)
 523 {
 524         dma_chan[lch].enabled_irqs |= bits;
 525 }
 526 EXPORT_SYMBOL(omap_enable_dma_irq);
 527
 528 void omap_disable_dma_irq(int lch, u16 bits)
 529 {
 530         dma_chan[lch].enabled_irqs &= ~bits;
 531 }
 532 EXPORT_SYMBOL(omap_disable_dma_irq);
 533
 534 static inline void enable_lnk(int lch)
 535 {
 536         u32 l;
 537
 538         l = p->dma_read(CLNK_CTRL, lch);
 539
 540         if (dma_omap1())
 541                 l &= ~(1 << 14);
 542
 543         /* Set the ENABLE_LNK bits */
 544         if (dma_chan[lch].next_lch != -1)
 545                 l = dma_chan[lch].next_lch | (1 << 15);
 546
 547 #ifndef CONFIG_ARCH_OMAP1
 548         if (dma_omap2plus())
 549                 if (dma_chan[lch].next_linked_ch != -1)
 550                         l = dma_chan[lch].next_linked_ch | (1 << 15);
 551 #endif
 552
 553         p->dma_write(l, CLNK_CTRL, lch);
 554 }
 555
 556 static inline void disable_lnk(int lch)
 557 {
 558         u32 l;
 559
 560         l = p->dma_read(CLNK_CTRL, lch);
 561
 562         /* Disable interrupts */
 563         omap_disable_channel_irq(lch);
 564
 565         if (dma_omap1()) {
 566                 /* Set the STOP_LNK bit */
 567                 l |= 1 << 14;
 568         }
 569
 570         if (dma_omap2plus()) {
 571                 /* Clear the ENABLE_LNK bit */
 572                 l &= ~(1 << 15);
 573         }
 574
 575         p->dma_write(l, CLNK_CTRL, lch);
 576         dma_chan[lch].flags &= ~OMAP_DMA_ACTIVE;
 577 }
 578
 579 static inline void omap2_enable_irq_lch(int lch)
 580 {
 581         u32 val;
 582         unsigned long flags;
 583
 584         if (dma_omap1())
 585                 return;
 586
 587         spin_lock_irqsave(&dma_chan_lock, flags);
 588         /* clear IRQ STATUS */
 589         p->dma_write(1 << lch, IRQSTATUS_L0, lch);
 590         /* Enable interrupt */
 591         val = p->dma_read(IRQENABLE_L0, lch);
 592         val |= 1 << lch;
 593         p->dma_write(val, IRQENABLE_L0, lch);
 594         spin_unlock_irqrestore(&dma_chan_lock, flags);
 595 }
 596
 597 static inline void omap2_disable_irq_lch(int lch)
 598 {
 599         u32 val;
 600         unsigned long flags;
 601
 602         if (dma_omap1())
 603                 return;
 604
 605         spin_lock_irqsave(&dma_chan_lock, flags);
 606         /* Disable interrupt */
 607         val = p->dma_read(IRQENABLE_L0, lch);
 608         val &= ~(1 << lch);
 609         p->dma_write(val, IRQENABLE_L0, lch);
 610         /* clear IRQ STATUS */
 611         p->dma_write(1 << lch, IRQSTATUS_L0, lch);
 612         spin_unlock_irqrestore(&dma_chan_lock, flags);
 613 }
 614
 615 int omap_request_dma(int dev_id, const char *dev_name,
 616                      void (*callback)(int lch, u16 ch_status, void *data),
 617                      void *data, int *dma_ch_out)
 618 {
 619         int ch, free_ch = -1;
 620         unsigned long flags;
 621         struct omap_dma_lch *chan;
 622
 623         WARN(strcmp(dev_name, "DMA engine"), "Using deprecated platform DMA API - please update to DMA engine");
 624
 625         spin_lock_irqsave(&dma_chan_lock, flags);
 626         for (ch = 0; ch < dma_chan_count; ch++) {
 627                 if (free_ch == -1 && dma_chan[ch].dev_id == -1) {
 628                         free_ch = ch;
 629                         /* Exit after first free channel found */
 630                         break;
 631                 }
 632         }
 633         if (free_ch == -1) {
 634                 spin_unlock_irqrestore(&dma_chan_lock, flags);
 635                 return -EBUSY;
 636         }
 637         chan = dma_chan + free_ch;
 638         chan->dev_id = dev_id;
 639
 640         if (p->clear_lch_regs)
 641                 p->clear_lch_regs(free_ch);
 642
 643         if (dma_omap2plus())
 644                 omap_clear_dma(free_ch);
 645
 646         spin_unlock_irqrestore(&dma_chan_lock, flags);
 647
 648         chan->dev_name = dev_name;
 649         chan->callback = callback;
 650         chan->data = data;
 651         chan->flags = 0;
 652
 653 #ifndef CONFIG_ARCH_OMAP1
 654         if (dma_omap2plus()) {
 655                 chan->chain_id = -1;
 656                 chan->next_linked_ch = -1;
 657         }
 658 #endif
 659
 660         chan->enabled_irqs = OMAP_DMA_DROP_IRQ | OMAP_DMA_BLOCK_IRQ;
 661
 662         if (dma_omap1())
 663                 chan->enabled_irqs |= OMAP1_DMA_TOUT_IRQ;
 664         else if (dma_omap2plus())
 665                 chan->enabled_irqs |= OMAP2_DMA_MISALIGNED_ERR_IRQ |
 666                         OMAP2_DMA_TRANS_ERR_IRQ;
 667
 668         if (dma_omap16xx()) {
 669                 /* If the sync device is set, configure it dynamically. */
 670                 if (dev_id != 0) {
 671                         set_gdma_dev(free_ch + 1, dev_id);
 672                         dev_id = free_ch + 1;
 673                 }
 674                 /*
 675                  * Disable the 1510 compatibility mode and set the sync device
 676                  * id.
 677                  */
 678                 p->dma_write(dev_id | (1 << 10), CCR, free_ch);
 679         } else if (dma_omap1()) {
 680                 p->dma_write(dev_id, CCR, free_ch);
 681         }
 682
 683         if (dma_omap2plus()) {
 684                 omap_enable_channel_irq(free_ch);
 685                 omap2_enable_irq_lch(free_ch);
 686         }
 687
 688         *dma_ch_out = free_ch;
 689
 690         return 0;
 691 }
 692 EXPORT_SYMBOL(omap_request_dma);
 693
 694 void omap_free_dma(int lch)
 695 {
 696         unsigned long flags;
 697
 698         if (dma_chan[lch].dev_id == -1) {
 699                 pr_err("omap_dma: trying to free unallocated DMA channel %d\n",
 700                        lch);
 701                 return;
 702         }
 703
 704         /* Disable interrupt for logical channel */
 705         if (dma_omap2plus())
 706                 omap2_disable_irq_lch(lch);
 707
 708         /* Disable all DMA interrupts for the channel. */
 709         omap_disable_channel_irq(lch);
 710
 711         /* Make sure the DMA transfer is stopped. */
 712         p->dma_write(0, CCR, lch);
 713
 714         /* Clear registers */
 715         if (dma_omap2plus())
 716                 omap_clear_dma(lch);
 717
 718         spin_lock_irqsave(&dma_chan_lock, flags);
 719         dma_chan[lch].dev_id = -1;
 720         dma_chan[lch].next_lch = -1;
 721         dma_chan[lch].callback = NULL;
 722         spin_unlock_irqrestore(&dma_chan_lock, flags);
 723 }
 724 EXPORT_SYMBOL(omap_free_dma);
 725
 726 /**
 727  * @brief omap_dma_set_global_params : Set global priority settings for dma
 728  *
 729  * @param arb_rate
 730  * @param max_fifo_depth
 731  * @param tparams - Number of threads to reserve : DMA_THREAD_RESERVE_NORM
 732  *                                                 DMA_THREAD_RESERVE_ONET
 733  *                                                 DMA_THREAD_RESERVE_TWOT
 734  *                                                 DMA_THREAD_RESERVE_THREET
 735  */
 736 void
 737 omap_dma_set_global_params(int arb_rate, int max_fifo_depth, int tparams)
 738 {
 739         u32 reg;
 740
 741         if (dma_omap1()) {
 742                 printk(KERN_ERR "FIXME: no %s on 15xx/16xx\n", __func__);
 743                 return;
 744         }
 745
 746         if (max_fifo_depth == 0)
 747                 max_fifo_depth = 1;
 748         if (arb_rate == 0)
 749                 arb_rate = 1;
 750
 751         reg = 0xff & max_fifo_depth;
 752         reg |= (0x3 & tparams) << 12;
 753         reg |= (arb_rate & 0xff) << 16;
 754
 755         p->dma_write(reg, GCR, 0);
 756 }
 757 EXPORT_SYMBOL(omap_dma_set_global_params);
 758
 759 /**
 760  * @brief omap_dma_set_prio_lch : Set channel wise priority settings
 761  *
 762  * @param lch
 763  * @param read_prio - Read priority
 764  * @param write_prio - Write priority
 765  * Both of the above can be set with one of the following values :
 766  *      DMA_CH_PRIO_HIGH/DMA_CH_PRIO_LOW
 767  */
 768 static int
 769 omap_dma_set_prio_lch(int lch, unsigned char read_prio,
 770                       unsigned char write_prio)
 771 {
 772         u32 l;
 773
 774         if (unlikely((lch < 0 || lch >= dma_lch_count))) {
 775                 printk(KERN_ERR "Invalid channel id\n");
 776                 return -EINVAL;
 777         }
 778         l = p->dma_read(CCR, lch);
 779         l &= ~((1 << 6) | (1 << 26));
 780         if (d->dev_caps & IS_RW_PRIORITY)
 781                 l |= ((read_prio & 0x1) << 6) | ((write_prio & 0x1) << 26);
 782         else
 783                 l |= ((read_prio & 0x1) << 6);
 784
 785         p->dma_write(l, CCR, lch);
 786
 787         return 0;
 788 }
 789
 790
 791 /*
 792  * Clears any DMA state so the DMA engine is ready to restart with new buffers
 793  * through omap_start_dma(). Any buffers in flight are discarded.
 794  */
 795 static void omap_clear_dma(int lch)
 796 {
 797         unsigned long flags;
 798
 799         local_irq_save(flags);
 800         p->clear_dma(lch);
 801         local_irq_restore(flags);
 802 }
 803
 804 void omap_start_dma(int lch)
 805 {
 806         u32 l;
 807
 808         /*
 809          * The CPC/CDAC register needs to be initialized to zero
 810          * before starting dma transfer.
 811          */
 812         if (dma_omap15xx())
 813                 p->dma_write(0, CPC, lch);
 814         else
 815                 p->dma_write(0, CDAC, lch);
 816
 817         if (!omap_dma_in_1510_mode() && dma_chan[lch].next_lch != -1) {
 818                 int next_lch, cur_lch;
 819                 char dma_chan_link_map[MAX_LOGICAL_DMA_CH_COUNT];
 820
 821                 /* Set the link register of the first channel */
 822                 enable_lnk(lch);
 823
 824                 memset(dma_chan_link_map, 0, sizeof(dma_chan_link_map));
 825                 dma_chan_link_map[lch] = 1;
 826
 827                 cur_lch = dma_chan[lch].next_lch;
 828                 do {
 829                         next_lch = dma_chan[cur_lch].next_lch;
 830
 831                         /* The loop case: we've been here already */
 832                         if (dma_chan_link_map[cur_lch])
 833                                 break;
 834                         /* Mark the current channel */
 835                         dma_chan_link_map[cur_lch] = 1;
 836
 837                         enable_lnk(cur_lch);
 838                         omap_enable_channel_irq(cur_lch);
 839
 840                         cur_lch = next_lch;
 841                 } while (next_lch != -1);
 842         } else if (IS_DMA_ERRATA(DMA_ERRATA_PARALLEL_CHANNELS))
 843                 p->dma_write(lch, CLNK_CTRL, lch);
 844
 845         omap_enable_channel_irq(lch);
 846
 847         l = p->dma_read(CCR, lch);
 848
 849         if (IS_DMA_ERRATA(DMA_ERRATA_IFRAME_BUFFERING))
 850                         l |= OMAP_DMA_CCR_BUFFERING_DISABLE;
 851         l |= OMAP_DMA_CCR_EN;
 852
 853         /*
 854          * As dma_write() uses IO accessors which are weakly ordered, there
 855          * is no guarantee that data in coherent DMA memory will be visible
 856          * to the DMA device.  Add a memory barrier here to ensure that any
 857          * such data is visible prior to enabling DMA.
 858          */
 859         mb();
 860         p->dma_write(l, CCR, lch);
 861
 862         dma_chan[lch].flags |= OMAP_DMA_ACTIVE;
 863 }
 864 EXPORT_SYMBOL(omap_start_dma);
 865
 866 void omap_stop_dma(int lch)
 867 {
 868         u32 l;
 869
 870         /* Disable all interrupts on the channel */
 871         omap_disable_channel_irq(lch);
 872
 873         l = p->dma_read(CCR, lch);
 874         if (IS_DMA_ERRATA(DMA_ERRATA_i541) &&
 875                         (l & OMAP_DMA_CCR_SEL_SRC_DST_SYNC)) {
 876                 int i = 0;
 877                 u32 sys_cf;
 878
 879                 /* Configure No-Standby */
 880                 l = p->dma_read(OCP_SYSCONFIG, lch);
 881                 sys_cf = l;
 882                 l &= ~DMA_SYSCONFIG_MIDLEMODE_MASK;
 883                 l |= DMA_SYSCONFIG_MIDLEMODE(DMA_IDLEMODE_NO_IDLE);
 884                 p->dma_write(l , OCP_SYSCONFIG, 0);
 885
 886                 l = p->dma_read(CCR, lch);
 887                 l &= ~OMAP_DMA_CCR_EN;
 888                 p->dma_write(l, CCR, lch);
 889
 890                 /* Wait for sDMA FIFO drain */
 891                 l = p->dma_read(CCR, lch);
 892                 while (i < 100 && (l & (OMAP_DMA_CCR_RD_ACTIVE |
 893                                         OMAP_DMA_CCR_WR_ACTIVE))) {
 894                         udelay(5);
 895                         i++;
 896                         l = p->dma_read(CCR, lch);
 897                 }
 898                 if (i >= 100)
 899                         pr_err("DMA drain did not complete on lch %d\n", lch);
 900                 /* Restore OCP_SYSCONFIG */
 901                 p->dma_write(sys_cf, OCP_SYSCONFIG, lch);
 902         } else {
 903                 l &= ~OMAP_DMA_CCR_EN;
 904                 p->dma_write(l, CCR, lch);
 905         }
 906
 907         /*
 908          * Ensure that data transferred by DMA is visible to any access
 909          * after DMA has been disabled.  This is important for coherent
 910          * DMA regions.
 911          */
 912         mb();
 913
 914         if (!omap_dma_in_1510_mode() && dma_chan[lch].next_lch != -1) {
 915                 int next_lch, cur_lch = lch;
 916                 char dma_chan_link_map[MAX_LOGICAL_DMA_CH_COUNT];
 917
 918                 memset(dma_chan_link_map, 0, sizeof(dma_chan_link_map));
 919                 do {
 920                         /* The loop case: we've been here already */
 921                         if (dma_chan_link_map[cur_lch])
 922                                 break;
 923                         /* Mark the current channel */
 924                         dma_chan_link_map[cur_lch] = 1;
 925
 926                         disable_lnk(cur_lch);
 927
 928                         next_lch = dma_chan[cur_lch].next_lch;
 929                         cur_lch = next_lch;
 930                 } while (next_lch != -1);
 931         }
 932
 933         dma_chan[lch].flags &= ~OMAP_DMA_ACTIVE;
 934 }
 935 EXPORT_SYMBOL(omap_stop_dma);
 936
 937 /*
 938  * Allows changing the DMA callback function or data. This may be needed if
 939  * the driver shares a single DMA channel for multiple dma triggers.
 940  */
 941 int omap_set_dma_callback(int lch,
 942                           void (*callback)(int lch, u16 ch_status, void *data),
 943                           void *data)
 944 {
 945         unsigned long flags;
 946
 947         if (lch < 0)
 948                 return -ENODEV;
 949
 950         spin_lock_irqsave(&dma_chan_lock, flags);
 951         if (dma_chan[lch].dev_id == -1) {
 952                 printk(KERN_ERR "DMA callback for not set for free channel\n");
 953                 spin_unlock_irqrestore(&dma_chan_lock, flags);
 954                 return -EINVAL;
 955         }
 956         dma_chan[lch].callback = callback;
 957         dma_chan[lch].data = data;
 958         spin_unlock_irqrestore(&dma_chan_lock, flags);
 959
 960         return 0;
 961 }
 962 EXPORT_SYMBOL(omap_set_dma_callback);
 963
 964 /*
 965  * Returns current physical source address for the given DMA channel.
 966  * If the channel is running the caller must disable interrupts prior calling
 967  * this function and process the returned value before re-enabling interrupt to
 968  * prevent races with the interrupt handler. Note that in continuous mode there
 969  * is a chance for CSSA_L register overflow between the two reads resulting
 970  * in incorrect return value.
 971  */
 972 dma_addr_t omap_get_dma_src_pos(int lch)
 973 {
 974         dma_addr_t offset = 0;
 975
 976         if (dma_omap15xx())
 977                 offset = p->dma_read(CPC, lch);
 978         else
 979                 offset = p->dma_read(CSAC, lch);
 980
 981         if (IS_DMA_ERRATA(DMA_ERRATA_3_3) && offset == 0)
 982                 offset = p->dma_read(CSAC, lch);
 983
 984         if (!dma_omap15xx()) {
 985                 /*
 986                  * CDAC == 0 indicates that the DMA transfer on the channel has
 987                  * not been started (no data has been transferred so far).
 988                  * Return the programmed source start address in this case.
 989                  */
 990                 if (likely(p->dma_read(CDAC, lch)))
 991                         offset = p->dma_read(CSAC, lch);
 992                 else
 993                         offset = p->dma_read(CSSA, lch);
 994         }
 995
 996         if (dma_omap1())
 997                 offset |= (p->dma_read(CSSA, lch) & 0xFFFF0000);
 998
 999         return offset;
1000 }
1001 EXPORT_SYMBOL(omap_get_dma_src_pos);
1002
1003 /*
1004  * Returns current physical destination address for the given DMA channel.
1005  * If the channel is running the caller must disable interrupts prior calling
1006  * this function and process the returned value before re-enabling interrupt to
1007  * prevent races with the interrupt handler. Note that in continuous mode there
1008  * is a chance for CDSA_L register overflow between the two reads resulting
1009  * in incorrect return value.
1010  */
1011 dma_addr_t omap_get_dma_dst_pos(int lch)
1012 {
1013         dma_addr_t offset = 0;
1014
1015         if (dma_omap15xx())
1016                 offset = p->dma_read(CPC, lch);
1017         else
1018                 offset = p->dma_read(CDAC, lch);
1019
1020         /*
1021          * omap 3.2/3.3 erratum: sometimes 0 is returned if CSAC/CDAC is
1022          * read before the DMA controller finished disabling the channel.
1023          */
1024         if (!dma_omap15xx() && offset == 0) {
1025                 offset = p->dma_read(CDAC, lch);
1026                 /*
1027                  * CDAC == 0 indicates that the DMA transfer on the channel has
1028                  * not been started (no data has been transferred so far).
1029                  * Return the programmed destination start address in this case.
1030                  */
1031                 if (unlikely(!offset))
1032                         offset = p->dma_read(CDSA, lch);
1033         }
1034
1035         if (dma_omap1())
1036                 offset |= (p->dma_read(CDSA, lch) & 0xFFFF0000);
1037
1038         return offset;
1039 }
1040 EXPORT_SYMBOL(omap_get_dma_dst_pos);
1041
1042 int omap_get_dma_active_status(int lch)
1043 {
1044         return (p->dma_read(CCR, lch) & OMAP_DMA_CCR_EN) != 0;
1045 }
1046 EXPORT_SYMBOL(omap_get_dma_active_status);
1047
1048 int omap_dma_running(void)
1049 {
1050         int lch;
1051
1052         if (dma_omap1())
1053                 if (omap_lcd_dma_running())
1054                         return 1;
1055
1056         for (lch = 0; lch < dma_chan_count; lch++)
1057                 if (p->dma_read(CCR, lch) & OMAP_DMA_CCR_EN)
1058                         return 1;
1059
1060         return 0;
1061 }
1062
1063 /*
1064  * lch_queue DMA will start right after lch_head one is finished.
1065  * For this DMA link to start, you still need to start (see omap_start_dma)
1066  * the first one. That will fire up the entire queue.
1067  */
1068 void omap_dma_link_lch(int lch_head, int lch_queue)
1069 {
1070         if (omap_dma_in_1510_mode()) {
1071                 if (lch_head == lch_queue) {
1072                         p->dma_write(p->dma_read(CCR, lch_head) | (3 << 8),
1073                                                                 CCR, lch_head);
1074                         return;
1075                 }
1076                 printk(KERN_ERR "DMA linking is not supported in 1510 mode\n");
1077                 BUG();
1078                 return;
1079         }
1080
1081         if ((dma_chan[lch_head].dev_id == -1) ||
1082             (dma_chan[lch_queue].dev_id == -1)) {
1083                 pr_err("omap_dma: trying to link non requested channels\n");
1084                 dump_stack();
1085         }
1086
1087         dma_chan[lch_head].next_lch = lch_queue;
1088 }
1089 EXPORT_SYMBOL(omap_dma_link_lch);
1090
1091 /*----------------------------------------------------------------------------*/
1092
1093 #ifdef CONFIG_ARCH_OMAP1
1094
1095 static int omap1_dma_handle_ch(int ch)
1096 {
1097         u32 csr;
1098
1099         if (enable_1510_mode && ch >= 6) {
1100                 csr = dma_chan[ch].saved_csr;
1101                 dma_chan[ch].saved_csr = 0;
1102         } else
1103                 csr = p->dma_read(CSR, ch);
1104         if (enable_1510_mode && ch <= 2 && (csr >> 7) != 0) {
1105                 dma_chan[ch + 6].saved_csr = csr >> 7;
1106                 csr &= 0x7f;
1107         }
1108         if ((csr & 0x3f) == 0)
1109                 return 0;
1110         if (unlikely(dma_chan[ch].dev_id == -1)) {
1111                 pr_warn("Spurious interrupt from DMA channel %d (CSR %04x)\n",
1112                         ch, csr);
1113                 return 0;
1114         }
1115         if (unlikely(csr & OMAP1_DMA_TOUT_IRQ))
1116                 pr_warn("DMA timeout with device %d\n", dma_chan[ch].dev_id);
1117         if (unlikely(csr & OMAP_DMA_DROP_IRQ))
1118                 pr_warn("DMA synchronization event drop occurred with device %d\n",
1119                         dma_chan[ch].dev_id);
1120         if (likely(csr & OMAP_DMA_BLOCK_IRQ))
1121                 dma_chan[ch].flags &= ~OMAP_DMA_ACTIVE;
1122         if (likely(dma_chan[ch].callback != NULL))
1123                 dma_chan[ch].callback(ch, csr, dma_chan[ch].data);
1124
1125         return 1;
1126 }
1127
1128 static irqreturn_t omap1_dma_irq_handler(int irq, void *dev_id)
1129 {
1130         int ch = ((int) dev_id) - 1;
1131         int handled = 0;
1132
1133         for (;;) {
1134                 int handled_now = 0;
1135
1136                 handled_now += omap1_dma_handle_ch(ch);
1137                 if (enable_1510_mode && dma_chan[ch + 6].saved_csr)
1138                         handled_now += omap1_dma_handle_ch(ch + 6);
1139                 if (!handled_now)
1140                         break;
1141                 handled += handled_now;
1142         }
1143
1144         return handled ? IRQ_HANDLED : IRQ_NONE;
1145 }
1146
1147 #else
1148 #define omap1_dma_irq_handler   NULL
1149 #endif
1150
1151 #ifdef CONFIG_ARCH_OMAP2PLUS
1152
1153 static int omap2_dma_handle_ch(int ch)
1154 {
1155         u32 status = p->dma_read(CSR, ch);
1156
1157         if (!status) {
1158                 if (printk_ratelimit())
1159                         pr_warn("Spurious DMA IRQ for lch %d\n", ch);
1160                 p->dma_write(1 << ch, IRQSTATUS_L0, ch);
1161                 return 0;
1162         }
1163         if (unlikely(dma_chan[ch].dev_id == -1)) {
1164                 if (printk_ratelimit())
1165                         pr_warn("IRQ %04x for non-allocated DMA channel %d\n",
1166                                 status, ch);
1167                 return 0;
1168         }
1169         if (unlikely(status & OMAP_DMA_DROP_IRQ))
1170                 pr_info("DMA synchronization event drop occurred with device %d\n",
1171                         dma_chan[ch].dev_id);
1172         if (unlikely(status & OMAP2_DMA_TRANS_ERR_IRQ)) {
1173                 printk(KERN_INFO "DMA transaction error with device %d\n",
1174                        dma_chan[ch].dev_id);
1175                 if (IS_DMA_ERRATA(DMA_ERRATA_i378)) {
1176                         u32 ccr;
1177
1178                         ccr = p->dma_read(CCR, ch);
1179                         ccr &= ~OMAP_DMA_CCR_EN;
1180                         p->dma_write(ccr, CCR, ch);
1181                         dma_chan[ch].flags &= ~OMAP_DMA_ACTIVE;
1182                 }
1183         }
1184         if (unlikely(status & OMAP2_DMA_SECURE_ERR_IRQ))
1185                 printk(KERN_INFO "DMA secure error with device %d\n",
1186                        dma_chan[ch].dev_id);
1187         if (unlikely(status & OMAP2_DMA_MISALIGNED_ERR_IRQ))
1188                 printk(KERN_INFO "DMA misaligned error with device %d\n",
1189                        dma_chan[ch].dev_id);
1190
1191         p->dma_write(status, CSR, ch);
1192         p->dma_write(1 << ch, IRQSTATUS_L0, ch);
1193         /* read back the register to flush the write */
1194         p->dma_read(IRQSTATUS_L0, ch);
1195
1196         /* If the ch is not chained then chain_id will be -1 */
1197         if (dma_chan[ch].chain_id != -1) {
1198                 int chain_id = dma_chan[ch].chain_id;
1199                 dma_chan[ch].state = DMA_CH_NOTSTARTED;
1200                 if (p->dma_read(CLNK_CTRL, ch) & (1 << 15))
1201                         dma_chan[dma_chan[ch].next_linked_ch].state =
1202                                                         DMA_CH_STARTED;
1203                 if (dma_linked_lch[chain_id].chain_mode ==
1204                                                 OMAP_DMA_DYNAMIC_CHAIN)
1205                         disable_lnk(ch);
1206
1207                 if (!OMAP_DMA_CHAIN_QEMPTY(chain_id))
1208                         OMAP_DMA_CHAIN_INCQHEAD(chain_id);
1209
1210                 status = p->dma_read(CSR, ch);
1211                 p->dma_write(status, CSR, ch);
1212         }
1213
1214         if (likely(dma_chan[ch].callback != NULL))
1215                 dma_chan[ch].callback(ch, status, dma_chan[ch].data);
1216
1217         return 0;
1218 }
1219
1220 /* STATUS register count is from 1-32 while our is 0-31 */
1221 static irqreturn_t omap2_dma_irq_handler(int irq, void *dev_id)
1222 {
1223         u32 val, enable_reg;
1224         int i;
1225
1226         val = p->dma_read(IRQSTATUS_L0, 0);
1227         if (val == 0) {
1228                 if (printk_ratelimit())
1229                         printk(KERN_WARNING "Spurious DMA IRQ\n");
1230                 return IRQ_HANDLED;
1231         }
1232         enable_reg = p->dma_read(IRQENABLE_L0, 0);
1233         val &= enable_reg; /* Dispatch only relevant interrupts */
1234         for (i = 0; i < dma_lch_count && val != 0; i++) {
1235                 if (val & 1)
1236                         omap2_dma_handle_ch(i);
1237                 val >>= 1;
1238         }
1239
1240         return IRQ_HANDLED;
1241 }
1242
1243 static struct irqaction omap24xx_dma_irq = {
1244         .name = "DMA",
1245         .handler = omap2_dma_irq_handler,
1246 };
1247
1248 #else
1249 static struct irqaction omap24xx_dma_irq;
1250 #endif
1251
1252 /*----------------------------------------------------------------------------*/
1253
1254 /*
1255  * Note that we are currently using only IRQENABLE_L0 and L1.
1256  * As the DSP may be using IRQENABLE_L2 and L3, let's not
1257  * touch those for now.
1258  */
1259 void omap_dma_global_context_save(void)
1260 {
1261         omap_dma_global_context.dma_irqenable_l0 =
1262                 p->dma_read(IRQENABLE_L0, 0);
1263         omap_dma_global_context.dma_irqenable_l1 =
1264                 p->dma_read(IRQENABLE_L1, 0);
1265         omap_dma_global_context.dma_ocp_sysconfig =
1266                 p->dma_read(OCP_SYSCONFIG, 0);
1267         omap_dma_global_context.dma_gcr = p->dma_read(GCR, 0);
1268 }
1269
1270 void omap_dma_global_context_restore(void)
1271 {
1272         int ch;
1273
1274         p->dma_write(omap_dma_global_context.dma_gcr, GCR, 0);
1275         p->dma_write(omap_dma_global_context.dma_ocp_sysconfig,
1276                 OCP_SYSCONFIG, 0);
1277         p->dma_write(omap_dma_global_context.dma_irqenable_l0,
1278                 IRQENABLE_L0, 0);
1279         p->dma_write(omap_dma_global_context.dma_irqenable_l1,
1280                 IRQENABLE_L1, 0);
1281
1282         if (IS_DMA_ERRATA(DMA_ROMCODE_BUG))
1283                 p->dma_write(0x3 , IRQSTATUS_L0, 0);
1284
1285         for (ch = 0; ch < dma_chan_count; ch++)
1286                 if (dma_chan[ch].dev_id != -1)
1287                         omap_clear_dma(ch);
1288 }
1289
1290 struct omap_system_dma_plat_info *omap_get_plat_info(void)
1291 {
1292         return p;
1293 }
1294 EXPORT_SYMBOL_GPL(omap_get_plat_info);
1295
1296 static int omap_system_dma_probe(struct platform_device *pdev)
1297 {
1298         int ch, ret = 0;
1299         int dma_irq;
1300         char irq_name[4];
1301         int irq_rel;
1302
1303         p = pdev->dev.platform_data;
1304         if (!p) {
1305                 dev_err(&pdev->dev,
1306                         "%s: System DMA initialized without platform data\n",
1307                         __func__);
1308                 return -EINVAL;
1309         }
1310
1311         d                       = p->dma_attr;
1312         errata                  = p->errata;
1313
1314         if ((d->dev_caps & RESERVE_CHANNEL) && omap_dma_reserve_channels
1315                         && (omap_dma_reserve_channels < d->lch_count))
1316                 d->lch_count    = omap_dma_reserve_channels;
1317
1318         dma_lch_count           = d->lch_count;
1319         dma_chan_count          = dma_lch_count;
1320         enable_1510_mode        = d->dev_caps & ENABLE_1510_MODE;
1321
1322         dma_chan = devm_kcalloc(&pdev->dev, dma_lch_count,
1323                                 sizeof(struct omap_dma_lch), GFP_KERNEL);
1324         if (!dma_chan) {
1325                 dev_err(&pdev->dev, "%s: kzalloc fail\n", __func__);
1326                 return -ENOMEM;
1327         }
1328
1329
1330         if (dma_omap2plus()) {
1331                 dma_linked_lch = kzalloc(sizeof(struct dma_link_info) *
1332                                                 dma_lch_count, GFP_KERNEL);
1333                 if (!dma_linked_lch) {
1334                         ret = -ENOMEM;
1335                         goto exit_dma_lch_fail;
1336                 }
1337         }
1338
1339         spin_lock_init(&dma_chan_lock);
1340         for (ch = 0; ch < dma_chan_count; ch++) {
1341                 omap_clear_dma(ch);
1342                 if (dma_omap2plus())
1343                         omap2_disable_irq_lch(ch);
1344
1345                 dma_chan[ch].dev_id = -1;
1346                 dma_chan[ch].next_lch = -1;
1347
1348                 if (ch >= 6 && enable_1510_mode)
1349                         continue;
1350
1351                 if (dma_omap1()) {
1352                         /*
1353                          * request_irq() doesn't like dev_id (ie. ch) being
1354                          * zero, so we have to kludge around this.
1355                          */
1356                         sprintf(&irq_name[0], "%d", ch);
1357                         dma_irq = platform_get_irq_byname(pdev, irq_name);
1358
1359                         if (dma_irq < 0) {
1360                                 ret = dma_irq;
1361                                 goto exit_dma_irq_fail;
1362                         }
1363
1364                         /* INT_DMA_LCD is handled in lcd_dma.c */
1365                         if (dma_irq == INT_DMA_LCD)
1366                                 continue;
1367
1368                         ret = request_irq(dma_irq,
1369                                         omap1_dma_irq_handler, 0, "DMA",
1370                                         (void *) (ch + 1));
1371                         if (ret != 0)
1372                                 goto exit_dma_irq_fail;
1373                 }
1374         }
1375
1376         if (d->dev_caps & IS_RW_PRIORITY)
1377                 omap_dma_set_global_params(DMA_DEFAULT_ARB_RATE,
1378                                 DMA_DEFAULT_FIFO_DEPTH, 0);
1379
1380         if (dma_omap2plus() && !(d->dev_caps & DMA_ENGINE_HANDLE_IRQ)) {
1381                 strcpy(irq_name, "0");
1382                 dma_irq = platform_get_irq_byname(pdev, irq_name);
1383                 if (dma_irq < 0) {
1384                         dev_err(&pdev->dev, "failed: request IRQ %d", dma_irq);
1385                         ret = dma_irq;
1386                         goto exit_dma_lch_fail;
1387                 }
1388                 ret = setup_irq(dma_irq, &omap24xx_dma_irq);
1389                 if (ret) {
1390                         dev_err(&pdev->dev, "set_up failed for IRQ %d for DMA (error %d)\n",
1391                                 dma_irq, ret);
1392                         goto exit_dma_lch_fail;
1393                 }
1394         }
1395
1396         /* reserve dma channels 0 and 1 in high security devices on 34xx */
1397         if (d->dev_caps & HS_CHANNELS_RESERVED) {
1398                 pr_info("Reserving DMA channels 0 and 1 for HS ROM code\n");
1399                 dma_chan[0].dev_id = 0;
1400                 dma_chan[1].dev_id = 1;
1401         }
1402         p->show_dma_caps();
1403         return 0;
1404
1405 exit_dma_irq_fail:
1406         dev_err(&pdev->dev, "unable to request IRQ %d for DMA (error %d)\n",
1407                 dma_irq, ret);
1408         for (irq_rel = 0; irq_rel < ch; irq_rel++) {
1409                 dma_irq = platform_get_irq(pdev, irq_rel);
1410                 free_irq(dma_irq, (void *)(irq_rel + 1));
1411         }
1412
1413 exit_dma_lch_fail:
1414         return ret;
1415 }
1416
1417 static int omap_system_dma_remove(struct platform_device *pdev)
1418 {
1419         int dma_irq;
1420
1421         if (dma_omap2plus()) {
1422                 char irq_name[4];
1423                 strcpy(irq_name, "0");
1424                 dma_irq = platform_get_irq_byname(pdev, irq_name);
1425                 if (dma_irq >= 0)
1426                         remove_irq(dma_irq, &omap24xx_dma_irq);
1427         } else {
1428                 int irq_rel = 0;
1429                 for ( ; irq_rel < dma_chan_count; irq_rel++) {
1430                         dma_irq = platform_get_irq(pdev, irq_rel);
1431                         free_irq(dma_irq, (void *)(irq_rel + 1));
1432                 }
1433         }
1434         return 0;
1435 }
1436
1437 static struct platform_driver omap_system_dma_driver = {
1438         .probe          = omap_system_dma_probe,
1439         .remove         = omap_system_dma_remove,
1440         .driver         = {
1441                 .name   = "omap_dma_system"
1442         },
1443 };
1444
1445 static int __init omap_system_dma_init(void)
1446 {
1447         return platform_driver_register(&omap_system_dma_driver);
1448 }
1449 arch_initcall(omap_system_dma_init);
1450
1451 static void __exit omap_system_dma_exit(void)
1452 {
1453         platform_driver_unregister(&omap_system_dma_driver);
1454 }
1455
1456 MODULE_DESCRIPTION("OMAP SYSTEM DMA DRIVER");
1457 MODULE_LICENSE("GPL");
1458 MODULE_ALIAS("platform:" DRIVER_NAME);
1459 MODULE_AUTHOR("Texas Instruments Inc");
1460
1461 /*
1462  * Reserve the omap SDMA channels using cmdline bootarg
1463  * "omap_dma_reserve_ch=". The valid range is 1 to 32
1464  */
1465 static int __init omap_dma_cmdline_reserve_ch(char *str)
1466 {
1467         if (get_option(&str, &omap_dma_reserve_channels) != 1)
1468                 omap_dma_reserve_channels = 0;
1469         return 1;
1470 }
1471
1472 __setup("omap_dma_reserve_ch=", omap_dma_cmdline_reserve_ch);
1473
1474