2 * linux/arch/arm/mm/proc-v7.S
4 * Copyright (C) 2001 Deep Blue Solutions Ltd.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 * This is the "shell" of the ARMv7 processor support.
12 #include <linux/init.h>
13 #include <linux/linkage.h>
14 #include <asm/assembler.h>
15 #include <asm/asm-offsets.h>
16 #include <asm/hwcap.h>
17 #include <asm/pgtable-hwdef.h>
18 #include <asm/pgtable.h>
20 #include "proc-macros.S"
22 #ifdef CONFIG_ARM_LPAE
23 #include "proc-v7-3level.S"
25 #include "proc-v7-2level.S"
28 ENTRY(cpu_v7_proc_init)
30 ENDPROC(cpu_v7_proc_init)
32 ENTRY(cpu_v7_proc_fin)
33 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
34 bic r0, r0, #0x1000 @ ...i............
35 bic r0, r0, #0x0006 @ .............ca.
36 mcr p15, 0, r0, c1, c0, 0 @ disable caches
38 ENDPROC(cpu_v7_proc_fin)
43 * Perform a soft reset of the system. Put the CPU into the
44 * same state as it would be if it had been reset, and branch
45 * to what would be the reset vector.
47 * - loc - location to jump to for soft reset
49 * This code must be executed using a flat identity mapping with
53 .pushsection .idmap.text, "ax"
55 mrc p15, 0, r1, c1, c0, 0 @ ctrl register
56 bic r1, r1, #0x1 @ ...............m
57 THUMB( bic r1, r1, #1 << 30 ) @ SCTLR.TE (Thumb exceptions)
58 mcr p15, 0, r1, c1, c0, 0 @ disable MMU
67 * Idle the processor (eg, wait for interrupt).
69 * IRQs are already disabled.
72 dsb @ WFI may enter a low-power mode
75 ENDPROC(cpu_v7_do_idle)
77 ENTRY(cpu_v7_dcache_clean_area)
78 ALT_SMP(W(nop)) @ MP extensions imply L1 PTW
81 1: dcache_line_size r2, r3
82 2: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
88 ENDPROC(cpu_v7_dcache_clean_area)
90 string cpu_v7_name, "ARMv7 Processor"
93 /* Suspend/resume support: derived from arch/arm/mach-s5pv210/sleep.S */
94 .globl cpu_v7_suspend_size
95 .equ cpu_v7_suspend_size, 4 * 9
96 #ifdef CONFIG_ARM_CPU_SUSPEND
97 ENTRY(cpu_v7_do_suspend)
98 stmfd sp!, {r4 - r10, lr}
99 mrc p15, 0, r4, c13, c0, 0 @ FCSE/PID
100 mrc p15, 0, r5, c13, c0, 3 @ User r/o thread ID
103 mrc p15, 0, r6, c3, c0, 0 @ Domain ID
104 #ifdef CONFIG_ARM_LPAE
105 mrrc p15, 1, r5, r7, c2 @ TTB 1
107 mrc p15, 0, r7, c2, c0, 1 @ TTB 1
109 mrc p15, 0, r11, c2, c0, 2 @ TTB control register
111 mrc p15, 0, r8, c1, c0, 0 @ Control register
112 mrc p15, 0, r9, c1, c0, 1 @ Auxiliary control register
113 mrc p15, 0, r10, c1, c0, 2 @ Co-processor access control
115 ldmfd sp!, {r4 - r10, pc}
116 ENDPROC(cpu_v7_do_suspend)
118 ENTRY(cpu_v7_do_resume)
120 mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache
121 mcr p15, 0, ip, c13, c0, 1 @ set reserved context ID
123 mcr p15, 0, r4, c13, c0, 0 @ FCSE/PID
124 mcr p15, 0, r5, c13, c0, 3 @ User r/o thread ID
127 mcr p15, 0, ip, c8, c7, 0 @ invalidate TLBs
128 mcr p15, 0, r6, c3, c0, 0 @ Domain ID
129 #ifdef CONFIG_ARM_LPAE
130 mcrr p15, 0, r1, ip, c2 @ TTB 0
131 mcrr p15, 1, r5, r7, c2 @ TTB 1
133 ALT_SMP(orr r1, r1, #TTB_FLAGS_SMP)
134 ALT_UP(orr r1, r1, #TTB_FLAGS_UP)
135 mcr p15, 0, r1, c2, c0, 0 @ TTB 0
136 mcr p15, 0, r7, c2, c0, 1 @ TTB 1
138 mcr p15, 0, r11, c2, c0, 2 @ TTB control register
141 mcr p15, 0, r4, c10, c2, 0 @ write PRRR
142 mcr p15, 0, r5, c10, c2, 1 @ write NMRR
143 #endif /* CONFIG_MMU */
144 mrc p15, 0, r4, c1, c0, 1 @ Read Auxiliary control register
145 teq r4, r9 @ Is it already set?
146 mcrne p15, 0, r9, c1, c0, 1 @ No, so write it
147 mcr p15, 0, r10, c1, c0, 2 @ Co-processor access control
150 mov r0, r8 @ control register
152 ENDPROC(cpu_v7_do_resume)
156 * Cortex-A9 processor functions
158 globl_equ cpu_ca9mp_proc_init, cpu_v7_proc_init
159 globl_equ cpu_ca9mp_proc_fin, cpu_v7_proc_fin
160 globl_equ cpu_ca9mp_reset, cpu_v7_reset
161 globl_equ cpu_ca9mp_do_idle, cpu_v7_do_idle
162 globl_equ cpu_ca9mp_dcache_clean_area, cpu_v7_dcache_clean_area
163 globl_equ cpu_ca9mp_switch_mm, cpu_v7_switch_mm
164 globl_equ cpu_ca9mp_set_pte_ext, cpu_v7_set_pte_ext
165 .globl cpu_ca9mp_suspend_size
166 .equ cpu_ca9mp_suspend_size, cpu_v7_suspend_size + 4 * 2
167 #ifdef CONFIG_ARM_CPU_SUSPEND
168 ENTRY(cpu_ca9mp_do_suspend)
170 mrc p15, 0, r4, c15, c0, 1 @ Diagnostic register
171 mrc p15, 0, r5, c15, c0, 0 @ Power register
175 ENDPROC(cpu_ca9mp_do_suspend)
177 ENTRY(cpu_ca9mp_do_resume)
179 mrc p15, 0, r10, c15, c0, 1 @ Read Diagnostic register
180 teq r4, r10 @ Already restored?
181 mcrne p15, 0, r4, c15, c0, 1 @ No, so restore it
182 mrc p15, 0, r10, c15, c0, 0 @ Read Power register
183 teq r5, r10 @ Already restored?
184 mcrne p15, 0, r5, c15, c0, 0 @ No, so restore it
186 ENDPROC(cpu_ca9mp_do_resume)
189 #ifdef CONFIG_CPU_PJ4B
190 globl_equ cpu_pj4b_switch_mm, cpu_v7_switch_mm
191 globl_equ cpu_pj4b_set_pte_ext, cpu_v7_set_pte_ext
192 globl_equ cpu_pj4b_proc_init, cpu_v7_proc_init
193 globl_equ cpu_pj4b_proc_fin, cpu_v7_proc_fin
194 globl_equ cpu_pj4b_reset, cpu_v7_reset
195 #ifdef CONFIG_PJ4B_ERRATA_4742
196 ENTRY(cpu_pj4b_do_idle)
197 dsb @ WFI may enter a low-power mode
201 ENDPROC(cpu_pj4b_do_idle)
203 globl_equ cpu_pj4b_do_idle, cpu_v7_do_idle
205 globl_equ cpu_pj4b_dcache_clean_area, cpu_v7_dcache_clean_area
206 #ifdef CONFIG_ARM_CPU_SUSPEND
207 ENTRY(cpu_pj4b_do_suspend)
208 stmfd sp!, {r6 - r10}
209 mrc p15, 1, r6, c15, c1, 0 @ save CP15 - extra features
210 mrc p15, 1, r7, c15, c2, 0 @ save CP15 - Aux Func Modes Ctrl 0
211 mrc p15, 1, r8, c15, c1, 2 @ save CP15 - Aux Debug Modes Ctrl 2
212 mrc p15, 1, r9, c15, c1, 1 @ save CP15 - Aux Debug Modes Ctrl 1
213 mrc p15, 0, r10, c9, c14, 0 @ save CP15 - PMC
214 stmia r0!, {r6 - r10}
215 ldmfd sp!, {r6 - r10}
217 ENDPROC(cpu_pj4b_do_suspend)
219 ENTRY(cpu_pj4b_do_resume)
220 ldmia r0!, {r6 - r10}
221 mcr p15, 1, r6, c15, c1, 0 @ restore CP15 - extra features
222 mcr p15, 1, r7, c15, c2, 0 @ restore CP15 - Aux Func Modes Ctrl 0
223 mcr p15, 1, r8, c15, c1, 2 @ restore CP15 - Aux Debug Modes Ctrl 2
224 mcr p15, 1, r9, c15, c1, 1 @ restore CP15 - Aux Debug Modes Ctrl 1
225 mcr p15, 0, r10, c9, c14, 0 @ restore CP15 - PMC
227 ENDPROC(cpu_pj4b_do_resume)
229 .globl cpu_pj4b_suspend_size
230 .equ cpu_pj4b_suspend_size, cpu_v7_suspend_size + 4 * 5
237 * Initialise TLB, Caches, and MMU state ready to switch the MMU
238 * on. Return in r0 the new CP15 C1 control register setting.
240 * This should be able to cover all ARMv7 cores.
242 * It is assumed that:
243 * - cache type register is implemented
248 mov r10, #(1 << 0) @ Cache/TLB ops broadcasting
258 ALT_SMP(mrc p15, 0, r0, c1, c0, 1)
259 ALT_UP(mov r0, #(1 << 6)) @ fake it for UP
260 tst r0, #(1 << 6) @ SMP/nAMP mode enabled?
261 orreq r0, r0, #(1 << 6) @ Enable SMP/nAMP mode
262 orreq r0, r0, r10 @ Enable CPU-specific SMP bits
263 mcreq p15, 0, r0, c1, c0, 1
268 #ifdef CONFIG_CPU_PJ4B
270 /* Auxiliary Debug Modes Control 1 Register */
271 #define PJ4B_STATIC_BP (1 << 2) /* Enable Static BP */
272 #define PJ4B_INTER_PARITY (1 << 8) /* Disable Internal Parity Handling */
273 #define PJ4B_CLEAN_LINE (1 << 16) /* Disable data transfer for clean line */
275 /* Auxiliary Debug Modes Control 2 Register */
276 #define PJ4B_FAST_LDR (1 << 23) /* Disable fast LDR */
277 #define PJ4B_SNOOP_DATA (1 << 25) /* Do not interleave write and snoop data */
278 #define PJ4B_CWF (1 << 27) /* Disable Critical Word First feature */
279 #define PJ4B_OUTSDNG_NC (1 << 29) /* Disable outstanding non cacheable rqst */
280 #define PJ4B_L1_REP_RR (1 << 30) /* L1 replacement - Strict round robin */
281 #define PJ4B_AUX_DBG_CTRL2 (PJ4B_SNOOP_DATA | PJ4B_CWF |\
282 PJ4B_OUTSDNG_NC | PJ4B_L1_REP_RR)
284 /* Auxiliary Functional Modes Control Register 0 */
285 #define PJ4B_SMP_CFB (1 << 1) /* Set SMP mode. Join the coherency fabric */
286 #define PJ4B_L1_PAR_CHK (1 << 2) /* Support L1 parity checking */
287 #define PJ4B_BROADCAST_CACHE (1 << 8) /* Broadcast Cache and TLB maintenance */
289 /* Auxiliary Debug Modes Control 0 Register */
290 #define PJ4B_WFI_WFE (1 << 22) /* WFI/WFE - serve the DVM and back to idle */
292 /* Auxiliary Debug Modes Control 1 Register */
293 mrc p15, 1, r0, c15, c1, 1
294 orr r0, r0, #PJ4B_CLEAN_LINE
295 orr r0, r0, #PJ4B_INTER_PARITY
296 bic r0, r0, #PJ4B_STATIC_BP
297 mcr p15, 1, r0, c15, c1, 1
299 /* Auxiliary Debug Modes Control 2 Register */
300 mrc p15, 1, r0, c15, c1, 2
301 bic r0, r0, #PJ4B_FAST_LDR
302 orr r0, r0, #PJ4B_AUX_DBG_CTRL2
303 mcr p15, 1, r0, c15, c1, 2
305 /* Auxiliary Functional Modes Control Register 0 */
306 mrc p15, 1, r0, c15, c2, 0
308 orr r0, r0, #PJ4B_SMP_CFB
310 orr r0, r0, #PJ4B_L1_PAR_CHK
311 orr r0, r0, #PJ4B_BROADCAST_CACHE
312 mcr p15, 1, r0, c15, c2, 0
314 /* Auxiliary Debug Modes Control 0 Register */
315 mrc p15, 1, r0, c15, c1, 0
316 orr r0, r0, #PJ4B_WFI_WFE
317 mcr p15, 1, r0, c15, c1, 0
319 #endif /* CONFIG_CPU_PJ4B */
322 adr r12, __v7_setup_stack @ the local stack
323 stmia r12, {r0-r5, r7, r9, r11, lr}
324 bl v7_flush_dcache_louis
325 ldmia r12, {r0-r5, r7, r9, r11, lr}
327 mrc p15, 0, r0, c0, c0, 0 @ read main ID register
328 and r10, r0, #0xff000000 @ ARM?
331 and r5, r0, #0x00f00000 @ variant
332 and r6, r0, #0x0000000f @ revision
333 orr r6, r6, r5, lsr #20-4 @ combine variant and revision
334 ubfx r0, r0, #4, #12 @ primary part number
336 /* Cortex-A8 Errata */
337 ldr r10, =0x00000c08 @ Cortex-A8 primary part number
340 #if defined(CONFIG_ARM_ERRATA_430973) && !defined(CONFIG_ARCH_MULTIPLATFORM)
342 teq r5, #0x00100000 @ only present in r1p*
343 mrceq p15, 0, r10, c1, c0, 1 @ read aux control register
344 orreq r10, r10, #(1 << 6) @ set IBE to 1
345 mcreq p15, 0, r10, c1, c0, 1 @ write aux control register
347 #ifdef CONFIG_ARM_ERRATA_458693
348 teq r6, #0x20 @ only present in r2p0
349 mrceq p15, 0, r10, c1, c0, 1 @ read aux control register
350 orreq r10, r10, #(1 << 5) @ set L1NEON to 1
351 orreq r10, r10, #(1 << 9) @ set PLDNOP to 1
352 mcreq p15, 0, r10, c1, c0, 1 @ write aux control register
354 #ifdef CONFIG_ARM_ERRATA_460075
355 teq r6, #0x20 @ only present in r2p0
356 mrceq p15, 1, r10, c9, c0, 2 @ read L2 cache aux ctrl register
358 orreq r10, r10, #(1 << 22) @ set the Write Allocate disable bit
359 mcreq p15, 1, r10, c9, c0, 2 @ write the L2 cache aux ctrl register
363 /* Cortex-A9 Errata */
364 2: ldr r10, =0x00000c09 @ Cortex-A9 primary part number
367 #ifdef CONFIG_ARM_ERRATA_742230
368 cmp r6, #0x22 @ only present up to r2p2
369 mrcle p15, 0, r10, c15, c0, 1 @ read diagnostic register
370 orrle r10, r10, #1 << 4 @ set bit #4
371 mcrle p15, 0, r10, c15, c0, 1 @ write diagnostic register
373 #ifdef CONFIG_ARM_ERRATA_742231
374 teq r6, #0x20 @ present in r2p0
375 teqne r6, #0x21 @ present in r2p1
376 teqne r6, #0x22 @ present in r2p2
377 mrceq p15, 0, r10, c15, c0, 1 @ read diagnostic register
378 orreq r10, r10, #1 << 12 @ set bit #12
379 orreq r10, r10, #1 << 22 @ set bit #22
380 mcreq p15, 0, r10, c15, c0, 1 @ write diagnostic register
382 #ifdef CONFIG_ARM_ERRATA_743622
383 teq r5, #0x00200000 @ only present in r2p*
384 mrceq p15, 0, r10, c15, c0, 1 @ read diagnostic register
385 orreq r10, r10, #1 << 6 @ set bit #6
386 mcreq p15, 0, r10, c15, c0, 1 @ write diagnostic register
388 #if defined(CONFIG_ARM_ERRATA_751472) && defined(CONFIG_SMP)
389 ALT_SMP(cmp r6, #0x30) @ present prior to r3p0
391 mrclt p15, 0, r10, c15, c0, 1 @ read diagnostic register
392 orrlt r10, r10, #1 << 11 @ set bit #11
393 mcrlt p15, 0, r10, c15, c0, 1 @ write diagnostic register
397 /* Cortex-A15 Errata */
398 3: ldr r10, =0x00000c0f @ Cortex-A15 primary part number
402 #ifdef CONFIG_ARM_ERRATA_773022
403 cmp r6, #0x4 @ only present up to r0p4
404 mrcle p15, 0, r10, c1, c0, 1 @ read aux control register
405 orrle r10, r10, #1 << 1 @ disable loop buffer
406 mcrle p15, 0, r10, c1, c0, 1 @ write aux control register
410 mcr p15, 0, r10, c7, c5, 0 @ I+BTB cache invalidate
412 mcr p15, 0, r10, c8, c7, 0 @ invalidate I + D TLBs
413 v7_ttb_setup r10, r4, r8, r5 @ TTBCR, TTBRx setup
416 mcr p15, 0, r5, c10, c2, 0 @ write PRRR
417 mcr p15, 0, r6, c10, c2, 1 @ write NMRR
419 dsb @ Complete invalidations
420 #ifndef CONFIG_ARM_THUMBEE
421 mrc p15, 0, r0, c0, c1, 0 @ read ID_PFR0 for ThumbEE
422 and r0, r0, #(0xf << 12) @ ThumbEE enabled field
423 teq r0, #(1 << 12) @ check if ThumbEE is present
426 mcr p14, 6, r5, c1, c0, 0 @ Initialize TEEHBR to 0
427 mrc p14, 6, r0, c0, c0, 0 @ load TEECR
428 orr r0, r0, #1 @ set the 1st bit in order to
429 mcr p14, 6, r0, c0, c0, 0 @ stop userspace TEEHBR access
434 ARM_BE8(orr r6, r6, #1 << 25) @ big-endian page tables
435 #ifdef CONFIG_SWP_EMULATE
436 orr r5, r5, #(1 << 10) @ set SW bit in "clear"
437 bic r6, r6, #(1 << 10) @ clear it in "mmuset"
439 mrc p15, 0, r0, c1, c0, 0 @ read control register
440 bic r0, r0, r5 @ clear bits them
441 orr r0, r0, r6 @ set them
442 THUMB( orr r0, r0, #1 << 30 ) @ Thumb exceptions
443 ret lr @ return to head.S:__ret
448 .space 4 * 11 @ 11 registers
452 @ define struct processor (see <asm/proc-fns.h> and proc-macros.S)
453 define_processor_functions v7, dabort=v7_early_abort, pabort=v7_pabort, suspend=1
454 define_processor_functions ca9mp, dabort=v7_early_abort, pabort=v7_pabort, suspend=1
455 #ifdef CONFIG_CPU_PJ4B
456 define_processor_functions pj4b, dabort=v7_early_abort, pabort=v7_pabort, suspend=1
461 string cpu_arch_name, "armv7"
462 string cpu_elf_name, "v7"
465 .section ".proc.info.init", #alloc, #execinstr
468 * Standard v7 proc info content
470 .macro __v7_proc initfunc, mm_mmuflags = 0, io_mmuflags = 0, hwcaps = 0, proc_fns = v7_processor_functions
471 ALT_SMP(.long PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_SECT_AP_READ | \
472 PMD_SECT_AF | PMD_FLAGS_SMP | \mm_mmuflags)
473 ALT_UP(.long PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_SECT_AP_READ | \
474 PMD_SECT_AF | PMD_FLAGS_UP | \mm_mmuflags)
475 .long PMD_TYPE_SECT | PMD_SECT_AP_WRITE | \
476 PMD_SECT_AP_READ | PMD_SECT_AF | \io_mmuflags
480 .long HWCAP_SWP | HWCAP_HALF | HWCAP_THUMB | HWCAP_FAST_MULT | \
481 HWCAP_EDSP | HWCAP_TLS | \hwcaps
489 #ifndef CONFIG_ARM_LPAE
491 * ARM Ltd. Cortex A5 processor.
493 .type __v7_ca5mp_proc_info, #object
494 __v7_ca5mp_proc_info:
497 __v7_proc __v7_ca5mp_setup
498 .size __v7_ca5mp_proc_info, . - __v7_ca5mp_proc_info
501 * ARM Ltd. Cortex A9 processor.
503 .type __v7_ca9mp_proc_info, #object
504 __v7_ca9mp_proc_info:
507 __v7_proc __v7_ca9mp_setup, proc_fns = ca9mp_processor_functions
508 .size __v7_ca9mp_proc_info, . - __v7_ca9mp_proc_info
510 #endif /* CONFIG_ARM_LPAE */
513 * Marvell PJ4B processor.
515 #ifdef CONFIG_CPU_PJ4B
516 .type __v7_pj4b_proc_info, #object
520 __v7_proc __v7_pj4b_setup, proc_fns = pj4b_processor_functions
521 .size __v7_pj4b_proc_info, . - __v7_pj4b_proc_info
525 * ARM Ltd. Cortex R7 processor.
527 .type __v7_cr7mp_proc_info, #object
528 __v7_cr7mp_proc_info:
531 __v7_proc __v7_cr7mp_setup
532 .size __v7_cr7mp_proc_info, . - __v7_cr7mp_proc_info
535 * ARM Ltd. Cortex A7 processor.
537 .type __v7_ca7mp_proc_info, #object
538 __v7_ca7mp_proc_info:
541 __v7_proc __v7_ca7mp_setup
542 .size __v7_ca7mp_proc_info, . - __v7_ca7mp_proc_info
545 * ARM Ltd. Cortex A12 processor.
547 .type __v7_ca12mp_proc_info, #object
548 __v7_ca12mp_proc_info:
551 __v7_proc __v7_ca12mp_setup
552 .size __v7_ca12mp_proc_info, . - __v7_ca12mp_proc_info
555 * ARM Ltd. Cortex A15 processor.
557 .type __v7_ca15mp_proc_info, #object
558 __v7_ca15mp_proc_info:
561 __v7_proc __v7_ca15mp_setup
562 .size __v7_ca15mp_proc_info, . - __v7_ca15mp_proc_info
565 * Broadcom Corporation Brahma-B15 processor.
567 .type __v7_b15mp_proc_info, #object
568 __v7_b15mp_proc_info:
571 __v7_proc __v7_b15mp_setup
572 .size __v7_b15mp_proc_info, . - __v7_b15mp_proc_info
575 * ARM Ltd. Cortex A17 processor.
577 .type __v7_ca17mp_proc_info, #object
578 __v7_ca17mp_proc_info:
581 __v7_proc __v7_ca17mp_setup
582 .size __v7_ca17mp_proc_info, . - __v7_ca17mp_proc_info
585 * Qualcomm Inc. Krait processors.
587 .type __krait_proc_info, #object
589 .long 0x510f0400 @ Required ID value
590 .long 0xff0ffc00 @ Mask for ID
592 * Some Krait processors don't indicate support for SDIV and UDIV
593 * instructions in the ARM instruction set, even though they actually
594 * do support them. They also don't indicate support for fused multiply
595 * instructions even though they actually do support them.
597 __v7_proc __v7_setup, hwcaps = HWCAP_IDIV | HWCAP_VFPv4
598 .size __krait_proc_info, . - __krait_proc_info
601 * Match any ARMv7 processor core.
603 .type __v7_proc_info, #object
605 .long 0x000f0000 @ Required ID value
606 .long 0x000f0000 @ Mask for ID
608 .size __v7_proc_info, . - __v7_proc_info