2 * linux/arch/arm/mm/proc-v7.S
4 * Copyright (C) 2001 Deep Blue Solutions Ltd.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 * This is the "shell" of the ARMv7 processor support.
12 #include <linux/init.h>
13 #include <linux/linkage.h>
14 #include <asm/assembler.h>
15 #include <asm/asm-offsets.h>
16 #include <asm/hwcap.h>
17 #include <asm/pgtable-hwdef.h>
18 #include <asm/pgtable.h>
20 #include "proc-macros.S"
22 #ifdef CONFIG_ARM_LPAE
23 #include "proc-v7-3level.S"
25 #include "proc-v7-2level.S"
28 ENTRY(cpu_v7_proc_init)
30 ENDPROC(cpu_v7_proc_init)
32 ENTRY(cpu_v7_proc_fin)
33 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
34 bic r0, r0, #0x1000 @ ...i............
35 bic r0, r0, #0x0006 @ .............ca.
36 mcr p15, 0, r0, c1, c0, 0 @ disable caches
38 ENDPROC(cpu_v7_proc_fin)
43 * Perform a soft reset of the system. Put the CPU into the
44 * same state as it would be if it had been reset, and branch
45 * to what would be the reset vector.
47 * - loc - location to jump to for soft reset
49 * This code must be executed using a flat identity mapping with
53 .pushsection .idmap.text, "ax"
55 mrc p15, 0, r1, c1, c0, 0 @ ctrl register
56 bic r1, r1, #0x1 @ ...............m
57 THUMB( bic r1, r1, #1 << 30 ) @ SCTLR.TE (Thumb exceptions)
58 mcr p15, 0, r1, c1, c0, 0 @ disable MMU
67 * Idle the processor (eg, wait for interrupt).
69 * IRQs are already disabled.
72 dsb @ WFI may enter a low-power mode
75 ENDPROC(cpu_v7_do_idle)
77 ENTRY(cpu_v7_dcache_clean_area)
78 ALT_SMP(W(nop)) @ MP extensions imply L1 PTW
81 1: dcache_line_size r2, r3
82 2: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
88 ENDPROC(cpu_v7_dcache_clean_area)
90 string cpu_v7_name, "ARMv7 Processor"
93 /* Suspend/resume support: derived from arch/arm/mach-s5pv210/sleep.S */
94 .globl cpu_v7_suspend_size
95 .equ cpu_v7_suspend_size, 4 * 8
96 #ifdef CONFIG_ARM_CPU_SUSPEND
97 ENTRY(cpu_v7_do_suspend)
98 stmfd sp!, {r4 - r10, lr}
99 mrc p15, 0, r4, c13, c0, 0 @ FCSE/PID
100 mrc p15, 0, r5, c13, c0, 3 @ User r/o thread ID
102 mrc p15, 0, r6, c3, c0, 0 @ Domain ID
103 mrc p15, 0, r7, c2, c0, 1 @ TTB 1
104 mrc p15, 0, r11, c2, c0, 2 @ TTB control register
105 mrc p15, 0, r8, c1, c0, 0 @ Control register
106 mrc p15, 0, r9, c1, c0, 1 @ Auxiliary control register
107 mrc p15, 0, r10, c1, c0, 2 @ Co-processor access control
109 ldmfd sp!, {r4 - r10, pc}
110 ENDPROC(cpu_v7_do_suspend)
112 ENTRY(cpu_v7_do_resume)
114 mcr p15, 0, ip, c8, c7, 0 @ invalidate TLBs
115 mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache
116 mcr p15, 0, ip, c13, c0, 1 @ set reserved context ID
118 mcr p15, 0, r4, c13, c0, 0 @ FCSE/PID
119 mcr p15, 0, r5, c13, c0, 3 @ User r/o thread ID
121 mcr p15, 0, r6, c3, c0, 0 @ Domain ID
122 #ifndef CONFIG_ARM_LPAE
123 ALT_SMP(orr r1, r1, #TTB_FLAGS_SMP)
124 ALT_UP(orr r1, r1, #TTB_FLAGS_UP)
126 mcr p15, 0, r1, c2, c0, 0 @ TTB 0
127 mcr p15, 0, r7, c2, c0, 1 @ TTB 1
128 mcr p15, 0, r11, c2, c0, 2 @ TTB control register
129 mrc p15, 0, r4, c1, c0, 1 @ Read Auxiliary control register
130 teq r4, r9 @ Is it already set?
131 mcrne p15, 0, r9, c1, c0, 1 @ No, so write it
132 mcr p15, 0, r10, c1, c0, 2 @ Co-processor access control
135 mcr p15, 0, r4, c10, c2, 0 @ write PRRR
136 mcr p15, 0, r5, c10, c2, 1 @ write NMRR
139 mov r0, r8 @ control register
141 ENDPROC(cpu_v7_do_resume)
144 #ifdef CONFIG_CPU_PJ4B
145 globl_equ cpu_pj4b_switch_mm, cpu_v7_switch_mm
146 globl_equ cpu_pj4b_set_pte_ext, cpu_v7_set_pte_ext
147 globl_equ cpu_pj4b_proc_init, cpu_v7_proc_init
148 globl_equ cpu_pj4b_proc_fin, cpu_v7_proc_fin
149 globl_equ cpu_pj4b_reset, cpu_v7_reset
150 #ifdef CONFIG_PJ4B_ERRATA_4742
151 ENTRY(cpu_pj4b_do_idle)
152 dsb @ WFI may enter a low-power mode
156 ENDPROC(cpu_pj4b_do_idle)
158 globl_equ cpu_pj4b_do_idle, cpu_v7_do_idle
160 globl_equ cpu_pj4b_dcache_clean_area, cpu_v7_dcache_clean_area
161 globl_equ cpu_pj4b_do_suspend, cpu_v7_do_suspend
162 globl_equ cpu_pj4b_do_resume, cpu_v7_do_resume
163 globl_equ cpu_pj4b_suspend_size, cpu_v7_suspend_size
172 * Initialise TLB, Caches, and MMU state ready to switch the MMU
173 * on. Return in r0 the new CP15 C1 control register setting.
175 * This should be able to cover all ARMv7 cores.
177 * It is assumed that:
178 * - cache type register is implemented
182 mov r10, #(1 << 0) @ TLB ops broadcasting
190 ALT_SMP(mrc p15, 0, r0, c1, c0, 1)
191 ALT_UP(mov r0, #(1 << 6)) @ fake it for UP
192 tst r0, #(1 << 6) @ SMP/nAMP mode enabled?
193 orreq r0, r0, #(1 << 6) @ Enable SMP/nAMP mode
194 orreq r0, r0, r10 @ Enable CPU-specific SMP bits
195 mcreq p15, 0, r0, c1, c0, 1
200 #ifdef CONFIG_CPU_PJ4B
202 /* Auxiliary Debug Modes Control 1 Register */
203 #define PJ4B_STATIC_BP (1 << 2) /* Enable Static BP */
204 #define PJ4B_INTER_PARITY (1 << 8) /* Disable Internal Parity Handling */
205 #define PJ4B_CLEAN_LINE (1 << 16) /* Disable data transfer for clean line */
207 /* Auxiliary Debug Modes Control 2 Register */
208 #define PJ4B_FAST_LDR (1 << 23) /* Disable fast LDR */
209 #define PJ4B_SNOOP_DATA (1 << 25) /* Do not interleave write and snoop data */
210 #define PJ4B_CWF (1 << 27) /* Disable Critical Word First feature */
211 #define PJ4B_OUTSDNG_NC (1 << 29) /* Disable outstanding non cacheable rqst */
212 #define PJ4B_L1_REP_RR (1 << 30) /* L1 replacement - Strict round robin */
213 #define PJ4B_AUX_DBG_CTRL2 (PJ4B_SNOOP_DATA | PJ4B_CWF |\
214 PJ4B_OUTSDNG_NC | PJ4B_L1_REP_RR)
216 /* Auxiliary Functional Modes Control Register 0 */
217 #define PJ4B_SMP_CFB (1 << 1) /* Set SMP mode. Join the coherency fabric */
218 #define PJ4B_L1_PAR_CHK (1 << 2) /* Support L1 parity checking */
219 #define PJ4B_BROADCAST_CACHE (1 << 8) /* Broadcast Cache and TLB maintenance */
221 /* Auxiliary Debug Modes Control 0 Register */
222 #define PJ4B_WFI_WFE (1 << 22) /* WFI/WFE - serve the DVM and back to idle */
224 /* Auxiliary Debug Modes Control 1 Register */
225 mrc p15, 1, r0, c15, c1, 1
226 orr r0, r0, #PJ4B_CLEAN_LINE
227 orr r0, r0, #PJ4B_INTER_PARITY
228 bic r0, r0, #PJ4B_STATIC_BP
229 mcr p15, 1, r0, c15, c1, 1
231 /* Auxiliary Debug Modes Control 2 Register */
232 mrc p15, 1, r0, c15, c1, 2
233 bic r0, r0, #PJ4B_FAST_LDR
234 orr r0, r0, #PJ4B_AUX_DBG_CTRL2
235 mcr p15, 1, r0, c15, c1, 2
237 /* Auxiliary Functional Modes Control Register 0 */
238 mrc p15, 1, r0, c15, c2, 0
240 orr r0, r0, #PJ4B_SMP_CFB
242 orr r0, r0, #PJ4B_L1_PAR_CHK
243 orr r0, r0, #PJ4B_BROADCAST_CACHE
244 mcr p15, 1, r0, c15, c2, 0
246 /* Auxiliary Debug Modes Control 0 Register */
247 mrc p15, 1, r0, c15, c1, 0
248 orr r0, r0, #PJ4B_WFI_WFE
249 mcr p15, 1, r0, c15, c1, 0
251 #endif /* CONFIG_CPU_PJ4B */
254 adr r12, __v7_setup_stack @ the local stack
255 stmia r12, {r0-r5, r7, r9, r11, lr}
256 bl v7_flush_dcache_louis
257 ldmia r12, {r0-r5, r7, r9, r11, lr}
259 mrc p15, 0, r0, c0, c0, 0 @ read main ID register
260 and r10, r0, #0xff000000 @ ARM?
263 and r5, r0, #0x00f00000 @ variant
264 and r6, r0, #0x0000000f @ revision
265 orr r6, r6, r5, lsr #20-4 @ combine variant and revision
266 ubfx r0, r0, #4, #12 @ primary part number
268 /* Cortex-A8 Errata */
269 ldr r10, =0x00000c08 @ Cortex-A8 primary part number
272 #if defined(CONFIG_ARM_ERRATA_430973) && !defined(CONFIG_ARCH_MULTIPLATFORM)
274 teq r5, #0x00100000 @ only present in r1p*
275 mrceq p15, 0, r10, c1, c0, 1 @ read aux control register
276 orreq r10, r10, #(1 << 6) @ set IBE to 1
277 mcreq p15, 0, r10, c1, c0, 1 @ write aux control register
279 #ifdef CONFIG_ARM_ERRATA_458693
280 teq r6, #0x20 @ only present in r2p0
281 mrceq p15, 0, r10, c1, c0, 1 @ read aux control register
282 orreq r10, r10, #(1 << 5) @ set L1NEON to 1
283 orreq r10, r10, #(1 << 9) @ set PLDNOP to 1
284 mcreq p15, 0, r10, c1, c0, 1 @ write aux control register
286 #ifdef CONFIG_ARM_ERRATA_460075
287 teq r6, #0x20 @ only present in r2p0
288 mrceq p15, 1, r10, c9, c0, 2 @ read L2 cache aux ctrl register
290 orreq r10, r10, #(1 << 22) @ set the Write Allocate disable bit
291 mcreq p15, 1, r10, c9, c0, 2 @ write the L2 cache aux ctrl register
295 /* Cortex-A9 Errata */
296 2: ldr r10, =0x00000c09 @ Cortex-A9 primary part number
299 #ifdef CONFIG_ARM_ERRATA_742230
300 cmp r6, #0x22 @ only present up to r2p2
301 mrcle p15, 0, r10, c15, c0, 1 @ read diagnostic register
302 orrle r10, r10, #1 << 4 @ set bit #4
303 mcrle p15, 0, r10, c15, c0, 1 @ write diagnostic register
305 #ifdef CONFIG_ARM_ERRATA_742231
306 teq r6, #0x20 @ present in r2p0
307 teqne r6, #0x21 @ present in r2p1
308 teqne r6, #0x22 @ present in r2p2
309 mrceq p15, 0, r10, c15, c0, 1 @ read diagnostic register
310 orreq r10, r10, #1 << 12 @ set bit #12
311 orreq r10, r10, #1 << 22 @ set bit #22
312 mcreq p15, 0, r10, c15, c0, 1 @ write diagnostic register
314 #ifdef CONFIG_ARM_ERRATA_743622
315 teq r5, #0x00200000 @ only present in r2p*
316 mrceq p15, 0, r10, c15, c0, 1 @ read diagnostic register
317 orreq r10, r10, #1 << 6 @ set bit #6
318 mcreq p15, 0, r10, c15, c0, 1 @ write diagnostic register
320 #if defined(CONFIG_ARM_ERRATA_751472) && defined(CONFIG_SMP)
321 ALT_SMP(cmp r6, #0x30) @ present prior to r3p0
323 mrclt p15, 0, r10, c15, c0, 1 @ read diagnostic register
324 orrlt r10, r10, #1 << 11 @ set bit #11
325 mcrlt p15, 0, r10, c15, c0, 1 @ write diagnostic register
329 /* Cortex-A12 Errata */
330 3: ldr r10, =0x00000c0d @ Cortex-A12 primary part number
333 #ifdef CONFIG_ARM_ERRATA_818325
334 teq r6, #0x00 @ present in r0p0
335 teqne r6, #0x01 @ present in r0p1-00lac0-rc11
336 mrceq p15, 0, r10, c15, c0, 1 @ read diagnostic register
337 orreq r10, r10, #1 << 12 @ set bit #12
338 mcreq p15, 0, r10, c15, c0, 1 @ write diagnostic register
343 mcr p15, 0, r10, c7, c5, 0 @ I+BTB cache invalidate
345 mcr p15, 0, r10, c8, c7, 0 @ invalidate I + D TLBs
346 v7_ttb_setup r10, r4, r8, r5 @ TTBCR, TTBRx setup
349 mcr p15, 0, r5, c10, c2, 0 @ write PRRR
350 mcr p15, 0, r6, c10, c2, 1 @ write NMRR
352 dsb @ Complete invalidations
353 #ifndef CONFIG_ARM_THUMBEE
354 mrc p15, 0, r0, c0, c1, 0 @ read ID_PFR0 for ThumbEE
355 and r0, r0, #(0xf << 12) @ ThumbEE enabled field
356 teq r0, #(1 << 12) @ check if ThumbEE is present
359 mcr p14, 6, r5, c1, c0, 0 @ Initialize TEEHBR to 0
360 mrc p14, 6, r0, c0, c0, 0 @ load TEECR
361 orr r0, r0, #1 @ set the 1st bit in order to
362 mcr p14, 6, r0, c0, c0, 0 @ stop userspace TEEHBR access
367 ARM_BE8(orr r6, r6, #1 << 25) @ big-endian page tables
368 #ifdef CONFIG_SWP_EMULATE
369 orr r5, r5, #(1 << 10) @ set SW bit in "clear"
370 bic r6, r6, #(1 << 10) @ clear it in "mmuset"
372 mrc p15, 0, r0, c1, c0, 0 @ read control register
373 bic r0, r0, r5 @ clear bits them
374 orr r0, r0, r6 @ set them
375 THUMB( orr r0, r0, #1 << 30 ) @ Thumb exceptions
376 mov pc, lr @ return to head.S:__ret
381 .space 4 * 11 @ 11 registers
385 @ define struct processor (see <asm/proc-fns.h> and proc-macros.S)
386 define_processor_functions v7, dabort=v7_early_abort, pabort=v7_pabort, suspend=1
387 #ifdef CONFIG_CPU_PJ4B
388 define_processor_functions pj4b, dabort=v7_early_abort, pabort=v7_pabort, suspend=1
393 string cpu_arch_name, "armv7"
394 string cpu_elf_name, "v7"
397 .section ".proc.info.init", #alloc, #execinstr
400 * Standard v7 proc info content
402 .macro __v7_proc initfunc, mm_mmuflags = 0, io_mmuflags = 0, hwcaps = 0, proc_fns = v7_processor_functions
403 ALT_SMP(.long PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_SECT_AP_READ | \
404 PMD_SECT_AF | PMD_FLAGS_SMP | \mm_mmuflags)
405 ALT_UP(.long PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_SECT_AP_READ | \
406 PMD_SECT_AF | PMD_FLAGS_UP | \mm_mmuflags)
407 .long PMD_TYPE_SECT | PMD_SECT_AP_WRITE | \
408 PMD_SECT_AP_READ | PMD_SECT_AF | \io_mmuflags
412 .long HWCAP_SWP | HWCAP_HALF | HWCAP_THUMB | HWCAP_FAST_MULT | \
413 HWCAP_EDSP | HWCAP_TLS | \hwcaps
421 #ifndef CONFIG_ARM_LPAE
423 * ARM Ltd. Cortex A5 processor.
425 .type __v7_ca5mp_proc_info, #object
426 __v7_ca5mp_proc_info:
429 __v7_proc __v7_ca5mp_setup
430 .size __v7_ca5mp_proc_info, . - __v7_ca5mp_proc_info
433 * ARM Ltd. Cortex A9 processor.
435 .type __v7_ca9mp_proc_info, #object
436 __v7_ca9mp_proc_info:
439 __v7_proc __v7_ca9mp_setup
440 .size __v7_ca9mp_proc_info, . - __v7_ca9mp_proc_info
442 #endif /* CONFIG_ARM_LPAE */
445 * Marvell PJ4B processor.
447 #ifdef CONFIG_CPU_PJ4B
448 .type __v7_pj4b_proc_info, #object
452 __v7_proc __v7_pj4b_setup, proc_fns = pj4b_processor_functions
453 .size __v7_pj4b_proc_info, . - __v7_pj4b_proc_info
457 * ARM Ltd. Cortex A7 processor.
459 .type __v7_ca7mp_proc_info, #object
460 __v7_ca7mp_proc_info:
463 __v7_proc __v7_ca7mp_setup
464 .size __v7_ca7mp_proc_info, . - __v7_ca7mp_proc_info
467 * ARM Ltd. Cortex A12 processor.
469 .type __v7_ca12mp_proc_info, #object
470 __v7_ca12mp_proc_info:
473 __v7_proc __v7_ca12mp_setup
474 .size __v7_ca12mp_proc_info, . - __v7_ca12mp_proc_info
477 * ARM Ltd. Cortex A15 processor.
479 .type __v7_ca15mp_proc_info, #object
480 __v7_ca15mp_proc_info:
483 __v7_proc __v7_ca15mp_setup
484 .size __v7_ca15mp_proc_info, . - __v7_ca15mp_proc_info
487 * Qualcomm Inc. Krait processors.
489 .type __krait_proc_info, #object
491 .long 0x510f0400 @ Required ID value
492 .long 0xff0ffc00 @ Mask for ID
494 * Some Krait processors don't indicate support for SDIV and UDIV
495 * instructions in the ARM instruction set, even though they actually
498 __v7_proc __v7_setup, hwcaps = HWCAP_IDIV
499 .size __krait_proc_info, . - __krait_proc_info
502 * Match any ARMv7 processor core.
504 .type __v7_proc_info, #object
506 .long 0x000f0000 @ Required ID value
507 .long 0x000f0000 @ Mask for ID
509 .size __v7_proc_info, . - __v7_proc_info