arch/arm/mm/mmu.c

   1 /*
   2  *  linux/arch/arm/mm/mmu.c
   3  *
   4  *  Copyright (C) 1995-2005 Russell King
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  */
  10 #include <linux/module.h>
  11 #include <linux/kernel.h>
  12 #include <linux/errno.h>
  13 #include <linux/init.h>
  14 #include <linux/mman.h>
  15 #include <linux/nodemask.h>
  16 #include <linux/memblock.h>
  17 #include <linux/fs.h>
  18 #include <linux/vmalloc.h>
  19 #include <linux/sizes.h>
  20
  21 #include <asm/cp15.h>
  22 #include <asm/cputype.h>
  23 #include <asm/sections.h>
  24 #include <asm/cachetype.h>
  25 #include <asm/setup.h>
  26 #include <asm/smp_plat.h>
  27 #include <asm/tlb.h>
  28 #include <asm/highmem.h>
  29 #include <asm/system_info.h>
  30 #include <asm/traps.h>
  31
  32 #include <asm/mach/arch.h>
  33 #include <asm/mach/map.h>
  34 #include <asm/mach/pci.h>
  35
  36 #include "mm.h"
  37 #include "tcm.h"
  38
  39 /*
  40  * empty_zero_page is a special page that is used for
  41  * zero-initialized data and COW.
  42  */
  43 struct page *empty_zero_page;
  44 EXPORT_SYMBOL(empty_zero_page);
  45
  46 /*
  47  * The pmd table for the upper-most set of pages.
  48  */
  49 pmd_t *top_pmd;
  50
  51 #define CPOLICY_UNCACHED        0
  52 #define CPOLICY_BUFFERED        1
  53 #define CPOLICY_WRITETHROUGH    2
  54 #define CPOLICY_WRITEBACK       3
  55 #define CPOLICY_WRITEALLOC      4
  56
  57 static unsigned int cachepolicy __initdata = CPOLICY_WRITEBACK;
  58 static unsigned int ecc_mask __initdata = 0;
  59 pgprot_t pgprot_user;
  60 pgprot_t pgprot_kernel;
  61 pgprot_t pgprot_hyp_device;
  62 pgprot_t pgprot_s2;
  63 pgprot_t pgprot_s2_device;
  64
  65 EXPORT_SYMBOL(pgprot_user);
  66 EXPORT_SYMBOL(pgprot_kernel);
  67
  68 struct cachepolicy {
  69         const char      policy[16];
  70         unsigned int    cr_mask;
  71         pmdval_t        pmd;
  72         pteval_t        pte;
  73         pteval_t        pte_s2;
  74 };
  75
  76 #ifdef CONFIG_ARM_LPAE
  77 #define s2_policy(policy)       policy
  78 #else
  79 #define s2_policy(policy)       0
  80 #endif
  81
  82 static struct cachepolicy cache_policies[] __initdata = {
  83         {
  84                 .policy         = "uncached",
  85                 .cr_mask        = CR_W|CR_C,
  86                 .pmd            = PMD_SECT_UNCACHED,
  87                 .pte            = L_PTE_MT_UNCACHED,
  88                 .pte_s2         = s2_policy(L_PTE_S2_MT_UNCACHED),
  89         }, {
  90                 .policy         = "buffered",
  91                 .cr_mask        = CR_C,
  92                 .pmd            = PMD_SECT_BUFFERED,
  93                 .pte            = L_PTE_MT_BUFFERABLE,
  94                 .pte_s2         = s2_policy(L_PTE_S2_MT_UNCACHED),
  95         }, {
  96                 .policy         = "writethrough",
  97                 .cr_mask        = 0,
  98                 .pmd            = PMD_SECT_WT,
  99                 .pte            = L_PTE_MT_WRITETHROUGH,
 100                 .pte_s2         = s2_policy(L_PTE_S2_MT_WRITETHROUGH),
 101         }, {
 102                 .policy         = "writeback",
 103                 .cr_mask        = 0,
 104                 .pmd            = PMD_SECT_WB,
 105                 .pte            = L_PTE_MT_WRITEBACK,
 106                 .pte_s2         = s2_policy(L_PTE_S2_MT_WRITEBACK),
 107         }, {
 108                 .policy         = "writealloc",
 109                 .cr_mask        = 0,
 110                 .pmd            = PMD_SECT_WBWA,
 111                 .pte            = L_PTE_MT_WRITEALLOC,
 112                 .pte_s2         = s2_policy(L_PTE_S2_MT_WRITEBACK),
 113         }
 114 };
 115
 116 #ifdef CONFIG_CPU_CP15
 117 /*
 118  * These are useful for identifying cache coherency
 119  * problems by allowing the cache or the cache and
 120  * writebuffer to be turned off.  (Note: the write
 121  * buffer should not be on and the cache off).
 122  */
 123 static int __init early_cachepolicy(char *p)
 124 {
 125         int i;
 126
 127         for (i = 0; i < ARRAY_SIZE(cache_policies); i++) {
 128                 int len = strlen(cache_policies[i].policy);
 129
 130                 if (memcmp(p, cache_policies[i].policy, len) == 0) {
 131                         cachepolicy = i;
 132                         cr_alignment &= ~cache_policies[i].cr_mask;
 133                         cr_no_alignment &= ~cache_policies[i].cr_mask;
 134                         break;
 135                 }
 136         }
 137         if (i == ARRAY_SIZE(cache_policies))
 138                 printk(KERN_ERR "ERROR: unknown or unsupported cache policy\n");
 139         /*
 140          * This restriction is partly to do with the way we boot; it is
 141          * unpredictable to have memory mapped using two different sets of
 142          * memory attributes (shared, type, and cache attribs).  We can not
 143          * change these attributes once the initial assembly has setup the
 144          * page tables.
 145          */
 146         if (cpu_architecture() >= CPU_ARCH_ARMv6) {
 147                 printk(KERN_WARNING "Only cachepolicy=writeback supported on ARMv6 and later\n");
 148                 cachepolicy = CPOLICY_WRITEBACK;
 149         }
 150         flush_cache_all();
 151         set_cr(cr_alignment);
 152         return 0;
 153 }
 154 early_param("cachepolicy", early_cachepolicy);
 155
 156 static int __init early_nocache(char *__unused)
 157 {
 158         char *p = "buffered";
 159         printk(KERN_WARNING "nocache is deprecated; use cachepolicy=%s\n", p);
 160         early_cachepolicy(p);
 161         return 0;
 162 }
 163 early_param("nocache", early_nocache);
 164
 165 static int __init early_nowrite(char *__unused)
 166 {
 167         char *p = "uncached";
 168         printk(KERN_WARNING "nowb is deprecated; use cachepolicy=%s\n", p);
 169         early_cachepolicy(p);
 170         return 0;
 171 }
 172 early_param("nowb", early_nowrite);
 173
 174 #ifndef CONFIG_ARM_LPAE
 175 static int __init early_ecc(char *p)
 176 {
 177         if (memcmp(p, "on", 2) == 0)
 178                 ecc_mask = PMD_PROTECTION;
 179         else if (memcmp(p, "off", 3) == 0)
 180                 ecc_mask = 0;
 181         return 0;
 182 }
 183 early_param("ecc", early_ecc);
 184 #endif
 185
 186 static int __init noalign_setup(char *__unused)
 187 {
 188         cr_alignment &= ~CR_A;
 189         cr_no_alignment &= ~CR_A;
 190         set_cr(cr_alignment);
 191         return 1;
 192 }
 193 __setup("noalign", noalign_setup);
 194
 195 #ifndef CONFIG_SMP
 196 void adjust_cr(unsigned long mask, unsigned long set)
 197 {
 198         unsigned long flags;
 199
 200         mask &= ~CR_A;
 201
 202         set &= mask;
 203
 204         local_irq_save(flags);
 205
 206         cr_no_alignment = (cr_no_alignment & ~mask) | set;
 207         cr_alignment = (cr_alignment & ~mask) | set;
 208
 209         set_cr((get_cr() & ~mask) | set);
 210
 211         local_irq_restore(flags);
 212 }
 213 #endif
 214
 215 #else /* ifdef CONFIG_CPU_CP15 */
 216
 217 static int __init early_cachepolicy(char *p)
 218 {
 219         pr_warning("cachepolicy kernel parameter not supported without cp15\n");
 220 }
 221 early_param("cachepolicy", early_cachepolicy);
 222
 223 static int __init noalign_setup(char *__unused)
 224 {
 225         pr_warning("noalign kernel parameter not supported without cp15\n");
 226 }
 227 __setup("noalign", noalign_setup);
 228
 229 #endif /* ifdef CONFIG_CPU_CP15 / else */
 230
 231 #define PROT_PTE_DEVICE         L_PTE_PRESENT|L_PTE_YOUNG|L_PTE_DIRTY|L_PTE_XN
 232 #define PROT_SECT_DEVICE        PMD_TYPE_SECT|PMD_SECT_AP_WRITE
 233
 234 static struct mem_type mem_types[] = {
 235         [MT_DEVICE] = {           /* Strongly ordered / ARMv6 shared device */
 236                 .prot_pte       = PROT_PTE_DEVICE | L_PTE_MT_DEV_SHARED |
 237                                   L_PTE_SHARED,
 238                 .prot_l1        = PMD_TYPE_TABLE,
 239                 .prot_sect      = PROT_SECT_DEVICE | PMD_SECT_S,
 240                 .domain         = DOMAIN_IO,
 241         },
 242         [MT_DEVICE_NONSHARED] = { /* ARMv6 non-shared device */
 243                 .prot_pte       = PROT_PTE_DEVICE | L_PTE_MT_DEV_NONSHARED,
 244                 .prot_l1        = PMD_TYPE_TABLE,
 245                 .prot_sect      = PROT_SECT_DEVICE,
 246                 .domain         = DOMAIN_IO,
 247         },
 248         [MT_DEVICE_CACHED] = {    /* ioremap_cached */
 249                 .prot_pte       = PROT_PTE_DEVICE | L_PTE_MT_DEV_CACHED,
 250                 .prot_l1        = PMD_TYPE_TABLE,
 251                 .prot_sect      = PROT_SECT_DEVICE | PMD_SECT_WB,
 252                 .domain         = DOMAIN_IO,
 253         },
 254         [MT_DEVICE_WC] = {      /* ioremap_wc */
 255                 .prot_pte       = PROT_PTE_DEVICE | L_PTE_MT_DEV_WC,
 256                 .prot_l1        = PMD_TYPE_TABLE,
 257                 .prot_sect      = PROT_SECT_DEVICE,
 258                 .domain         = DOMAIN_IO,
 259         },
 260         [MT_UNCACHED] = {
 261                 .prot_pte       = PROT_PTE_DEVICE,
 262                 .prot_l1        = PMD_TYPE_TABLE,
 263                 .prot_sect      = PMD_TYPE_SECT | PMD_SECT_XN,
 264                 .domain         = DOMAIN_IO,
 265         },
 266         [MT_CACHECLEAN] = {
 267                 .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN,
 268                 .domain    = DOMAIN_KERNEL,
 269         },
 270 #ifndef CONFIG_ARM_LPAE
 271         [MT_MINICLEAN] = {
 272                 .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN | PMD_SECT_MINICACHE,
 273                 .domain    = DOMAIN_KERNEL,
 274         },
 275 #endif
 276         [MT_LOW_VECTORS] = {
 277                 .prot_pte  = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
 278                                 L_PTE_RDONLY,
 279                 .prot_l1   = PMD_TYPE_TABLE,
 280                 .domain    = DOMAIN_USER,
 281         },
 282         [MT_HIGH_VECTORS] = {
 283                 .prot_pte  = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
 284                                 L_PTE_USER | L_PTE_RDONLY,
 285                 .prot_l1   = PMD_TYPE_TABLE,
 286                 .domain    = DOMAIN_USER,
 287         },
 288         [MT_MEMORY] = {
 289                 .prot_pte  = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY,
 290                 .prot_l1   = PMD_TYPE_TABLE,
 291                 .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE,
 292                 .domain    = DOMAIN_KERNEL,
 293         },
 294         [MT_ROM] = {
 295                 .prot_sect = PMD_TYPE_SECT,
 296                 .domain    = DOMAIN_KERNEL,
 297         },
 298         [MT_MEMORY_NONCACHED] = {
 299                 .prot_pte  = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
 300                                 L_PTE_MT_BUFFERABLE,
 301                 .prot_l1   = PMD_TYPE_TABLE,
 302                 .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE,
 303                 .domain    = DOMAIN_KERNEL,
 304         },
 305         [MT_MEMORY_DTCM] = {
 306                 .prot_pte  = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
 307                                 L_PTE_XN,
 308                 .prot_l1   = PMD_TYPE_TABLE,
 309                 .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN,
 310                 .domain    = DOMAIN_KERNEL,
 311         },
 312         [MT_MEMORY_ITCM] = {
 313                 .prot_pte  = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY,
 314                 .prot_l1   = PMD_TYPE_TABLE,
 315                 .domain    = DOMAIN_KERNEL,
 316         },
 317         [MT_MEMORY_SO] = {
 318                 .prot_pte  = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
 319                                 L_PTE_MT_UNCACHED | L_PTE_XN,
 320                 .prot_l1   = PMD_TYPE_TABLE,
 321                 .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_SECT_S |
 322                                 PMD_SECT_UNCACHED | PMD_SECT_XN,
 323                 .domain    = DOMAIN_KERNEL,
 324         },
 325         [MT_MEMORY_DMA_READY] = {
 326                 .prot_pte  = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY,
 327                 .prot_l1   = PMD_TYPE_TABLE,
 328                 .domain    = DOMAIN_KERNEL,
 329         },
 330 };
 331
 332 const struct mem_type *get_mem_type(unsigned int type)
 333 {
 334         return type < ARRAY_SIZE(mem_types) ? &mem_types[type] : NULL;
 335 }
 336 EXPORT_SYMBOL(get_mem_type);
 337
 338 /*
 339  * Adjust the PMD section entries according to the CPU in use.
 340  */
 341 static void __init build_mem_type_table(void)
 342 {
 343         struct cachepolicy *cp;
 344         unsigned int cr = get_cr();
 345         pteval_t user_pgprot, kern_pgprot, vecs_pgprot;
 346         pteval_t hyp_device_pgprot, s2_pgprot, s2_device_pgprot;
 347         int cpu_arch = cpu_architecture();
 348         int i;
 349
 350         if (cpu_arch < CPU_ARCH_ARMv6) {
 351 #if defined(CONFIG_CPU_DCACHE_DISABLE)
 352                 if (cachepolicy > CPOLICY_BUFFERED)
 353                         cachepolicy = CPOLICY_BUFFERED;
 354 #elif defined(CONFIG_CPU_DCACHE_WRITETHROUGH)
 355                 if (cachepolicy > CPOLICY_WRITETHROUGH)
 356                         cachepolicy = CPOLICY_WRITETHROUGH;
 357 #endif
 358         }
 359         if (cpu_arch < CPU_ARCH_ARMv5) {
 360                 if (cachepolicy >= CPOLICY_WRITEALLOC)
 361                         cachepolicy = CPOLICY_WRITEBACK;
 362                 ecc_mask = 0;
 363         }
 364         if (is_smp())
 365                 cachepolicy = CPOLICY_WRITEALLOC;
 366
 367         /*
 368          * Strip out features not present on earlier architectures.
 369          * Pre-ARMv5 CPUs don't have TEX bits.  Pre-ARMv6 CPUs or those
 370          * without extended page tables don't have the 'Shared' bit.
 371          */
 372         if (cpu_arch < CPU_ARCH_ARMv5)
 373                 for (i = 0; i < ARRAY_SIZE(mem_types); i++)
 374                         mem_types[i].prot_sect &= ~PMD_SECT_TEX(7);
 375         if ((cpu_arch < CPU_ARCH_ARMv6 || !(cr & CR_XP)) && !cpu_is_xsc3())
 376                 for (i = 0; i < ARRAY_SIZE(mem_types); i++)
 377                         mem_types[i].prot_sect &= ~PMD_SECT_S;
 378
 379         /*
 380          * ARMv5 and lower, bit 4 must be set for page tables (was: cache
 381          * "update-able on write" bit on ARM610).  However, Xscale and
 382          * Xscale3 require this bit to be cleared.
 383          */
 384         if (cpu_is_xscale() || cpu_is_xsc3()) {
 385                 for (i = 0; i < ARRAY_SIZE(mem_types); i++) {
 386                         mem_types[i].prot_sect &= ~PMD_BIT4;
 387                         mem_types[i].prot_l1 &= ~PMD_BIT4;
 388                 }
 389         } else if (cpu_arch < CPU_ARCH_ARMv6) {
 390                 for (i = 0; i < ARRAY_SIZE(mem_types); i++) {
 391                         if (mem_types[i].prot_l1)
 392                                 mem_types[i].prot_l1 |= PMD_BIT4;
 393                         if (mem_types[i].prot_sect)
 394                                 mem_types[i].prot_sect |= PMD_BIT4;
 395                 }
 396         }
 397
 398         /*
 399          * Mark the device areas according to the CPU/architecture.
 400          */
 401         if (cpu_is_xsc3() || (cpu_arch >= CPU_ARCH_ARMv6 && (cr & CR_XP))) {
 402                 if (!cpu_is_xsc3()) {
 403                         /*
 404                          * Mark device regions on ARMv6+ as execute-never
 405                          * to prevent speculative instruction fetches.
 406                          */
 407                         mem_types[MT_DEVICE].prot_sect |= PMD_SECT_XN;
 408                         mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_XN;
 409                         mem_types[MT_DEVICE_CACHED].prot_sect |= PMD_SECT_XN;
 410                         mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_XN;
 411                 }
 412                 if (cpu_arch >= CPU_ARCH_ARMv7 && (cr & CR_TRE)) {
 413                         /*
 414                          * For ARMv7 with TEX remapping,
 415                          * - shared device is SXCB=1100
 416                          * - nonshared device is SXCB=0100
 417                          * - write combine device mem is SXCB=0001
 418                          * (Uncached Normal memory)
 419                          */
 420                         mem_types[MT_DEVICE].prot_sect |= PMD_SECT_TEX(1);
 421                         mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_TEX(1);
 422                         mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_BUFFERABLE;
 423                 } else if (cpu_is_xsc3()) {
 424                         /*
 425                          * For Xscale3,
 426                          * - shared device is TEXCB=00101
 427                          * - nonshared device is TEXCB=01000
 428                          * - write combine device mem is TEXCB=00100
 429                          * (Inner/Outer Uncacheable in xsc3 parlance)
 430                          */
 431                         mem_types[MT_DEVICE].prot_sect |= PMD_SECT_TEX(1) | PMD_SECT_BUFFERED;
 432                         mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_TEX(2);
 433                         mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_TEX(1);
 434                 } else {
 435                         /*
 436                          * For ARMv6 and ARMv7 without TEX remapping,
 437                          * - shared device is TEXCB=00001
 438                          * - nonshared device is TEXCB=01000
 439                          * - write combine device mem is TEXCB=00100
 440                          * (Uncached Normal in ARMv6 parlance).
 441                          */
 442                         mem_types[MT_DEVICE].prot_sect |= PMD_SECT_BUFFERED;
 443                         mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_TEX(2);
 444                         mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_TEX(1);
 445                 }
 446         } else {
 447                 /*
 448                  * On others, write combining is "Uncached/Buffered"
 449                  */
 450                 mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_BUFFERABLE;
 451         }
 452
 453         /*
 454          * Now deal with the memory-type mappings
 455          */
 456         cp = &cache_policies[cachepolicy];
 457         vecs_pgprot = kern_pgprot = user_pgprot = cp->pte;
 458         s2_pgprot = cp->pte_s2;
 459         hyp_device_pgprot = s2_device_pgprot = mem_types[MT_DEVICE].prot_pte;
 460
 461         /*
 462          * We don't use domains on ARMv6 (since this causes problems with
 463          * v6/v7 kernels), so we must use a separate memory type for user
 464          * r/o, kernel r/w to map the vectors page.
 465          */
 466 #ifndef CONFIG_ARM_LPAE
 467         if (cpu_arch == CPU_ARCH_ARMv6)
 468                 vecs_pgprot |= L_PTE_MT_VECTORS;
 469 #endif
 470
 471         /*
 472          * ARMv6 and above have extended page tables.
 473          */
 474         if (cpu_arch >= CPU_ARCH_ARMv6 && (cr & CR_XP)) {
 475 #ifndef CONFIG_ARM_LPAE
 476                 /*
 477                  * Mark cache clean areas and XIP ROM read only
 478                  * from SVC mode and no access from userspace.
 479                  */
 480                 mem_types[MT_ROM].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE;
 481                 mem_types[MT_MINICLEAN].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE;
 482                 mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE;
 483 #endif
 484
 485                 if (is_smp()) {
 486                         /*
 487                          * Mark memory with the "shared" attribute
 488                          * for SMP systems
 489                          */
 490                         user_pgprot |= L_PTE_SHARED;
 491                         kern_pgprot |= L_PTE_SHARED;
 492                         vecs_pgprot |= L_PTE_SHARED;
 493                         s2_pgprot |= L_PTE_SHARED;
 494                         mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_S;
 495                         mem_types[MT_DEVICE_WC].prot_pte |= L_PTE_SHARED;
 496                         mem_types[MT_DEVICE_CACHED].prot_sect |= PMD_SECT_S;
 497                         mem_types[MT_DEVICE_CACHED].prot_pte |= L_PTE_SHARED;
 498                         mem_types[MT_MEMORY].prot_sect |= PMD_SECT_S;
 499                         mem_types[MT_MEMORY].prot_pte |= L_PTE_SHARED;
 500                         mem_types[MT_MEMORY_DMA_READY].prot_pte |= L_PTE_SHARED;
 501                         mem_types[MT_MEMORY_NONCACHED].prot_sect |= PMD_SECT_S;
 502                         mem_types[MT_MEMORY_NONCACHED].prot_pte |= L_PTE_SHARED;
 503                 }
 504         }
 505
 506         /*
 507          * Non-cacheable Normal - intended for memory areas that must
 508          * not cause dirty cache line writebacks when used
 509          */
 510         if (cpu_arch >= CPU_ARCH_ARMv6) {
 511                 if (cpu_arch >= CPU_ARCH_ARMv7 && (cr & CR_TRE)) {
 512                         /* Non-cacheable Normal is XCB = 001 */
 513                         mem_types[MT_MEMORY_NONCACHED].prot_sect |=
 514                                 PMD_SECT_BUFFERED;
 515                 } else {
 516                         /* For both ARMv6 and non-TEX-remapping ARMv7 */
 517                         mem_types[MT_MEMORY_NONCACHED].prot_sect |=
 518                                 PMD_SECT_TEX(1);
 519                 }
 520         } else {
 521                 mem_types[MT_MEMORY_NONCACHED].prot_sect |= PMD_SECT_BUFFERABLE;
 522         }
 523
 524 #ifdef CONFIG_ARM_LPAE
 525         /*
 526          * Do not generate access flag faults for the kernel mappings.
 527          */
 528         for (i = 0; i < ARRAY_SIZE(mem_types); i++) {
 529                 mem_types[i].prot_pte |= PTE_EXT_AF;
 530                 if (mem_types[i].prot_sect)
 531                         mem_types[i].prot_sect |= PMD_SECT_AF;
 532         }
 533         kern_pgprot |= PTE_EXT_AF;
 534         vecs_pgprot |= PTE_EXT_AF;
 535 #endif
 536
 537         for (i = 0; i < 16; i++) {
 538                 pteval_t v = pgprot_val(protection_map[i]);
 539                 protection_map[i] = __pgprot(v | user_pgprot);
 540         }
 541
 542         mem_types[MT_LOW_VECTORS].prot_pte |= vecs_pgprot;
 543         mem_types[MT_HIGH_VECTORS].prot_pte |= vecs_pgprot;
 544
 545         pgprot_user   = __pgprot(L_PTE_PRESENT | L_PTE_YOUNG | user_pgprot);
 546         pgprot_kernel = __pgprot(L_PTE_PRESENT | L_PTE_YOUNG |
 547                                  L_PTE_DIRTY | kern_pgprot);
 548         pgprot_s2  = __pgprot(L_PTE_PRESENT | L_PTE_YOUNG | s2_pgprot);
 549         pgprot_s2_device  = __pgprot(s2_device_pgprot);
 550         pgprot_hyp_device  = __pgprot(hyp_device_pgprot);
 551
 552         mem_types[MT_LOW_VECTORS].prot_l1 |= ecc_mask;
 553         mem_types[MT_HIGH_VECTORS].prot_l1 |= ecc_mask;
 554         mem_types[MT_MEMORY].prot_sect |= ecc_mask | cp->pmd;
 555         mem_types[MT_MEMORY].prot_pte |= kern_pgprot;
 556         mem_types[MT_MEMORY_DMA_READY].prot_pte |= kern_pgprot;
 557         mem_types[MT_MEMORY_NONCACHED].prot_sect |= ecc_mask;
 558         mem_types[MT_ROM].prot_sect |= cp->pmd;
 559
 560         switch (cp->pmd) {
 561         case PMD_SECT_WT:
 562                 mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_WT;
 563                 break;
 564         case PMD_SECT_WB:
 565         case PMD_SECT_WBWA:
 566                 mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_WB;
 567                 break;
 568         }
 569         printk("Memory policy: ECC %sabled, Data cache %s\n",
 570                 ecc_mask ? "en" : "dis", cp->policy);
 571
 572         for (i = 0; i < ARRAY_SIZE(mem_types); i++) {
 573                 struct mem_type *t = &mem_types[i];
 574                 if (t->prot_l1)
 575                         t->prot_l1 |= PMD_DOMAIN(t->domain);
 576                 if (t->prot_sect)
 577                         t->prot_sect |= PMD_DOMAIN(t->domain);
 578         }
 579 }
 580
 581 #ifdef CONFIG_ARM_DMA_MEM_BUFFERABLE
 582 pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn,
 583                               unsigned long size, pgprot_t vma_prot)
 584 {
 585         if (!pfn_valid(pfn))
 586                 return pgprot_noncached(vma_prot);
 587         else if (file->f_flags & O_SYNC)
 588                 return pgprot_writecombine(vma_prot);
 589         return vma_prot;
 590 }
 591 EXPORT_SYMBOL(phys_mem_access_prot);
 592 #endif
 593
 594 #define vectors_base()  (vectors_high() ? 0xffff0000 : 0)
 595
 596 static void __init *early_alloc_aligned(unsigned long sz, unsigned long align)
 597 {
 598         void *ptr = __va(memblock_alloc(sz, align));
 599         memset(ptr, 0, sz);
 600         return ptr;
 601 }
 602
 603 static void __init *early_alloc(unsigned long sz)
 604 {
 605         return early_alloc_aligned(sz, sz);
 606 }
 607
 608 static pte_t * __init early_pte_alloc(pmd_t *pmd, unsigned long addr, unsigned long prot)
 609 {
 610         if (pmd_none(*pmd)) {
 611                 pte_t *pte = early_alloc(PTE_HWTABLE_OFF + PTE_HWTABLE_SIZE);
 612                 __pmd_populate(pmd, __pa(pte), prot);
 613         }
 614         BUG_ON(pmd_bad(*pmd));
 615         return pte_offset_kernel(pmd, addr);
 616 }
 617
 618 static void __init alloc_init_pte(pmd_t *pmd, unsigned long addr,
 619                                   unsigned long end, unsigned long pfn,
 620                                   const struct mem_type *type)
 621 {
 622         pte_t *pte = early_pte_alloc(pmd, addr, type->prot_l1);
 623         do {
 624                 set_pte_ext(pte, pfn_pte(pfn, __pgprot(type->prot_pte)), 0);
 625                 pfn++;
 626         } while (pte++, addr += PAGE_SIZE, addr != end);
 627 }
 628
 629 static void __init __map_init_section(pmd_t *pmd, unsigned long addr,
 630                         unsigned long end, phys_addr_t phys,
 631                         const struct mem_type *type)
 632 {
 633         pmd_t *p = pmd;
 634
 635 #ifndef CONFIG_ARM_LPAE
 636         /*
 637          * In classic MMU format, puds and pmds are folded in to
 638          * the pgds. pmd_offset gives the PGD entry. PGDs refer to a
 639          * group of L1 entries making up one logical pointer to
 640          * an L2 table (2MB), where as PMDs refer to the individual
 641          * L1 entries (1MB). Hence increment to get the correct
 642          * offset for odd 1MB sections.
 643          * (See arch/arm/include/asm/pgtable-2level.h)
 644          */
 645         if (addr & SECTION_SIZE)
 646                 pmd++;
 647 #endif
 648         do {
 649                 *pmd = __pmd(phys | type->prot_sect);
 650                 phys += SECTION_SIZE;
 651         } while (pmd++, addr += SECTION_SIZE, addr != end);
 652
 653         flush_pmd_entry(p);
 654 }
 655
 656 static void __init alloc_init_pmd(pud_t *pud, unsigned long addr,
 657                                       unsigned long end, phys_addr_t phys,
 658                                       const struct mem_type *type)
 659 {
 660         pmd_t *pmd = pmd_offset(pud, addr);
 661         unsigned long next;
 662
 663         do {
 664                 /*
 665                  * With LPAE, we must loop over to map
 666                  * all the pmds for the given range.
 667                  */
 668                 next = pmd_addr_end(addr, end);
 669
 670                 /*
 671                  * Try a section mapping - addr, next and phys must all be
 672                  * aligned to a section boundary.
 673                  */
 674                 if (type->prot_sect &&
 675                                 ((addr | next | phys) & ~SECTION_MASK) == 0) {
 676                         __map_init_section(pmd, addr, next, phys, type);
 677                 } else {
 678                         alloc_init_pte(pmd, addr, next,
 679                                                 __phys_to_pfn(phys), type);
 680                 }
 681
 682                 phys += next - addr;
 683
 684         } while (pmd++, addr = next, addr != end);
 685 }
 686
 687 static void __init alloc_init_pud(pgd_t *pgd, unsigned long addr,
 688         unsigned long end, unsigned long phys, const struct mem_type *type)
 689 {
 690         pud_t *pud = pud_offset(pgd, addr);
 691         unsigned long next;
 692
 693         do {
 694                 next = pud_addr_end(addr, end);
 695                 alloc_init_pmd(pud, addr, next, phys, type);
 696                 phys += next - addr;
 697         } while (pud++, addr = next, addr != end);
 698 }
 699
 700 #ifndef CONFIG_ARM_LPAE
 701 static void __init create_36bit_mapping(struct map_desc *md,
 702                                         const struct mem_type *type)
 703 {
 704         unsigned long addr, length, end;
 705         phys_addr_t phys;
 706         pgd_t *pgd;
 707
 708         addr = md->virtual;
 709         phys = __pfn_to_phys(md->pfn);
 710         length = PAGE_ALIGN(md->length);
 711
 712         if (!(cpu_architecture() >= CPU_ARCH_ARMv6 || cpu_is_xsc3())) {
 713                 printk(KERN_ERR "MM: CPU does not support supersection "
 714                        "mapping for 0x%08llx at 0x%08lx\n",
 715                        (long long)__pfn_to_phys((u64)md->pfn), addr);
 716                 return;
 717         }
 718
 719         /* N.B. ARMv6 supersections are only defined to work with domain 0.
 720          *      Since domain assignments can in fact be arbitrary, the
 721          *      'domain == 0' check below is required to insure that ARMv6
 722          *      supersections are only allocated for domain 0 regardless
 723          *      of the actual domain assignments in use.
 724          */
 725         if (type->domain) {
 726                 printk(KERN_ERR "MM: invalid domain in supersection "
 727                        "mapping for 0x%08llx at 0x%08lx\n",
 728                        (long long)__pfn_to_phys((u64)md->pfn), addr);
 729                 return;
 730         }
 731
 732         if ((addr | length | __pfn_to_phys(md->pfn)) & ~SUPERSECTION_MASK) {
 733                 printk(KERN_ERR "MM: cannot create mapping for 0x%08llx"
 734                        " at 0x%08lx invalid alignment\n",
 735                        (long long)__pfn_to_phys((u64)md->pfn), addr);
 736                 return;
 737         }
 738
 739         /*
 740          * Shift bits [35:32] of address into bits [23:20] of PMD
 741          * (See ARMv6 spec).
 742          */
 743         phys |= (((md->pfn >> (32 - PAGE_SHIFT)) & 0xF) << 20);
 744
 745         pgd = pgd_offset_k(addr);
 746         end = addr + length;
 747         do {
 748                 pud_t *pud = pud_offset(pgd, addr);
 749                 pmd_t *pmd = pmd_offset(pud, addr);
 750                 int i;
 751
 752                 for (i = 0; i < 16; i++)
 753                         *pmd++ = __pmd(phys | type->prot_sect | PMD_SECT_SUPER);
 754
 755                 addr += SUPERSECTION_SIZE;
 756                 phys += SUPERSECTION_SIZE;
 757                 pgd += SUPERSECTION_SIZE >> PGDIR_SHIFT;
 758         } while (addr != end);
 759 }
 760 #endif  /* !CONFIG_ARM_LPAE */
 761
 762 /*
 763  * Create the page directory entries and any necessary
 764  * page tables for the mapping specified by `md'.  We
 765  * are able to cope here with varying sizes and address
 766  * offsets, and we take full advantage of sections and
 767  * supersections.
 768  */
 769 static void __init create_mapping(struct map_desc *md)
 770 {
 771         unsigned long addr, length, end;
 772         phys_addr_t phys;
 773         const struct mem_type *type;
 774         pgd_t *pgd;
 775
 776         if (md->virtual != vectors_base() && md->virtual < TASK_SIZE) {
 777                 printk(KERN_WARNING "BUG: not creating mapping for 0x%08llx"
 778                        " at 0x%08lx in user region\n",
 779                        (long long)__pfn_to_phys((u64)md->pfn), md->virtual);
 780                 return;
 781         }
 782
 783         if ((md->type == MT_DEVICE || md->type == MT_ROM) &&
 784             md->virtual >= PAGE_OFFSET &&
 785             (md->virtual < VMALLOC_START || md->virtual >= VMALLOC_END)) {
 786                 printk(KERN_WARNING "BUG: mapping for 0x%08llx"
 787                        " at 0x%08lx out of vmalloc space\n",
 788                        (long long)__pfn_to_phys((u64)md->pfn), md->virtual);
 789         }
 790
 791         type = &mem_types[md->type];
 792
 793 #ifndef CONFIG_ARM_LPAE
 794         /*
 795          * Catch 36-bit addresses
 796          */
 797         if (md->pfn >= 0x100000) {
 798                 create_36bit_mapping(md, type);
 799                 return;
 800         }
 801 #endif
 802
 803         addr = md->virtual & PAGE_MASK;
 804         phys = __pfn_to_phys(md->pfn);
 805         length = PAGE_ALIGN(md->length + (md->virtual & ~PAGE_MASK));
 806
 807         if (type->prot_l1 == 0 && ((addr | phys | length) & ~SECTION_MASK)) {
 808                 printk(KERN_WARNING "BUG: map for 0x%08llx at 0x%08lx can not "
 809                        "be mapped using pages, ignoring.\n",
 810                        (long long)__pfn_to_phys(md->pfn), addr);
 811                 return;
 812         }
 813
 814         pgd = pgd_offset_k(addr);
 815         end = addr + length;
 816         do {
 817                 unsigned long next = pgd_addr_end(addr, end);
 818
 819                 alloc_init_pud(pgd, addr, next, phys, type);
 820
 821                 phys += next - addr;
 822                 addr = next;
 823         } while (pgd++, addr != end);
 824 }
 825
 826 /*
 827  * Create the architecture specific mappings
 828  */
 829 void __init iotable_init(struct map_desc *io_desc, int nr)
 830 {
 831         struct map_desc *md;
 832         struct vm_struct *vm;
 833         struct static_vm *svm;
 834
 835         if (!nr)
 836                 return;
 837
 838         svm = early_alloc_aligned(sizeof(*svm) * nr, __alignof__(*svm));
 839
 840         for (md = io_desc; nr; md++, nr--) {
 841                 create_mapping(md);
 842
 843                 vm = &svm->vm;
 844                 vm->addr = (void *)(md->virtual & PAGE_MASK);
 845                 vm->size = PAGE_ALIGN(md->length + (md->virtual & ~PAGE_MASK));
 846                 vm->phys_addr = __pfn_to_phys(md->pfn);
 847                 vm->flags = VM_IOREMAP | VM_ARM_STATIC_MAPPING;
 848                 vm->flags |= VM_ARM_MTYPE(md->type);
 849                 vm->caller = iotable_init;
 850                 add_static_vm_early(svm++);
 851         }
 852 }
 853
 854 void __init vm_reserve_area_early(unsigned long addr, unsigned long size,
 855                                   void *caller)
 856 {
 857         struct vm_struct *vm;
 858         struct static_vm *svm;
 859
 860         svm = early_alloc_aligned(sizeof(*svm), __alignof__(*svm));
 861
 862         vm = &svm->vm;
 863         vm->addr = (void *)addr;
 864         vm->size = size;
 865         vm->flags = VM_IOREMAP | VM_ARM_EMPTY_MAPPING;
 866         vm->caller = caller;
 867         add_static_vm_early(svm);
 868 }
 869
 870 #ifndef CONFIG_ARM_LPAE
 871
 872 /*
 873  * The Linux PMD is made of two consecutive section entries covering 2MB
 874  * (see definition in include/asm/pgtable-2level.h).  However a call to
 875  * create_mapping() may optimize static mappings by using individual
 876  * 1MB section mappings.  This leaves the actual PMD potentially half
 877  * initialized if the top or bottom section entry isn't used, leaving it
 878  * open to problems if a subsequent ioremap() or vmalloc() tries to use
 879  * the virtual space left free by that unused section entry.
 880  *
 881  * Let's avoid the issue by inserting dummy vm entries covering the unused
 882  * PMD halves once the static mappings are in place.
 883  */
 884
 885 static void __init pmd_empty_section_gap(unsigned long addr)
 886 {
 887         vm_reserve_area_early(addr, SECTION_SIZE, pmd_empty_section_gap);
 888 }
 889
 890 static void __init fill_pmd_gaps(void)
 891 {
 892         struct static_vm *svm;
 893         struct vm_struct *vm;
 894         unsigned long addr, next = 0;
 895         pmd_t *pmd;
 896
 897         list_for_each_entry(svm, &static_vmlist, list) {
 898                 vm = &svm->vm;
 899                 addr = (unsigned long)vm->addr;
 900                 if (addr < next)
 901                         continue;
 902
 903                 /*
 904                  * Check if this vm starts on an odd section boundary.
 905                  * If so and the first section entry for this PMD is free
 906                  * then we block the corresponding virtual address.
 907                  */
 908                 if ((addr & ~PMD_MASK) == SECTION_SIZE) {
 909                         pmd = pmd_off_k(addr);
 910                         if (pmd_none(*pmd))
 911                                 pmd_empty_section_gap(addr & PMD_MASK);
 912                 }
 913
 914                 /*
 915                  * Then check if this vm ends on an odd section boundary.
 916                  * If so and the second section entry for this PMD is empty
 917                  * then we block the corresponding virtual address.
 918                  */
 919                 addr += vm->size;
 920                 if ((addr & ~PMD_MASK) == SECTION_SIZE) {
 921                         pmd = pmd_off_k(addr) + 1;
 922                         if (pmd_none(*pmd))
 923                                 pmd_empty_section_gap(addr);
 924                 }
 925
 926                 /* no need to look at any vm entry until we hit the next PMD */
 927                 next = (addr + PMD_SIZE - 1) & PMD_MASK;
 928         }
 929 }
 930
 931 #else
 932 #define fill_pmd_gaps() do { } while (0)
 933 #endif
 934
 935 #if defined(CONFIG_PCI) && !defined(CONFIG_NEED_MACH_IO_H)
 936 static void __init pci_reserve_io(void)
 937 {
 938         struct static_vm *svm;
 939
 940         svm = find_static_vm_vaddr((void *)PCI_IO_VIRT_BASE);
 941         if (svm)
 942                 return;
 943
 944         vm_reserve_area_early(PCI_IO_VIRT_BASE, SZ_2M, pci_reserve_io);
 945 }
 946 #else
 947 #define pci_reserve_io() do { } while (0)
 948 #endif
 949
 950 #ifdef CONFIG_DEBUG_LL
 951 void __init debug_ll_io_init(void)
 952 {
 953         struct map_desc map;
 954
 955         debug_ll_addr(&map.pfn, &map.virtual);
 956         if (!map.pfn || !map.virtual)
 957                 return;
 958         map.pfn = __phys_to_pfn(map.pfn);
 959         map.virtual &= PAGE_MASK;
 960         map.length = PAGE_SIZE;
 961         map.type = MT_DEVICE;
 962         create_mapping(&map);
 963 }
 964 #endif
 965
 966 static void * __initdata vmalloc_min =
 967         (void *)(VMALLOC_END - (240 << 20) - VMALLOC_OFFSET);
 968
 969 /*
 970  * vmalloc=size forces the vmalloc area to be exactly 'size'
 971  * bytes. This can be used to increase (or decrease) the vmalloc
 972  * area - the default is 240m.
 973  */
 974 static int __init early_vmalloc(char *arg)
 975 {
 976         unsigned long vmalloc_reserve = memparse(arg, NULL);
 977
 978         if (vmalloc_reserve < SZ_16M) {
 979                 vmalloc_reserve = SZ_16M;
 980                 printk(KERN_WARNING
 981                         "vmalloc area too small, limiting to %luMB\n",
 982                         vmalloc_reserve >> 20);
 983         }
 984
 985         if (vmalloc_reserve > VMALLOC_END - (PAGE_OFFSET + SZ_32M)) {
 986                 vmalloc_reserve = VMALLOC_END - (PAGE_OFFSET + SZ_32M);
 987                 printk(KERN_WARNING
 988                         "vmalloc area is too big, limiting to %luMB\n",
 989                         vmalloc_reserve >> 20);
 990         }
 991
 992         vmalloc_min = (void *)(VMALLOC_END - vmalloc_reserve);
 993         return 0;
 994 }
 995 early_param("vmalloc", early_vmalloc);
 996
 997 phys_addr_t arm_lowmem_limit __initdata = 0;
 998
 999 void __init sanity_check_meminfo(void)
1000 {
1001         int i, j, highmem = 0;
1002
1003         for (i = 0, j = 0; i < meminfo.nr_banks; i++) {
1004                 struct membank *bank = &meminfo.bank[j];
1005                 *bank = meminfo.bank[i];
1006
1007                 if (bank->start > ULONG_MAX)
1008                         highmem = 1;
1009
1010 #ifdef CONFIG_HIGHMEM
1011                 if (__va(bank->start) >= vmalloc_min ||
1012                     __va(bank->start) < (void *)PAGE_OFFSET)
1013                         highmem = 1;
1014
1015                 bank->highmem = highmem;
1016
1017                 /*
1018                  * Split those memory banks which are partially overlapping
1019                  * the vmalloc area greatly simplifying things later.
1020                  */
1021                 if (!highmem && __va(bank->start) < vmalloc_min &&
1022                     bank->size > vmalloc_min - __va(bank->start)) {
1023                         if (meminfo.nr_banks >= NR_BANKS) {
1024                                 printk(KERN_CRIT "NR_BANKS too low, "
1025                                                  "ignoring high memory\n");
1026                         } else {
1027                                 memmove(bank + 1, bank,
1028                                         (meminfo.nr_banks - i) * sizeof(*bank));
1029                                 meminfo.nr_banks++;
1030                                 i++;
1031                                 bank[1].size -= vmalloc_min - __va(bank->start);
1032                                 bank[1].start = __pa(vmalloc_min - 1) + 1;
1033                                 bank[1].highmem = highmem = 1;
1034                                 j++;
1035                         }
1036                         bank->size = vmalloc_min - __va(bank->start);
1037                 }
1038 #else
1039                 bank->highmem = highmem;
1040
1041                 /*
1042                  * Highmem banks not allowed with !CONFIG_HIGHMEM.
1043                  */
1044                 if (highmem) {
1045                         printk(KERN_NOTICE "Ignoring RAM at %.8llx-%.8llx "
1046                                "(!CONFIG_HIGHMEM).\n",
1047                                (unsigned long long)bank->start,
1048                                (unsigned long long)bank->start + bank->size - 1);
1049                         continue;
1050                 }
1051
1052                 /*
1053                  * Check whether this memory bank would entirely overlap
1054                  * the vmalloc area.
1055                  */
1056                 if (__va(bank->start) >= vmalloc_min ||
1057                     __va(bank->start) < (void *)PAGE_OFFSET) {
1058                         printk(KERN_NOTICE "Ignoring RAM at %.8llx-%.8llx "
1059                                "(vmalloc region overlap).\n",
1060                                (unsigned long long)bank->start,
1061                                (unsigned long long)bank->start + bank->size - 1);
1062                         continue;
1063                 }
1064
1065                 /*
1066                  * Check whether this memory bank would partially overlap
1067                  * the vmalloc area.
1068                  */
1069                 if (__va(bank->start + bank->size - 1) >= vmalloc_min ||
1070                     __va(bank->start + bank->size - 1) <= __va(bank->start)) {
1071                         unsigned long newsize = vmalloc_min - __va(bank->start);
1072                         printk(KERN_NOTICE "Truncating RAM at %.8llx-%.8llx "
1073                                "to -%.8llx (vmalloc region overlap).\n",
1074                                (unsigned long long)bank->start,
1075                                (unsigned long long)bank->start + bank->size - 1,
1076                                (unsigned long long)bank->start + newsize - 1);
1077                         bank->size = newsize;
1078                 }
1079 #endif
1080                 if (!bank->highmem && bank->start + bank->size > arm_lowmem_limit)
1081                         arm_lowmem_limit = bank->start + bank->size;
1082
1083                 j++;
1084         }
1085 #ifdef CONFIG_HIGHMEM
1086         if (highmem) {
1087                 const char *reason = NULL;
1088
1089                 if (cache_is_vipt_aliasing()) {
1090                         /*
1091                          * Interactions between kmap and other mappings
1092                          * make highmem support with aliasing VIPT caches
1093                          * rather difficult.
1094                          */
1095                         reason = "with VIPT aliasing cache";
1096                 }
1097                 if (reason) {
1098                         printk(KERN_CRIT "HIGHMEM is not supported %s, ignoring high memory\n",
1099                                 reason);
1100                         while (j > 0 && meminfo.bank[j - 1].highmem)
1101                                 j--;
1102                 }
1103         }
1104 #endif
1105         meminfo.nr_banks = j;
1106         high_memory = __va(arm_lowmem_limit - 1) + 1;
1107         memblock_set_current_limit(arm_lowmem_limit);
1108 }
1109
1110 static inline void prepare_page_table(void)
1111 {
1112         unsigned long addr;
1113         phys_addr_t end;
1114
1115         /*
1116          * Clear out all the mappings below the kernel image.
1117          */
1118         for (addr = 0; addr < MODULES_VADDR; addr += PMD_SIZE)
1119                 pmd_clear(pmd_off_k(addr));
1120
1121 #ifdef CONFIG_XIP_KERNEL
1122         /* The XIP kernel is mapped in the module area -- skip over it */
1123         addr = ((unsigned long)_etext + PMD_SIZE - 1) & PMD_MASK;
1124 #endif
1125         for ( ; addr < PAGE_OFFSET; addr += PMD_SIZE)
1126                 pmd_clear(pmd_off_k(addr));
1127
1128         /*
1129          * Find the end of the first block of lowmem.
1130          */
1131         end = memblock.memory.regions[0].base + memblock.memory.regions[0].size;
1132         if (end >= arm_lowmem_limit)
1133                 end = arm_lowmem_limit;
1134
1135         /*
1136          * Clear out all the kernel space mappings, except for the first
1137          * memory bank, up to the vmalloc region.
1138          */
1139         for (addr = __phys_to_virt(end);
1140              addr < VMALLOC_START; addr += PMD_SIZE)
1141                 pmd_clear(pmd_off_k(addr));
1142 }
1143
1144 #ifdef CONFIG_ARM_LPAE
1145 /* the first page is reserved for pgd */
1146 #define SWAPPER_PG_DIR_SIZE     (PAGE_SIZE + \
1147                                  PTRS_PER_PGD * PTRS_PER_PMD * sizeof(pmd_t))
1148 #else
1149 #define SWAPPER_PG_DIR_SIZE     (PTRS_PER_PGD * sizeof(pgd_t))
1150 #endif
1151
1152 /*
1153  * Reserve the special regions of memory
1154  */
1155 void __init arm_mm_memblock_reserve(void)
1156 {
1157         /*
1158          * Reserve the page tables.  These are already in use,
1159          * and can only be in node 0.
1160          */
1161         memblock_reserve(__pa(swapper_pg_dir), SWAPPER_PG_DIR_SIZE);
1162
1163 #ifdef CONFIG_SA1111
1164         /*
1165          * Because of the SA1111 DMA bug, we want to preserve our
1166          * precious DMA-able memory...
1167          */
1168         memblock_reserve(PHYS_OFFSET, __pa(swapper_pg_dir) - PHYS_OFFSET);
1169 #endif
1170 }
1171
1172 /*
1173  * Set up the device mappings.  Since we clear out the page tables for all
1174  * mappings above VMALLOC_START, we will remove any debug device mappings.
1175  * This means you have to be careful how you debug this function, or any
1176  * called function.  This means you can't use any function or debugging
1177  * method which may touch any device, otherwise the kernel _will_ crash.
1178  */
1179 static void __init devicemaps_init(struct machine_desc *mdesc)
1180 {
1181         struct map_desc map;
1182         unsigned long addr;
1183         void *vectors;
1184
1185         /*
1186          * Allocate the vector page early.
1187          */
1188         vectors = early_alloc(PAGE_SIZE * 2);
1189
1190         early_trap_init(vectors);
1191
1192         for (addr = VMALLOC_START; addr; addr += PMD_SIZE)
1193                 pmd_clear(pmd_off_k(addr));
1194
1195         /*
1196          * Map the kernel if it is XIP.
1197          * It is always first in the modulearea.
1198          */
1199 #ifdef CONFIG_XIP_KERNEL
1200         map.pfn = __phys_to_pfn(CONFIG_XIP_PHYS_ADDR & SECTION_MASK);
1201         map.virtual = MODULES_VADDR;
1202         map.length = ((unsigned long)_etext - map.virtual + ~SECTION_MASK) & SECTION_MASK;
1203         map.type = MT_ROM;
1204         create_mapping(&map);
1205 #endif
1206
1207         /*
1208          * Map the cache flushing regions.
1209          */
1210 #ifdef FLUSH_BASE
1211         map.pfn = __phys_to_pfn(FLUSH_BASE_PHYS);
1212         map.virtual = FLUSH_BASE;
1213         map.length = SZ_1M;
1214         map.type = MT_CACHECLEAN;
1215         create_mapping(&map);
1216 #endif
1217 #ifdef FLUSH_BASE_MINICACHE
1218         map.pfn = __phys_to_pfn(FLUSH_BASE_PHYS + SZ_1M);
1219         map.virtual = FLUSH_BASE_MINICACHE;
1220         map.length = SZ_1M;
1221         map.type = MT_MINICLEAN;
1222         create_mapping(&map);
1223 #endif
1224
1225         /*
1226          * Create a mapping for the machine vectors at the high-vectors
1227          * location (0xffff0000).  If we aren't using high-vectors, also
1228          * create a mapping at the low-vectors virtual address.
1229          */
1230         map.pfn = __phys_to_pfn(virt_to_phys(vectors));
1231         map.virtual = 0xffff0000;
1232         map.length = PAGE_SIZE;
1233 #ifdef CONFIG_KUSER_HELPERS
1234         map.type = MT_HIGH_VECTORS;
1235 #else
1236         map.type = MT_LOW_VECTORS;
1237 #endif
1238         create_mapping(&map);
1239
1240         if (!vectors_high()) {
1241                 map.virtual = 0;
1242                 map.length = PAGE_SIZE * 2;
1243                 map.type = MT_LOW_VECTORS;
1244                 create_mapping(&map);
1245         }
1246
1247         /* Now create a kernel read-only mapping */
1248         map.pfn += 1;
1249         map.virtual = 0xffff0000 + PAGE_SIZE;
1250         map.length = PAGE_SIZE;
1251         map.type = MT_LOW_VECTORS;
1252         create_mapping(&map);
1253
1254         /*
1255          * Ask the machine support to map in the statically mapped devices.
1256          */
1257         if (mdesc->map_io)
1258                 mdesc->map_io();
1259         fill_pmd_gaps();
1260
1261         /* Reserve fixed i/o space in VMALLOC region */
1262         pci_reserve_io();
1263
1264         /*
1265          * Finally flush the caches and tlb to ensure that we're in a
1266          * consistent state wrt the writebuffer.  This also ensures that
1267          * any write-allocated cache lines in the vector page are written
1268          * back.  After this point, we can start to touch devices again.
1269          */
1270         local_flush_tlb_all();
1271         flush_cache_all();
1272 }
1273
1274 static void __init kmap_init(void)
1275 {
1276 #ifdef CONFIG_HIGHMEM
1277         pkmap_page_table = early_pte_alloc(pmd_off_k(PKMAP_BASE),
1278                 PKMAP_BASE, _PAGE_KERNEL_TABLE);
1279 #endif
1280 }
1281
1282 static void __init map_lowmem(void)
1283 {
1284         struct memblock_region *reg;
1285
1286         /* Map all the lowmem memory banks. */
1287         for_each_memblock(memory, reg) {
1288                 phys_addr_t start = reg->base;
1289                 phys_addr_t end = start + reg->size;
1290                 struct map_desc map;
1291
1292                 if (end > arm_lowmem_limit)
1293                         end = arm_lowmem_limit;
1294                 if (start >= end)
1295                         break;
1296
1297                 map.pfn = __phys_to_pfn(start);
1298                 map.virtual = __phys_to_virt(start);
1299                 map.length = end - start;
1300                 map.type = MT_MEMORY;
1301
1302                 create_mapping(&map);
1303         }
1304 }
1305
1306 /*
1307  * paging_init() sets up the page tables, initialises the zone memory
1308  * maps, and sets up the zero page, bad page and bad page tables.
1309  */
1310 void __init paging_init(struct machine_desc *mdesc)
1311 {
1312         void *zero_page;
1313
1314         memblock_set_current_limit(arm_lowmem_limit);
1315
1316         build_mem_type_table();
1317         prepare_page_table();
1318         map_lowmem();
1319         dma_contiguous_remap();
1320         devicemaps_init(mdesc);
1321         kmap_init();
1322         tcm_init();
1323
1324         top_pmd = pmd_off_k(0xffff0000);
1325
1326         /* allocate the zero page. */
1327         zero_page = early_alloc(PAGE_SIZE);
1328
1329         bootmem_init();
1330
1331         empty_zero_page = virt_to_page(zero_page);
1332         __flush_dcache_page(NULL, empty_zero_page);
1333 }