2 * linux/arch/arm/mm/mmu.c
4 * Copyright (C) 1995-2005 Russell King
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 #include <linux/module.h>
11 #include <linux/kernel.h>
12 #include <linux/errno.h>
13 #include <linux/init.h>
14 #include <linux/mman.h>
15 #include <linux/nodemask.h>
16 #include <linux/memblock.h>
17 #include <linux/sort.h>
20 #include <asm/cputype.h>
21 #include <asm/sections.h>
22 #include <asm/cachetype.h>
23 #include <asm/setup.h>
24 #include <asm/sizes.h>
25 #include <asm/smp_plat.h>
27 #include <asm/highmem.h>
29 #include <asm/mach/arch.h>
30 #include <asm/mach/map.h>
34 DEFINE_PER_CPU(struct mmu_gather, mmu_gathers);
37 * empty_zero_page is a special page that is used for
38 * zero-initialized data and COW.
40 struct page *empty_zero_page;
41 EXPORT_SYMBOL(empty_zero_page);
44 * The pmd table for the upper-most set of pages.
48 #define CPOLICY_UNCACHED 0
49 #define CPOLICY_BUFFERED 1
50 #define CPOLICY_WRITETHROUGH 2
51 #define CPOLICY_WRITEBACK 3
52 #define CPOLICY_WRITEALLOC 4
54 static unsigned int cachepolicy __initdata = CPOLICY_WRITEBACK;
55 static unsigned int ecc_mask __initdata = 0;
57 pgprot_t pgprot_kernel;
59 EXPORT_SYMBOL(pgprot_user);
60 EXPORT_SYMBOL(pgprot_kernel);
63 const char policy[16];
69 static struct cachepolicy cache_policies[] __initdata = {
73 .pmd = PMD_SECT_UNCACHED,
74 .pte = L_PTE_MT_UNCACHED,
78 .pmd = PMD_SECT_BUFFERED,
79 .pte = L_PTE_MT_BUFFERABLE,
81 .policy = "writethrough",
84 .pte = L_PTE_MT_WRITETHROUGH,
86 .policy = "writeback",
89 .pte = L_PTE_MT_WRITEBACK,
91 .policy = "writealloc",
94 .pte = L_PTE_MT_WRITEALLOC,
99 * These are useful for identifying cache coherency
100 * problems by allowing the cache or the cache and
101 * writebuffer to be turned off. (Note: the write
102 * buffer should not be on and the cache off).
104 static int __init early_cachepolicy(char *p)
108 for (i = 0; i < ARRAY_SIZE(cache_policies); i++) {
109 int len = strlen(cache_policies[i].policy);
111 if (memcmp(p, cache_policies[i].policy, len) == 0) {
113 cr_alignment &= ~cache_policies[i].cr_mask;
114 cr_no_alignment &= ~cache_policies[i].cr_mask;
118 if (i == ARRAY_SIZE(cache_policies))
119 printk(KERN_ERR "ERROR: unknown or unsupported cache policy\n");
121 * This restriction is partly to do with the way we boot; it is
122 * unpredictable to have memory mapped using two different sets of
123 * memory attributes (shared, type, and cache attribs). We can not
124 * change these attributes once the initial assembly has setup the
127 if (cpu_architecture() >= CPU_ARCH_ARMv6) {
128 printk(KERN_WARNING "Only cachepolicy=writeback supported on ARMv6 and later\n");
129 cachepolicy = CPOLICY_WRITEBACK;
132 set_cr(cr_alignment);
135 early_param("cachepolicy", early_cachepolicy);
137 static int __init early_nocache(char *__unused)
139 char *p = "buffered";
140 printk(KERN_WARNING "nocache is deprecated; use cachepolicy=%s\n", p);
141 early_cachepolicy(p);
144 early_param("nocache", early_nocache);
146 static int __init early_nowrite(char *__unused)
148 char *p = "uncached";
149 printk(KERN_WARNING "nowb is deprecated; use cachepolicy=%s\n", p);
150 early_cachepolicy(p);
153 early_param("nowb", early_nowrite);
155 static int __init early_ecc(char *p)
157 if (memcmp(p, "on", 2) == 0)
158 ecc_mask = PMD_PROTECTION;
159 else if (memcmp(p, "off", 3) == 0)
163 early_param("ecc", early_ecc);
165 static int __init noalign_setup(char *__unused)
167 cr_alignment &= ~CR_A;
168 cr_no_alignment &= ~CR_A;
169 set_cr(cr_alignment);
172 __setup("noalign", noalign_setup);
175 void adjust_cr(unsigned long mask, unsigned long set)
183 local_irq_save(flags);
185 cr_no_alignment = (cr_no_alignment & ~mask) | set;
186 cr_alignment = (cr_alignment & ~mask) | set;
188 set_cr((get_cr() & ~mask) | set);
190 local_irq_restore(flags);
194 #define PROT_PTE_DEVICE L_PTE_PRESENT|L_PTE_YOUNG|L_PTE_DIRTY|L_PTE_WRITE
195 #define PROT_SECT_DEVICE PMD_TYPE_SECT|PMD_SECT_AP_WRITE
197 static struct mem_type mem_types[] = {
198 [MT_DEVICE] = { /* Strongly ordered / ARMv6 shared device */
199 .prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_SHARED |
201 .prot_l1 = PMD_TYPE_TABLE,
202 .prot_sect = PROT_SECT_DEVICE | PMD_SECT_S,
205 [MT_DEVICE_NONSHARED] = { /* ARMv6 non-shared device */
206 .prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_NONSHARED,
207 .prot_l1 = PMD_TYPE_TABLE,
208 .prot_sect = PROT_SECT_DEVICE,
211 [MT_DEVICE_CACHED] = { /* ioremap_cached */
212 .prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_CACHED,
213 .prot_l1 = PMD_TYPE_TABLE,
214 .prot_sect = PROT_SECT_DEVICE | PMD_SECT_WB,
217 [MT_DEVICE_WC] = { /* ioremap_wc */
218 .prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_WC,
219 .prot_l1 = PMD_TYPE_TABLE,
220 .prot_sect = PROT_SECT_DEVICE,
224 .prot_pte = PROT_PTE_DEVICE,
225 .prot_l1 = PMD_TYPE_TABLE,
226 .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN,
230 .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN,
231 .domain = DOMAIN_KERNEL,
234 .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN | PMD_SECT_MINICACHE,
235 .domain = DOMAIN_KERNEL,
238 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
240 .prot_l1 = PMD_TYPE_TABLE,
241 .domain = DOMAIN_USER,
243 [MT_HIGH_VECTORS] = {
244 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
245 L_PTE_USER | L_PTE_EXEC,
246 .prot_l1 = PMD_TYPE_TABLE,
247 .domain = DOMAIN_USER,
250 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
251 L_PTE_WRITE | L_PTE_EXEC,
252 .prot_l1 = PMD_TYPE_TABLE,
253 .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE,
254 .domain = DOMAIN_KERNEL,
257 .prot_sect = PMD_TYPE_SECT,
258 .domain = DOMAIN_KERNEL,
260 [MT_MEMORY_NONCACHED] = {
261 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
262 L_PTE_WRITE | L_PTE_EXEC | L_PTE_MT_BUFFERABLE,
263 .prot_l1 = PMD_TYPE_TABLE,
264 .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE,
265 .domain = DOMAIN_KERNEL,
268 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG |
269 L_PTE_DIRTY | L_PTE_WRITE,
270 .prot_l1 = PMD_TYPE_TABLE,
271 .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN,
272 .domain = DOMAIN_KERNEL,
275 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
276 L_PTE_USER | L_PTE_EXEC,
277 .prot_l1 = PMD_TYPE_TABLE,
282 const struct mem_type *get_mem_type(unsigned int type)
284 return type < ARRAY_SIZE(mem_types) ? &mem_types[type] : NULL;
286 EXPORT_SYMBOL(get_mem_type);
289 * Adjust the PMD section entries according to the CPU in use.
291 static void __init build_mem_type_table(void)
293 struct cachepolicy *cp;
294 unsigned int cr = get_cr();
295 unsigned int user_pgprot, kern_pgprot, vecs_pgprot;
296 int cpu_arch = cpu_architecture();
299 if (cpu_arch < CPU_ARCH_ARMv6) {
300 #if defined(CONFIG_CPU_DCACHE_DISABLE)
301 if (cachepolicy > CPOLICY_BUFFERED)
302 cachepolicy = CPOLICY_BUFFERED;
303 #elif defined(CONFIG_CPU_DCACHE_WRITETHROUGH)
304 if (cachepolicy > CPOLICY_WRITETHROUGH)
305 cachepolicy = CPOLICY_WRITETHROUGH;
308 if (cpu_arch < CPU_ARCH_ARMv5) {
309 if (cachepolicy >= CPOLICY_WRITEALLOC)
310 cachepolicy = CPOLICY_WRITEBACK;
314 cachepolicy = CPOLICY_WRITEALLOC;
318 * Strip out features not present on earlier architectures.
319 * Pre-ARMv5 CPUs don't have TEX bits. Pre-ARMv6 CPUs or those
320 * without extended page tables don't have the 'Shared' bit.
322 if (cpu_arch < CPU_ARCH_ARMv5)
323 for (i = 0; i < ARRAY_SIZE(mem_types); i++)
324 mem_types[i].prot_sect &= ~PMD_SECT_TEX(7);
325 if ((cpu_arch < CPU_ARCH_ARMv6 || !(cr & CR_XP)) && !cpu_is_xsc3())
326 for (i = 0; i < ARRAY_SIZE(mem_types); i++)
327 mem_types[i].prot_sect &= ~PMD_SECT_S;
330 * ARMv5 and lower, bit 4 must be set for page tables (was: cache
331 * "update-able on write" bit on ARM610). However, Xscale and
332 * Xscale3 require this bit to be cleared.
334 if (cpu_is_xscale() || cpu_is_xsc3()) {
335 for (i = 0; i < ARRAY_SIZE(mem_types); i++) {
336 mem_types[i].prot_sect &= ~PMD_BIT4;
337 mem_types[i].prot_l1 &= ~PMD_BIT4;
339 } else if (cpu_arch < CPU_ARCH_ARMv6) {
340 for (i = 0; i < ARRAY_SIZE(mem_types); i++) {
341 if (mem_types[i].prot_l1)
342 mem_types[i].prot_l1 |= PMD_BIT4;
343 if (mem_types[i].prot_sect)
344 mem_types[i].prot_sect |= PMD_BIT4;
349 * Mark the device areas according to the CPU/architecture.
351 if (cpu_is_xsc3() || (cpu_arch >= CPU_ARCH_ARMv6 && (cr & CR_XP))) {
352 if (!cpu_is_xsc3()) {
354 * Mark device regions on ARMv6+ as execute-never
355 * to prevent speculative instruction fetches.
357 mem_types[MT_DEVICE].prot_sect |= PMD_SECT_XN;
358 mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_XN;
359 mem_types[MT_DEVICE_CACHED].prot_sect |= PMD_SECT_XN;
360 mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_XN;
362 if (cpu_arch >= CPU_ARCH_ARMv7 && (cr & CR_TRE)) {
364 * For ARMv7 with TEX remapping,
365 * - shared device is SXCB=1100
366 * - nonshared device is SXCB=0100
367 * - write combine device mem is SXCB=0001
368 * (Uncached Normal memory)
370 mem_types[MT_DEVICE].prot_sect |= PMD_SECT_TEX(1);
371 mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_TEX(1);
372 mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_BUFFERABLE;
373 } else if (cpu_is_xsc3()) {
376 * - shared device is TEXCB=00101
377 * - nonshared device is TEXCB=01000
378 * - write combine device mem is TEXCB=00100
379 * (Inner/Outer Uncacheable in xsc3 parlance)
381 mem_types[MT_DEVICE].prot_sect |= PMD_SECT_TEX(1) | PMD_SECT_BUFFERED;
382 mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_TEX(2);
383 mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_TEX(1);
386 * For ARMv6 and ARMv7 without TEX remapping,
387 * - shared device is TEXCB=00001
388 * - nonshared device is TEXCB=01000
389 * - write combine device mem is TEXCB=00100
390 * (Uncached Normal in ARMv6 parlance).
392 mem_types[MT_DEVICE].prot_sect |= PMD_SECT_BUFFERED;
393 mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_TEX(2);
394 mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_TEX(1);
398 * On others, write combining is "Uncached/Buffered"
400 mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_BUFFERABLE;
404 * Now deal with the memory-type mappings
406 cp = &cache_policies[cachepolicy];
407 vecs_pgprot = kern_pgprot = user_pgprot = cp->pte;
411 * Only use write-through for non-SMP systems
413 if (cpu_arch >= CPU_ARCH_ARMv5 && cachepolicy > CPOLICY_WRITETHROUGH)
414 vecs_pgprot = cache_policies[CPOLICY_WRITETHROUGH].pte;
418 * Enable CPU-specific coherency if supported.
419 * (Only available on XSC3 at the moment.)
421 if (arch_is_coherent() && cpu_is_xsc3()) {
422 mem_types[MT_MEMORY].prot_sect |= PMD_SECT_S;
423 mem_types[MT_MEMORY].prot_pte |= L_PTE_SHARED;
424 mem_types[MT_MEMORY_NONCACHED].prot_sect |= PMD_SECT_S;
425 mem_types[MT_MEMORY_NONCACHED].prot_pte |= L_PTE_SHARED;
428 * ARMv6 and above have extended page tables.
430 if (cpu_arch >= CPU_ARCH_ARMv6 && (cr & CR_XP)) {
432 * Mark cache clean areas and XIP ROM read only
433 * from SVC mode and no access from userspace.
435 mem_types[MT_ROM].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE;
436 mem_types[MT_MINICLEAN].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE;
437 mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE;
441 * Mark memory with the "shared" attribute for SMP systems
443 user_pgprot |= L_PTE_SHARED;
444 kern_pgprot |= L_PTE_SHARED;
445 vecs_pgprot |= L_PTE_SHARED;
446 mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_S;
447 mem_types[MT_DEVICE_WC].prot_pte |= L_PTE_SHARED;
448 mem_types[MT_DEVICE_CACHED].prot_sect |= PMD_SECT_S;
449 mem_types[MT_DEVICE_CACHED].prot_pte |= L_PTE_SHARED;
450 mem_types[MT_MEMORY].prot_sect |= PMD_SECT_S;
451 mem_types[MT_MEMORY].prot_pte |= L_PTE_SHARED;
452 mem_types[MT_MEMORY_NONCACHED].prot_sect |= PMD_SECT_S;
453 mem_types[MT_MEMORY_NONCACHED].prot_pte |= L_PTE_SHARED;
458 * Non-cacheable Normal - intended for memory areas that must
459 * not cause dirty cache line writebacks when used
461 if (cpu_arch >= CPU_ARCH_ARMv6) {
462 if (cpu_arch >= CPU_ARCH_ARMv7 && (cr & CR_TRE)) {
463 /* Non-cacheable Normal is XCB = 001 */
464 mem_types[MT_MEMORY_NONCACHED].prot_sect |=
467 /* For both ARMv6 and non-TEX-remapping ARMv7 */
468 mem_types[MT_MEMORY_NONCACHED].prot_sect |=
472 mem_types[MT_MEMORY_NONCACHED].prot_sect |= PMD_SECT_BUFFERABLE;
475 for (i = 0; i < 16; i++) {
476 unsigned long v = pgprot_val(protection_map[i]);
477 protection_map[i] = __pgprot(v | user_pgprot);
480 mem_types[MT_LOW_VECTORS].prot_pte |= vecs_pgprot;
481 mem_types[MT_HIGH_VECTORS].prot_pte |= vecs_pgprot;
483 pgprot_user = __pgprot(L_PTE_PRESENT | L_PTE_YOUNG | user_pgprot);
484 pgprot_kernel = __pgprot(L_PTE_PRESENT | L_PTE_YOUNG |
485 L_PTE_DIRTY | L_PTE_WRITE | kern_pgprot);
487 mem_types[MT_LOW_VECTORS].prot_l1 |= ecc_mask;
488 mem_types[MT_HIGH_VECTORS].prot_l1 |= ecc_mask;
489 mem_types[MT_MEMORY].prot_sect |= ecc_mask | cp->pmd;
490 mem_types[MT_MEMORY].prot_pte |= kern_pgprot;
491 mem_types[MT_MEMORY_NONCACHED].prot_sect |= ecc_mask;
492 mem_types[MT_ROM].prot_sect |= cp->pmd;
496 mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_WT;
500 mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_WB;
503 printk("Memory policy: ECC %sabled, Data cache %s\n",
504 ecc_mask ? "en" : "dis", cp->policy);
506 for (i = 0; i < ARRAY_SIZE(mem_types); i++) {
507 struct mem_type *t = &mem_types[i];
509 t->prot_l1 |= PMD_DOMAIN(t->domain);
511 t->prot_sect |= PMD_DOMAIN(t->domain);
515 #ifdef CONFIG_ARM_DMA_MEM_BUFFERABLE
516 pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn,
517 unsigned long size, pgprot_t vma_prot)
520 return pgprot_noncached(vma_prot);
521 else if (file->f_flags & O_SYNC)
522 return pgprot_writecombine(vma_prot);
525 EXPORT_SYMBOL(phys_mem_access_prot);
528 #define vectors_base() (vectors_high() ? 0xffff0000 : 0)
530 static void __init *early_alloc(unsigned long sz)
532 void *ptr = __va(memblock_alloc(sz, sz));
537 static pte_t * __init early_pte_alloc(pmd_t *pmd, unsigned long addr, unsigned long prot)
539 if (pmd_none(*pmd)) {
540 pte_t *pte = early_alloc(2 * PTRS_PER_PTE * sizeof(pte_t));
541 __pmd_populate(pmd, __pa(pte) | prot);
543 BUG_ON(pmd_bad(*pmd));
544 return pte_offset_kernel(pmd, addr);
547 static void __init alloc_init_pte(pmd_t *pmd, unsigned long addr,
548 unsigned long end, unsigned long pfn,
549 const struct mem_type *type)
551 pte_t *pte = early_pte_alloc(pmd, addr, type->prot_l1);
553 set_pte_ext(pte, pfn_pte(pfn, __pgprot(type->prot_pte)), 0);
555 } while (pte++, addr += PAGE_SIZE, addr != end);
558 static void __init alloc_init_section(pgd_t *pgd, unsigned long addr,
559 unsigned long end, unsigned long phys,
560 const struct mem_type *type)
562 pmd_t *pmd = pmd_offset(pgd, addr);
565 * Try a section mapping - end, addr and phys must all be aligned
566 * to a section boundary. Note that PMDs refer to the individual
567 * L1 entries, whereas PGDs refer to a group of L1 entries making
568 * up one logical pointer to an L2 table.
570 if (((addr | end | phys) & ~SECTION_MASK) == 0) {
573 if (addr & SECTION_SIZE)
577 *pmd = __pmd(phys | type->prot_sect);
578 phys += SECTION_SIZE;
579 } while (pmd++, addr += SECTION_SIZE, addr != end);
584 * No need to loop; pte's aren't interested in the
585 * individual L1 entries.
587 alloc_init_pte(pmd, addr, end, __phys_to_pfn(phys), type);
591 static void __init create_36bit_mapping(struct map_desc *md,
592 const struct mem_type *type)
594 unsigned long phys, addr, length, end;
598 phys = (unsigned long)__pfn_to_phys(md->pfn);
599 length = PAGE_ALIGN(md->length);
601 if (!(cpu_architecture() >= CPU_ARCH_ARMv6 || cpu_is_xsc3())) {
602 printk(KERN_ERR "MM: CPU does not support supersection "
603 "mapping for 0x%08llx at 0x%08lx\n",
604 __pfn_to_phys((u64)md->pfn), addr);
608 /* N.B. ARMv6 supersections are only defined to work with domain 0.
609 * Since domain assignments can in fact be arbitrary, the
610 * 'domain == 0' check below is required to insure that ARMv6
611 * supersections are only allocated for domain 0 regardless
612 * of the actual domain assignments in use.
615 printk(KERN_ERR "MM: invalid domain in supersection "
616 "mapping for 0x%08llx at 0x%08lx\n",
617 __pfn_to_phys((u64)md->pfn), addr);
621 if ((addr | length | __pfn_to_phys(md->pfn)) & ~SUPERSECTION_MASK) {
622 printk(KERN_ERR "MM: cannot create mapping for "
623 "0x%08llx at 0x%08lx invalid alignment\n",
624 __pfn_to_phys((u64)md->pfn), addr);
629 * Shift bits [35:32] of address into bits [23:20] of PMD
632 phys |= (((md->pfn >> (32 - PAGE_SHIFT)) & 0xF) << 20);
634 pgd = pgd_offset_k(addr);
637 pmd_t *pmd = pmd_offset(pgd, addr);
640 for (i = 0; i < 16; i++)
641 *pmd++ = __pmd(phys | type->prot_sect | PMD_SECT_SUPER);
643 addr += SUPERSECTION_SIZE;
644 phys += SUPERSECTION_SIZE;
645 pgd += SUPERSECTION_SIZE >> PGDIR_SHIFT;
646 } while (addr != end);
650 * Create the page directory entries and any necessary
651 * page tables for the mapping specified by `md'. We
652 * are able to cope here with varying sizes and address
653 * offsets, and we take full advantage of sections and
656 static void __init create_mapping(struct map_desc *md)
658 unsigned long phys, addr, length, end;
659 const struct mem_type *type;
662 if (md->virtual != vectors_base() && md->virtual < TASK_SIZE) {
663 printk(KERN_WARNING "BUG: not creating mapping for "
664 "0x%08llx at 0x%08lx in user region\n",
665 __pfn_to_phys((u64)md->pfn), md->virtual);
669 if ((md->type == MT_DEVICE || md->type == MT_ROM) &&
670 md->virtual >= PAGE_OFFSET && md->virtual < VMALLOC_END) {
671 printk(KERN_WARNING "BUG: mapping for 0x%08llx at 0x%08lx "
672 "overlaps vmalloc space\n",
673 __pfn_to_phys((u64)md->pfn), md->virtual);
676 type = &mem_types[md->type];
679 * Catch 36-bit addresses
681 if (md->pfn >= 0x100000) {
682 create_36bit_mapping(md, type);
686 addr = md->virtual & PAGE_MASK;
687 phys = (unsigned long)__pfn_to_phys(md->pfn);
688 length = PAGE_ALIGN(md->length + (md->virtual & ~PAGE_MASK));
690 if (type->prot_l1 == 0 && ((addr | phys | length) & ~SECTION_MASK)) {
691 printk(KERN_WARNING "BUG: map for 0x%08lx at 0x%08lx can not "
692 "be mapped using pages, ignoring.\n",
693 __pfn_to_phys(md->pfn), addr);
697 pgd = pgd_offset_k(addr);
700 unsigned long next = pgd_addr_end(addr, end);
702 alloc_init_section(pgd, addr, next, phys, type);
706 } while (pgd++, addr != end);
710 * Create the architecture specific mappings
712 void __init iotable_init(struct map_desc *io_desc, int nr)
716 for (i = 0; i < nr; i++)
717 create_mapping(io_desc + i);
720 #if defined(CONFIG_RK29_MEM_SIZE_M) && CONFIG_RK29_MEM_SIZE_M >= 1024
721 static void * __initdata vmalloc_min = (void *)(VMALLOC_END - SZ_256M);
723 static void * __initdata vmalloc_min = (void *)(VMALLOC_END - SZ_128M);
727 * vmalloc=size forces the vmalloc area to be exactly 'size'
728 * bytes. This can be used to increase (or decrease) the vmalloc
729 * area - the default is 128m.
731 static int __init early_vmalloc(char *arg)
733 unsigned long vmalloc_reserve = memparse(arg, NULL);
735 if (vmalloc_reserve < SZ_16M) {
736 vmalloc_reserve = SZ_16M;
738 "vmalloc area too small, limiting to %luMB\n",
739 vmalloc_reserve >> 20);
742 if (vmalloc_reserve > VMALLOC_END - (PAGE_OFFSET + SZ_32M)) {
743 vmalloc_reserve = VMALLOC_END - (PAGE_OFFSET + SZ_32M);
745 "vmalloc area is too big, limiting to %luMB\n",
746 vmalloc_reserve >> 20);
749 vmalloc_min = (void *)(VMALLOC_END - vmalloc_reserve);
752 early_param("vmalloc", early_vmalloc);
754 phys_addr_t lowmem_end_addr;
756 static void __init sanity_check_meminfo(void)
758 int i, j, highmem = 0;
760 lowmem_end_addr = __pa(vmalloc_min - 1) + 1;
762 for (i = 0, j = 0; i < meminfo.nr_banks; i++) {
763 struct membank *bank = &meminfo.bank[j];
764 *bank = meminfo.bank[i];
766 #ifdef CONFIG_HIGHMEM
767 if (__va(bank->start) > vmalloc_min ||
768 __va(bank->start) < (void *)PAGE_OFFSET)
771 bank->highmem = highmem;
774 * Split those memory banks which are partially overlapping
775 * the vmalloc area greatly simplifying things later.
777 if (__va(bank->start) < vmalloc_min &&
778 bank->size > vmalloc_min - __va(bank->start)) {
779 if (meminfo.nr_banks >= NR_BANKS) {
780 printk(KERN_CRIT "NR_BANKS too low, "
781 "ignoring high memory\n");
783 memmove(bank + 1, bank,
784 (meminfo.nr_banks - i) * sizeof(*bank));
787 bank[1].size -= vmalloc_min - __va(bank->start);
788 bank[1].start = __pa(vmalloc_min - 1) + 1;
789 bank[1].highmem = highmem = 1;
792 bank->size = vmalloc_min - __va(bank->start);
795 bank->highmem = highmem;
798 * Check whether this memory bank would entirely overlap
801 if (__va(bank->start) >= vmalloc_min ||
802 __va(bank->start) < (void *)PAGE_OFFSET) {
803 printk(KERN_NOTICE "Ignoring RAM at %.8lx-%.8lx "
804 "(vmalloc region overlap).\n",
805 bank->start, bank->start + bank->size - 1);
810 * Check whether this memory bank would partially overlap
813 if (__va(bank->start + bank->size) > vmalloc_min ||
814 __va(bank->start + bank->size) < __va(bank->start)) {
815 unsigned long newsize = vmalloc_min - __va(bank->start);
816 printk(KERN_NOTICE "Truncating RAM at %.8lx-%.8lx "
817 "to -%.8lx (vmalloc region overlap).\n",
818 bank->start, bank->start + bank->size - 1,
819 bank->start + newsize - 1);
820 bank->size = newsize;
825 #ifdef CONFIG_HIGHMEM
827 const char *reason = NULL;
829 if (cache_is_vipt_aliasing()) {
831 * Interactions between kmap and other mappings
832 * make highmem support with aliasing VIPT caches
835 reason = "with VIPT aliasing cache";
837 } else if (tlb_ops_need_broadcast()) {
839 * kmap_high needs to occasionally flush TLB entries,
840 * however, if the TLB entries need to be broadcast
842 * kmap_high(irqs off)->flush_all_zero_pkmaps->
843 * flush_tlb_kernel_range->smp_call_function_many
844 * (must not be called with irqs off)
846 reason = "without hardware TLB ops broadcasting";
850 printk(KERN_CRIT "HIGHMEM is not supported %s, ignoring high memory\n",
852 while (j > 0 && meminfo.bank[j - 1].highmem)
857 meminfo.nr_banks = j;
860 static inline void prepare_page_table(void)
866 * Clear out all the mappings below the kernel image.
868 for (addr = 0; addr < MODULES_VADDR; addr += PGDIR_SIZE)
869 pmd_clear(pmd_off_k(addr));
871 #ifdef CONFIG_XIP_KERNEL
872 /* The XIP kernel is mapped in the module area -- skip over it */
873 addr = ((unsigned long)_etext + PGDIR_SIZE - 1) & PGDIR_MASK;
875 for ( ; addr < PAGE_OFFSET; addr += PGDIR_SIZE)
876 pmd_clear(pmd_off_k(addr));
879 * Find the end of the first block of lowmem. This is complicated
880 * when we use memblock.
882 end = memblock.memory.region[0].base + memblock.memory.region[0].size;
883 if (end >= lowmem_end_addr)
884 end = lowmem_end_addr;
887 * Clear out all the kernel space mappings, except for the first
888 * memory bank, up to the end of the vmalloc region.
890 for (addr = __phys_to_virt(end);
891 addr < VMALLOC_END; addr += PGDIR_SIZE)
892 pmd_clear(pmd_off_k(addr));
896 * Reserve the special regions of memory
898 void __init arm_mm_memblock_reserve(void)
901 * Reserve the page tables. These are already in use,
902 * and can only be in node 0.
904 memblock_reserve(__pa(swapper_pg_dir), PTRS_PER_PGD * sizeof(pgd_t));
908 * Because of the SA1111 DMA bug, we want to preserve our
909 * precious DMA-able memory...
911 memblock_reserve(PHYS_OFFSET, __pa(swapper_pg_dir) - PHYS_OFFSET);
916 * Set up device the mappings. Since we clear out the page tables for all
917 * mappings above VMALLOC_END, we will remove any debug device mappings.
918 * This means you have to be careful how you debug this function, or any
919 * called function. This means you can't use any function or debugging
920 * method which may touch any device, otherwise the kernel _will_ crash.
922 static void __init devicemaps_init(struct machine_desc *mdesc)
929 * Allocate the vector page early.
931 vectors = early_alloc(PAGE_SIZE);
933 for (addr = VMALLOC_END; addr; addr += PGDIR_SIZE)
934 pmd_clear(pmd_off_k(addr));
937 * Map the kernel if it is XIP.
938 * It is always first in the modulearea.
940 #ifdef CONFIG_XIP_KERNEL
941 map.pfn = __phys_to_pfn(CONFIG_XIP_PHYS_ADDR & SECTION_MASK);
942 map.virtual = MODULES_VADDR;
943 map.length = ((unsigned long)_etext - map.virtual + ~SECTION_MASK) & SECTION_MASK;
945 create_mapping(&map);
949 * Map the cache flushing regions.
952 map.pfn = __phys_to_pfn(FLUSH_BASE_PHYS);
953 map.virtual = FLUSH_BASE;
955 map.type = MT_CACHECLEAN;
956 create_mapping(&map);
958 #ifdef FLUSH_BASE_MINICACHE
959 map.pfn = __phys_to_pfn(FLUSH_BASE_PHYS + SZ_1M);
960 map.virtual = FLUSH_BASE_MINICACHE;
962 map.type = MT_MINICLEAN;
963 create_mapping(&map);
967 * Create a mapping for the machine vectors at the high-vectors
968 * location (0xffff0000). If we aren't using high-vectors, also
969 * create a mapping at the low-vectors virtual address.
971 map.pfn = __phys_to_pfn(virt_to_phys(vectors));
972 map.virtual = 0xffff0000;
973 map.length = PAGE_SIZE;
974 map.type = MT_HIGH_VECTORS;
975 create_mapping(&map);
977 if (!vectors_high()) {
979 map.type = MT_LOW_VECTORS;
980 create_mapping(&map);
984 * Ask the machine support to map in the statically mapped devices.
990 * Finally flush the caches and tlb to ensure that we're in a
991 * consistent state wrt the writebuffer. This also ensures that
992 * any write-allocated cache lines in the vector page are written
993 * back. After this point, we can start to touch devices again.
995 local_flush_tlb_all();
999 static void __init kmap_init(void)
1001 #ifdef CONFIG_HIGHMEM
1002 pkmap_page_table = early_pte_alloc(pmd_off_k(PKMAP_BASE),
1003 PKMAP_BASE, _PAGE_KERNEL_TABLE);
1007 static void __init map_lowmem(void)
1011 /* Map all the lowmem memory banks. */
1012 for (i = 0; i < memblock.memory.cnt; i++) {
1013 phys_addr_t start = memblock.memory.region[i].base;
1014 phys_addr_t end = start + memblock.memory.region[i].size;
1015 struct map_desc map;
1017 if (end >= lowmem_end_addr)
1018 end = lowmem_end_addr;
1022 map.pfn = __phys_to_pfn(start);
1023 map.virtual = __phys_to_virt(start);
1024 map.length = end - start;
1025 map.type = MT_MEMORY;
1027 create_mapping(&map);
1031 static int __init meminfo_cmp(const void *_a, const void *_b)
1033 const struct membank *a = _a, *b = _b;
1034 long cmp = bank_pfn_start(a) - bank_pfn_start(b);
1035 return cmp < 0 ? -1 : cmp > 0 ? 1 : 0;
1039 * paging_init() sets up the page tables, initialises the zone memory
1040 * maps, and sets up the zero page, bad page and bad page tables.
1042 void __init paging_init(struct machine_desc *mdesc)
1046 sort(&meminfo.bank, meminfo.nr_banks, sizeof(meminfo.bank[0]), meminfo_cmp, NULL);
1048 build_mem_type_table();
1049 sanity_check_meminfo();
1050 prepare_page_table();
1052 devicemaps_init(mdesc);
1055 top_pmd = pmd_off_k(0xffff0000);
1057 /* allocate the zero page. */
1058 zero_page = early_alloc(PAGE_SIZE);
1062 empty_zero_page = virt_to_page(zero_page);
1063 __flush_dcache_page(NULL, empty_zero_page);
1067 * In order to soft-boot, we need to insert a 1:1 mapping in place of
1068 * the user-mode pages. This will then ensure that we have predictable
1069 * results when turning the mmu off
1071 void setup_mm_for_reboot(char mode)
1073 unsigned long base_pmdval;
1078 * We need to access to user-mode page tables here. For kernel threads
1079 * we don't have any user-mode mappings so we use the context that we
1082 pgd = current->active_mm->pgd;
1084 base_pmdval = PMD_SECT_AP_WRITE | PMD_SECT_AP_READ | PMD_TYPE_SECT;
1085 if (cpu_architecture() <= CPU_ARCH_ARMv5TEJ && !cpu_is_xscale())
1086 base_pmdval |= PMD_BIT4;
1088 for (i = 0; i < FIRST_USER_PGD_NR + USER_PTRS_PER_PGD; i++, pgd++) {
1089 unsigned long pmdval = (i << PGDIR_SHIFT) | base_pmdval;
1092 pmd = pmd_off(pgd, i << PGDIR_SHIFT);
1093 pmd[0] = __pmd(pmdval);
1094 pmd[1] = __pmd(pmdval + (1 << (PGDIR_SHIFT - 1)));
1095 flush_pmd_entry(pmd);
1098 local_flush_tlb_all();