2 * linux/arch/arm/mm/dma-mapping.c
4 * Copyright (C) 2000-2004 Russell King
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 * DMA uncached mapping support.
12 #include <linux/module.h>
14 #include <linux/gfp.h>
15 #include <linux/errno.h>
16 #include <linux/list.h>
17 #include <linux/init.h>
18 #include <linux/device.h>
19 #include <linux/dma-mapping.h>
20 #include <linux/dma-contiguous.h>
21 #include <linux/highmem.h>
22 #include <linux/memblock.h>
23 #include <linux/slab.h>
24 #include <linux/iommu.h>
26 #include <linux/vmalloc.h>
27 #include <linux/sizes.h>
29 #include <asm/memory.h>
30 #include <asm/highmem.h>
31 #include <asm/cacheflush.h>
32 #include <asm/tlbflush.h>
33 #include <asm/mach/arch.h>
34 #include <asm/dma-iommu.h>
35 #include <asm/mach/map.h>
36 #include <asm/system_info.h>
37 #include <asm/dma-contiguous.h>
42 * The DMA API is built upon the notion of "buffer ownership". A buffer
43 * is either exclusively owned by the CPU (and therefore may be accessed
44 * by it) or exclusively owned by the DMA device. These helper functions
45 * represent the transitions between these two ownership states.
47 * Note, however, that on later ARMs, this notion does not work due to
48 * speculative prefetches. We model our approach on the assumption that
49 * the CPU does do speculative prefetches, which means we clean caches
50 * before transfers and delay cache invalidation until transfer completion.
53 static void __dma_page_cpu_to_dev(struct page *, unsigned long,
54 size_t, enum dma_data_direction);
55 static void __dma_page_dev_to_cpu(struct page *, unsigned long,
56 size_t, enum dma_data_direction);
59 * arm_dma_map_page - map a portion of a page for streaming DMA
60 * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices
61 * @page: page that buffer resides in
62 * @offset: offset into page for start of buffer
63 * @size: size of buffer to map
64 * @dir: DMA transfer direction
66 * Ensure that any data held in the cache is appropriately discarded
69 * The device owns this memory once this call has completed. The CPU
70 * can regain ownership by calling dma_unmap_page().
72 static dma_addr_t arm_dma_map_page(struct device *dev, struct page *page,
73 unsigned long offset, size_t size, enum dma_data_direction dir,
74 struct dma_attrs *attrs)
76 if (!dma_get_attr(DMA_ATTR_SKIP_CPU_SYNC, attrs))
77 __dma_page_cpu_to_dev(page, offset, size, dir);
78 return pfn_to_dma(dev, page_to_pfn(page)) + offset;
81 static dma_addr_t arm_coherent_dma_map_page(struct device *dev, struct page *page,
82 unsigned long offset, size_t size, enum dma_data_direction dir,
83 struct dma_attrs *attrs)
85 return pfn_to_dma(dev, page_to_pfn(page)) + offset;
89 * arm_dma_unmap_page - unmap a buffer previously mapped through dma_map_page()
90 * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices
91 * @handle: DMA address of buffer
92 * @size: size of buffer (same as passed to dma_map_page)
93 * @dir: DMA transfer direction (same as passed to dma_map_page)
95 * Unmap a page streaming mode DMA translation. The handle and size
96 * must match what was provided in the previous dma_map_page() call.
97 * All other usages are undefined.
99 * After this call, reads by the CPU to the buffer are guaranteed to see
100 * whatever the device wrote there.
102 static void arm_dma_unmap_page(struct device *dev, dma_addr_t handle,
103 size_t size, enum dma_data_direction dir,
104 struct dma_attrs *attrs)
106 if (!dma_get_attr(DMA_ATTR_SKIP_CPU_SYNC, attrs))
107 __dma_page_dev_to_cpu(pfn_to_page(dma_to_pfn(dev, handle)),
108 handle & ~PAGE_MASK, size, dir);
111 static void arm_dma_sync_single_for_cpu(struct device *dev,
112 dma_addr_t handle, size_t size, enum dma_data_direction dir)
114 unsigned int offset = handle & (PAGE_SIZE - 1);
115 struct page *page = pfn_to_page(dma_to_pfn(dev, handle-offset));
116 __dma_page_dev_to_cpu(page, offset, size, dir);
119 static void arm_dma_sync_single_for_device(struct device *dev,
120 dma_addr_t handle, size_t size, enum dma_data_direction dir)
122 unsigned int offset = handle & (PAGE_SIZE - 1);
123 struct page *page = pfn_to_page(dma_to_pfn(dev, handle-offset));
124 __dma_page_cpu_to_dev(page, offset, size, dir);
127 struct dma_map_ops arm_dma_ops = {
128 .alloc = arm_dma_alloc,
129 .free = arm_dma_free,
130 .mmap = arm_dma_mmap,
131 .get_sgtable = arm_dma_get_sgtable,
132 .map_page = arm_dma_map_page,
133 .unmap_page = arm_dma_unmap_page,
134 .map_sg = arm_dma_map_sg,
135 .unmap_sg = arm_dma_unmap_sg,
136 .sync_single_for_cpu = arm_dma_sync_single_for_cpu,
137 .sync_single_for_device = arm_dma_sync_single_for_device,
138 .sync_sg_for_cpu = arm_dma_sync_sg_for_cpu,
139 .sync_sg_for_device = arm_dma_sync_sg_for_device,
140 .set_dma_mask = arm_dma_set_mask,
142 EXPORT_SYMBOL(arm_dma_ops);
144 static void *arm_coherent_dma_alloc(struct device *dev, size_t size,
145 dma_addr_t *handle, gfp_t gfp, struct dma_attrs *attrs);
146 static void arm_coherent_dma_free(struct device *dev, size_t size, void *cpu_addr,
147 dma_addr_t handle, struct dma_attrs *attrs);
149 struct dma_map_ops arm_coherent_dma_ops = {
150 .alloc = arm_coherent_dma_alloc,
151 .free = arm_coherent_dma_free,
152 .mmap = arm_dma_mmap,
153 .get_sgtable = arm_dma_get_sgtable,
154 .map_page = arm_coherent_dma_map_page,
155 .map_sg = arm_dma_map_sg,
156 .set_dma_mask = arm_dma_set_mask,
158 EXPORT_SYMBOL(arm_coherent_dma_ops);
160 static u64 get_coherent_dma_mask(struct device *dev)
162 u64 mask = (u64)arm_dma_limit;
165 mask = dev->coherent_dma_mask;
168 * Sanity check the DMA mask - it must be non-zero, and
169 * must be able to be satisfied by a DMA allocation.
172 dev_warn(dev, "coherent DMA mask is unset\n");
176 if ((~mask) & (u64)arm_dma_limit) {
177 dev_warn(dev, "coherent DMA mask %#llx is smaller "
178 "than system GFP_DMA mask %#llx\n",
179 mask, (u64)arm_dma_limit);
187 static void __dma_clear_buffer(struct page *page, size_t size)
190 * Ensure that the allocated pages are zeroed, and that any data
191 * lurking in the kernel direct-mapped region is invalidated.
193 if (PageHighMem(page)) {
194 phys_addr_t base = __pfn_to_phys(page_to_pfn(page));
195 phys_addr_t end = base + size;
197 void *ptr = kmap_atomic(page);
198 memset(ptr, 0, PAGE_SIZE);
199 dmac_flush_range(ptr, ptr + PAGE_SIZE);
204 outer_flush_range(base, end);
206 void *ptr = page_address(page);
207 memset(ptr, 0, size);
208 dmac_flush_range(ptr, ptr + size);
209 outer_flush_range(__pa(ptr), __pa(ptr) + size);
214 * Allocate a DMA buffer for 'dev' of size 'size' using the
215 * specified gfp mask. Note that 'size' must be page aligned.
217 static struct page *__dma_alloc_buffer(struct device *dev, size_t size, gfp_t gfp)
219 unsigned long order = get_order(size);
220 struct page *page, *p, *e;
222 page = alloc_pages(gfp, order);
227 * Now split the huge page and free the excess pages
229 split_page(page, order);
230 for (p = page + (size >> PAGE_SHIFT), e = page + (1 << order); p < e; p++)
233 __dma_clear_buffer(page, size);
239 * Free a DMA buffer. 'size' must be page aligned.
241 static void __dma_free_buffer(struct page *page, size_t size)
243 struct page *e = page + (size >> PAGE_SHIFT);
252 #ifdef CONFIG_HUGETLB_PAGE
253 #warning ARM Coherent DMA allocator does not (yet) support huge TLB
256 static void *__alloc_from_contiguous(struct device *dev, size_t size,
257 pgprot_t prot, struct page **ret_page,
260 static void *__alloc_remap_buffer(struct device *dev, size_t size, gfp_t gfp,
261 pgprot_t prot, struct page **ret_page,
265 __dma_alloc_remap(struct page *page, size_t size, gfp_t gfp, pgprot_t prot,
268 struct vm_struct *area;
272 * DMA allocation can be mapped to user space, so lets
273 * set VM_USERMAP flags too.
275 area = get_vm_area_caller(size, VM_ARM_DMA_CONSISTENT | VM_USERMAP,
279 addr = (unsigned long)area->addr;
280 area->phys_addr = __pfn_to_phys(page_to_pfn(page));
282 if (ioremap_page_range(addr, addr + size, area->phys_addr, prot)) {
283 vunmap((void *)addr);
289 static void __dma_free_remap(void *cpu_addr, size_t size)
291 unsigned int flags = VM_ARM_DMA_CONSISTENT | VM_USERMAP;
292 struct vm_struct *area = find_vm_area(cpu_addr);
293 if (!area || (area->flags & flags) != flags) {
294 WARN(1, "trying to free invalid coherent area: %p\n", cpu_addr);
297 unmap_kernel_range((unsigned long)cpu_addr, size);
301 #define DEFAULT_DMA_COHERENT_POOL_SIZE SZ_256K
306 unsigned long *bitmap;
307 unsigned long nr_pages;
312 static struct dma_pool atomic_pool = {
313 .size = DEFAULT_DMA_COHERENT_POOL_SIZE,
316 static int __init early_coherent_pool(char *p)
318 atomic_pool.size = memparse(p, &p);
321 early_param("coherent_pool", early_coherent_pool);
323 void __init init_dma_coherent_pool_size(unsigned long size)
326 * Catch any attempt to set the pool size too late.
328 BUG_ON(atomic_pool.vaddr);
331 * Set architecture specific coherent pool size only if
332 * it has not been changed by kernel command line parameter.
334 if (atomic_pool.size == DEFAULT_DMA_COHERENT_POOL_SIZE)
335 atomic_pool.size = size;
339 * Initialise the coherent pool for atomic allocations.
341 static int __init atomic_pool_init(void)
343 struct dma_pool *pool = &atomic_pool;
344 pgprot_t prot = pgprot_dmacoherent(pgprot_kernel);
345 gfp_t gfp = GFP_KERNEL | GFP_DMA;
346 unsigned long nr_pages = pool->size >> PAGE_SHIFT;
347 unsigned long *bitmap;
351 int bitmap_size = BITS_TO_LONGS(nr_pages) * sizeof(long);
353 bitmap = kzalloc(bitmap_size, GFP_KERNEL);
357 pages = kzalloc(nr_pages * sizeof(struct page *), GFP_KERNEL);
361 if (IS_ENABLED(CONFIG_DMA_CMA))
362 ptr = __alloc_from_contiguous(NULL, pool->size, prot, &page,
365 ptr = __alloc_remap_buffer(NULL, pool->size, gfp, prot, &page,
370 for (i = 0; i < nr_pages; i++)
373 spin_lock_init(&pool->lock);
376 pool->bitmap = bitmap;
377 pool->nr_pages = nr_pages;
378 pr_info("DMA: preallocated %u KiB pool for atomic coherent allocations\n",
379 (unsigned)pool->size / 1024);
387 pr_err("DMA: failed to allocate %u KiB pool for atomic coherent allocation\n",
388 (unsigned)pool->size / 1024);
392 * CMA is activated by core_initcall, so we must be called after it.
394 postcore_initcall(atomic_pool_init);
396 struct dma_contig_early_reserve {
401 static struct dma_contig_early_reserve dma_mmu_remap[MAX_CMA_AREAS] __initdata;
403 static int dma_mmu_remap_num __initdata;
405 void __init dma_contiguous_early_fixup(phys_addr_t base, unsigned long size)
407 dma_mmu_remap[dma_mmu_remap_num].base = base;
408 dma_mmu_remap[dma_mmu_remap_num].size = size;
412 void __init dma_contiguous_remap(void)
415 for (i = 0; i < dma_mmu_remap_num; i++) {
416 phys_addr_t start = dma_mmu_remap[i].base;
417 phys_addr_t end = start + dma_mmu_remap[i].size;
421 if (end > arm_lowmem_limit)
422 end = arm_lowmem_limit;
426 map.pfn = __phys_to_pfn(start);
427 map.virtual = __phys_to_virt(start);
428 map.length = end - start;
429 map.type = MT_MEMORY_DMA_READY;
432 * Clear previous low-memory mapping
434 for (addr = __phys_to_virt(start); addr < __phys_to_virt(end);
436 pmd_clear(pmd_off_k(addr));
438 iotable_init(&map, 1);
442 static int __dma_update_pte(pte_t *pte, pgtable_t token, unsigned long addr,
445 struct page *page = virt_to_page(addr);
446 pgprot_t prot = *(pgprot_t *)data;
448 set_pte_ext(pte, mk_pte(page, prot), 0);
452 static void __dma_remap(struct page *page, size_t size, pgprot_t prot)
454 unsigned long start = (unsigned long) page_address(page);
455 unsigned end = start + size;
457 apply_to_page_range(&init_mm, start, size, __dma_update_pte, &prot);
458 flush_tlb_kernel_range(start, end);
461 static void *__alloc_remap_buffer(struct device *dev, size_t size, gfp_t gfp,
462 pgprot_t prot, struct page **ret_page,
467 page = __dma_alloc_buffer(dev, size, gfp);
471 ptr = __dma_alloc_remap(page, size, gfp, prot, caller);
473 __dma_free_buffer(page, size);
481 static void *__alloc_from_pool(size_t size, struct page **ret_page)
483 struct dma_pool *pool = &atomic_pool;
484 unsigned int count = PAGE_ALIGN(size) >> PAGE_SHIFT;
488 unsigned long align_mask;
491 WARN(1, "coherent pool not initialised!\n");
496 * Align the region allocation - allocations from pool are rather
497 * small, so align them to their order in pages, minimum is a page
498 * size. This helps reduce fragmentation of the DMA space.
500 align_mask = (1 << get_order(size)) - 1;
502 spin_lock_irqsave(&pool->lock, flags);
503 pageno = bitmap_find_next_zero_area(pool->bitmap, pool->nr_pages,
504 0, count, align_mask);
505 if (pageno < pool->nr_pages) {
506 bitmap_set(pool->bitmap, pageno, count);
507 ptr = pool->vaddr + PAGE_SIZE * pageno;
508 *ret_page = pool->pages[pageno];
510 pr_err_once("ERROR: %u KiB atomic DMA coherent pool is too small!\n"
511 "Please increase it with coherent_pool= kernel parameter!\n",
512 (unsigned)pool->size / 1024);
514 spin_unlock_irqrestore(&pool->lock, flags);
519 static bool __in_atomic_pool(void *start, size_t size)
521 struct dma_pool *pool = &atomic_pool;
522 void *end = start + size;
523 void *pool_start = pool->vaddr;
524 void *pool_end = pool->vaddr + pool->size;
526 if (start < pool_start || start >= pool_end)
532 WARN(1, "Wrong coherent size(%p-%p) from atomic pool(%p-%p)\n",
533 start, end - 1, pool_start, pool_end - 1);
538 static int __free_from_pool(void *start, size_t size)
540 struct dma_pool *pool = &atomic_pool;
541 unsigned long pageno, count;
544 if (!__in_atomic_pool(start, size))
547 pageno = (start - pool->vaddr) >> PAGE_SHIFT;
548 count = size >> PAGE_SHIFT;
550 spin_lock_irqsave(&pool->lock, flags);
551 bitmap_clear(pool->bitmap, pageno, count);
552 spin_unlock_irqrestore(&pool->lock, flags);
557 static void *__alloc_from_contiguous(struct device *dev, size_t size,
558 pgprot_t prot, struct page **ret_page,
561 unsigned long order = get_order(size);
562 size_t count = size >> PAGE_SHIFT;
566 page = dma_alloc_from_contiguous(dev, count, order);
570 __dma_clear_buffer(page, size);
572 if (PageHighMem(page)) {
573 ptr = __dma_alloc_remap(page, size, GFP_KERNEL, prot, caller);
575 dma_release_from_contiguous(dev, page, count);
579 __dma_remap(page, size, prot);
580 ptr = page_address(page);
586 static void __free_from_contiguous(struct device *dev, struct page *page,
587 void *cpu_addr, size_t size)
589 if (PageHighMem(page))
590 __dma_free_remap(cpu_addr, size);
592 __dma_remap(page, size, pgprot_kernel);
593 dma_release_from_contiguous(dev, page, size >> PAGE_SHIFT);
596 static inline pgprot_t __get_dma_pgprot(struct dma_attrs *attrs, pgprot_t prot)
598 prot = dma_get_attr(DMA_ATTR_WRITE_COMBINE, attrs) ?
599 pgprot_writecombine(prot) :
600 pgprot_dmacoherent(prot);
606 #else /* !CONFIG_MMU */
610 #define __get_dma_pgprot(attrs, prot) __pgprot(0)
611 #define __alloc_remap_buffer(dev, size, gfp, prot, ret, c) NULL
612 #define __alloc_from_pool(size, ret_page) NULL
613 #define __alloc_from_contiguous(dev, size, prot, ret, c) NULL
614 #define __free_from_pool(cpu_addr, size) 0
615 #define __free_from_contiguous(dev, page, cpu_addr, size) do { } while (0)
616 #define __dma_free_remap(cpu_addr, size) do { } while (0)
618 #endif /* CONFIG_MMU */
620 static void *__alloc_simple_buffer(struct device *dev, size_t size, gfp_t gfp,
621 struct page **ret_page)
624 page = __dma_alloc_buffer(dev, size, gfp);
629 return page_address(page);
634 static void *__dma_alloc(struct device *dev, size_t size, dma_addr_t *handle,
635 gfp_t gfp, pgprot_t prot, bool is_coherent, const void *caller)
637 u64 mask = get_coherent_dma_mask(dev);
638 struct page *page = NULL;
641 #ifdef CONFIG_DMA_API_DEBUG
642 u64 limit = (mask + 1) & ~mask;
643 if (limit && size >= limit) {
644 dev_warn(dev, "coherent allocation too big (requested %#x mask %#llx)\n",
653 if (mask < 0xffffffffULL)
657 * Following is a work-around (a.k.a. hack) to prevent pages
658 * with __GFP_COMP being passed to split_page() which cannot
659 * handle them. The real problem is that this flag probably
660 * should be 0 on ARM as it is not supported on this
661 * platform; see CONFIG_HUGETLBFS.
663 gfp &= ~(__GFP_COMP);
665 *handle = DMA_ERROR_CODE;
666 size = PAGE_ALIGN(size);
668 if (is_coherent || nommu())
669 addr = __alloc_simple_buffer(dev, size, gfp, &page);
670 else if (!(gfp & __GFP_WAIT))
671 addr = __alloc_from_pool(size, &page);
672 else if (!IS_ENABLED(CONFIG_DMA_CMA))
673 addr = __alloc_remap_buffer(dev, size, gfp, prot, &page, caller);
675 addr = __alloc_from_contiguous(dev, size, prot, &page, caller);
678 *handle = pfn_to_dma(dev, page_to_pfn(page));
684 * Allocate DMA-coherent memory space and return both the kernel remapped
685 * virtual and bus address for that space.
687 void *arm_dma_alloc(struct device *dev, size_t size, dma_addr_t *handle,
688 gfp_t gfp, struct dma_attrs *attrs)
690 pgprot_t prot = __get_dma_pgprot(attrs, pgprot_kernel);
693 if (dma_alloc_from_coherent(dev, size, handle, &memory))
696 return __dma_alloc(dev, size, handle, gfp, prot, false,
697 __builtin_return_address(0));
700 static void *arm_coherent_dma_alloc(struct device *dev, size_t size,
701 dma_addr_t *handle, gfp_t gfp, struct dma_attrs *attrs)
703 pgprot_t prot = __get_dma_pgprot(attrs, pgprot_kernel);
706 if (dma_alloc_from_coherent(dev, size, handle, &memory))
709 return __dma_alloc(dev, size, handle, gfp, prot, true,
710 __builtin_return_address(0));
714 * Create userspace mapping for the DMA-coherent memory.
716 int arm_dma_mmap(struct device *dev, struct vm_area_struct *vma,
717 void *cpu_addr, dma_addr_t dma_addr, size_t size,
718 struct dma_attrs *attrs)
722 unsigned long nr_vma_pages = (vma->vm_end - vma->vm_start) >> PAGE_SHIFT;
723 unsigned long nr_pages = PAGE_ALIGN(size) >> PAGE_SHIFT;
724 unsigned long pfn = dma_to_pfn(dev, dma_addr);
725 unsigned long off = vma->vm_pgoff;
727 vma->vm_page_prot = __get_dma_pgprot(attrs, vma->vm_page_prot);
729 if (dma_mmap_from_coherent(dev, vma, cpu_addr, size, &ret))
732 if (off < nr_pages && nr_vma_pages <= (nr_pages - off)) {
733 ret = remap_pfn_range(vma, vma->vm_start,
735 vma->vm_end - vma->vm_start,
738 #endif /* CONFIG_MMU */
744 * Free a buffer as defined by the above mapping.
746 static void __arm_dma_free(struct device *dev, size_t size, void *cpu_addr,
747 dma_addr_t handle, struct dma_attrs *attrs,
750 struct page *page = pfn_to_page(dma_to_pfn(dev, handle));
752 if (dma_release_from_coherent(dev, get_order(size), cpu_addr))
755 size = PAGE_ALIGN(size);
757 if (is_coherent || nommu()) {
758 __dma_free_buffer(page, size);
759 } else if (__free_from_pool(cpu_addr, size)) {
761 } else if (!IS_ENABLED(CONFIG_DMA_CMA)) {
762 __dma_free_remap(cpu_addr, size);
763 __dma_free_buffer(page, size);
766 * Non-atomic allocations cannot be freed with IRQs disabled
768 WARN_ON(irqs_disabled());
769 __free_from_contiguous(dev, page, cpu_addr, size);
773 void arm_dma_free(struct device *dev, size_t size, void *cpu_addr,
774 dma_addr_t handle, struct dma_attrs *attrs)
776 __arm_dma_free(dev, size, cpu_addr, handle, attrs, false);
779 static void arm_coherent_dma_free(struct device *dev, size_t size, void *cpu_addr,
780 dma_addr_t handle, struct dma_attrs *attrs)
782 __arm_dma_free(dev, size, cpu_addr, handle, attrs, true);
785 int arm_dma_get_sgtable(struct device *dev, struct sg_table *sgt,
786 void *cpu_addr, dma_addr_t handle, size_t size,
787 struct dma_attrs *attrs)
789 struct page *page = pfn_to_page(dma_to_pfn(dev, handle));
792 ret = sg_alloc_table(sgt, 1, GFP_KERNEL);
796 sg_set_page(sgt->sgl, page, PAGE_ALIGN(size), 0);
800 static void dma_cache_maint_page(struct page *page, unsigned long offset,
801 size_t size, enum dma_data_direction dir,
802 void (*op)(const void *, size_t, int))
807 pfn = page_to_pfn(page) + offset / PAGE_SIZE;
811 * A single sg entry may refer to multiple physically contiguous
812 * pages. But we still need to process highmem pages individually.
813 * If highmem is not configured then the bulk of this loop gets
820 page = pfn_to_page(pfn);
822 if (PageHighMem(page)) {
823 if (len + offset > PAGE_SIZE)
824 len = PAGE_SIZE - offset;
826 if (cache_is_vipt_nonaliasing()) {
827 vaddr = kmap_atomic(page);
828 op(vaddr + offset, len, dir);
829 kunmap_atomic(vaddr);
831 vaddr = kmap_high_get(page);
833 op(vaddr + offset, len, dir);
838 vaddr = page_address(page) + offset;
848 * Make an area consistent for devices.
849 * Note: Drivers should NOT use this function directly, as it will break
850 * platforms with CONFIG_DMABOUNCE.
851 * Use the driver DMA support - see dma-mapping.h (dma_sync_*)
853 static void __dma_page_cpu_to_dev(struct page *page, unsigned long off,
854 size_t size, enum dma_data_direction dir)
858 dma_cache_maint_page(page, off, size, dir, dmac_map_area);
860 paddr = page_to_phys(page) + off;
861 if (dir == DMA_FROM_DEVICE) {
862 outer_inv_range(paddr, paddr + size);
864 outer_clean_range(paddr, paddr + size);
866 /* FIXME: non-speculating: flush on bidirectional mappings? */
869 static void __dma_page_dev_to_cpu(struct page *page, unsigned long off,
870 size_t size, enum dma_data_direction dir)
872 unsigned long paddr = page_to_phys(page) + off;
874 /* FIXME: non-speculating: not required */
875 /* don't bother invalidating if DMA to device */
876 if (dir != DMA_TO_DEVICE)
877 outer_inv_range(paddr, paddr + size);
879 dma_cache_maint_page(page, off, size, dir, dmac_unmap_area);
882 * Mark the D-cache clean for these pages to avoid extra flushing.
884 if (dir != DMA_TO_DEVICE && size >= PAGE_SIZE) {
888 pfn = page_to_pfn(page) + off / PAGE_SIZE;
892 left -= PAGE_SIZE - off;
894 while (left >= PAGE_SIZE) {
895 page = pfn_to_page(pfn++);
896 set_bit(PG_dcache_clean, &page->flags);
903 * arm_dma_map_sg - map a set of SG buffers for streaming mode DMA
904 * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices
905 * @sg: list of buffers
906 * @nents: number of buffers to map
907 * @dir: DMA transfer direction
909 * Map a set of buffers described by scatterlist in streaming mode for DMA.
910 * This is the scatter-gather version of the dma_map_single interface.
911 * Here the scatter gather list elements are each tagged with the
912 * appropriate dma address and length. They are obtained via
913 * sg_dma_{address,length}.
915 * Device ownership issues as mentioned for dma_map_single are the same
918 int arm_dma_map_sg(struct device *dev, struct scatterlist *sg, int nents,
919 enum dma_data_direction dir, struct dma_attrs *attrs)
921 struct dma_map_ops *ops = get_dma_ops(dev);
922 struct scatterlist *s;
925 for_each_sg(sg, s, nents, i) {
926 #ifdef CONFIG_NEED_SG_DMA_LENGTH
927 s->dma_length = s->length;
929 s->dma_address = ops->map_page(dev, sg_page(s), s->offset,
930 s->length, dir, attrs);
931 if (dma_mapping_error(dev, s->dma_address))
937 for_each_sg(sg, s, i, j)
938 ops->unmap_page(dev, sg_dma_address(s), sg_dma_len(s), dir, attrs);
943 * arm_dma_unmap_sg - unmap a set of SG buffers mapped by dma_map_sg
944 * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices
945 * @sg: list of buffers
946 * @nents: number of buffers to unmap (same as was passed to dma_map_sg)
947 * @dir: DMA transfer direction (same as was passed to dma_map_sg)
949 * Unmap a set of streaming mode DMA translations. Again, CPU access
950 * rules concerning calls here are the same as for dma_unmap_single().
952 void arm_dma_unmap_sg(struct device *dev, struct scatterlist *sg, int nents,
953 enum dma_data_direction dir, struct dma_attrs *attrs)
955 struct dma_map_ops *ops = get_dma_ops(dev);
956 struct scatterlist *s;
960 for_each_sg(sg, s, nents, i)
961 ops->unmap_page(dev, sg_dma_address(s), sg_dma_len(s), dir, attrs);
965 * arm_dma_sync_sg_for_cpu
966 * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices
967 * @sg: list of buffers
968 * @nents: number of buffers to map (returned from dma_map_sg)
969 * @dir: DMA transfer direction (same as was passed to dma_map_sg)
971 void arm_dma_sync_sg_for_cpu(struct device *dev, struct scatterlist *sg,
972 int nents, enum dma_data_direction dir)
974 struct dma_map_ops *ops = get_dma_ops(dev);
975 struct scatterlist *s;
978 for_each_sg(sg, s, nents, i)
979 ops->sync_single_for_cpu(dev, sg_dma_address(s), s->length,
984 * arm_dma_sync_sg_for_device
985 * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices
986 * @sg: list of buffers
987 * @nents: number of buffers to map (returned from dma_map_sg)
988 * @dir: DMA transfer direction (same as was passed to dma_map_sg)
990 void arm_dma_sync_sg_for_device(struct device *dev, struct scatterlist *sg,
991 int nents, enum dma_data_direction dir)
993 struct dma_map_ops *ops = get_dma_ops(dev);
994 struct scatterlist *s;
997 for_each_sg(sg, s, nents, i)
998 ops->sync_single_for_device(dev, sg_dma_address(s), s->length,
1003 * Return whether the given device DMA address mask can be supported
1004 * properly. For example, if your device can only drive the low 24-bits
1005 * during bus mastering, then you would pass 0x00ffffff as the mask
1008 int dma_supported(struct device *dev, u64 mask)
1010 if (mask < (u64)arm_dma_limit)
1014 EXPORT_SYMBOL(dma_supported);
1016 int arm_dma_set_mask(struct device *dev, u64 dma_mask)
1018 if (!dev->dma_mask || !dma_supported(dev, dma_mask))
1021 *dev->dma_mask = dma_mask;
1026 #define PREALLOC_DMA_DEBUG_ENTRIES 4096
1028 static int __init dma_debug_do_init(void)
1030 dma_debug_init(PREALLOC_DMA_DEBUG_ENTRIES);
1033 fs_initcall(dma_debug_do_init);
1035 #ifdef CONFIG_ARM_DMA_USE_IOMMU
1039 static inline dma_addr_t __alloc_iova(struct dma_iommu_mapping *mapping,
1042 unsigned int order = get_order(size);
1043 unsigned int align = 0;
1044 unsigned int count, start;
1045 unsigned long flags;
1047 if (order > CONFIG_ARM_DMA_IOMMU_ALIGNMENT)
1048 order = CONFIG_ARM_DMA_IOMMU_ALIGNMENT;
1050 count = ((PAGE_ALIGN(size) >> PAGE_SHIFT) +
1051 (1 << mapping->order) - 1) >> mapping->order;
1053 if (order > mapping->order)
1054 align = (1 << (order - mapping->order)) - 1;
1056 spin_lock_irqsave(&mapping->lock, flags);
1057 start = bitmap_find_next_zero_area(mapping->bitmap, mapping->bits, 0,
1059 if (start > mapping->bits) {
1060 spin_unlock_irqrestore(&mapping->lock, flags);
1061 return DMA_ERROR_CODE;
1064 bitmap_set(mapping->bitmap, start, count);
1065 spin_unlock_irqrestore(&mapping->lock, flags);
1067 return mapping->base + (start << (mapping->order + PAGE_SHIFT));
1070 static inline void __free_iova(struct dma_iommu_mapping *mapping,
1071 dma_addr_t addr, size_t size)
1073 unsigned int start = (addr - mapping->base) >>
1074 (mapping->order + PAGE_SHIFT);
1075 unsigned int count = ((size >> PAGE_SHIFT) +
1076 (1 << mapping->order) - 1) >> mapping->order;
1077 unsigned long flags;
1079 spin_lock_irqsave(&mapping->lock, flags);
1080 bitmap_clear(mapping->bitmap, start, count);
1081 spin_unlock_irqrestore(&mapping->lock, flags);
1084 static struct page **__iommu_alloc_buffer(struct device *dev, size_t size,
1085 gfp_t gfp, struct dma_attrs *attrs)
1087 struct page **pages;
1088 int count = size >> PAGE_SHIFT;
1089 int array_size = count * sizeof(struct page *);
1092 if (array_size <= PAGE_SIZE)
1093 pages = kzalloc(array_size, gfp);
1095 pages = vzalloc(array_size);
1099 if (dma_get_attr(DMA_ATTR_FORCE_CONTIGUOUS, attrs))
1101 unsigned long order = get_order(size);
1104 page = dma_alloc_from_contiguous(dev, count, order);
1108 __dma_clear_buffer(page, size);
1110 for (i = 0; i < count; i++)
1111 pages[i] = page + i;
1117 * IOMMU can map any pages, so himem can also be used here
1119 gfp |= __GFP_NOWARN | __GFP_HIGHMEM;
1122 int j, order = __fls(count);
1124 pages[i] = alloc_pages(gfp, order);
1125 while (!pages[i] && order)
1126 pages[i] = alloc_pages(gfp, --order);
1131 split_page(pages[i], order);
1134 pages[i + j] = pages[i] + j;
1137 __dma_clear_buffer(pages[i], PAGE_SIZE << order);
1139 count -= 1 << order;
1146 __free_pages(pages[i], 0);
1147 if (array_size <= PAGE_SIZE)
1154 static int __iommu_free_buffer(struct device *dev, struct page **pages,
1155 size_t size, struct dma_attrs *attrs)
1157 int count = size >> PAGE_SHIFT;
1158 int array_size = count * sizeof(struct page *);
1161 if (dma_get_attr(DMA_ATTR_FORCE_CONTIGUOUS, attrs)) {
1162 dma_release_from_contiguous(dev, pages[0], count);
1164 for (i = 0; i < count; i++)
1166 __free_pages(pages[i], 0);
1169 if (array_size <= PAGE_SIZE)
1177 * Create a CPU mapping for a specified pages
1180 __iommu_alloc_remap(struct page **pages, size_t size, gfp_t gfp, pgprot_t prot,
1183 unsigned int i, nr_pages = PAGE_ALIGN(size) >> PAGE_SHIFT;
1184 struct vm_struct *area;
1187 area = get_vm_area_caller(size, VM_ARM_DMA_CONSISTENT | VM_USERMAP,
1192 area->pages = pages;
1193 area->nr_pages = nr_pages;
1194 p = (unsigned long)area->addr;
1196 for (i = 0; i < nr_pages; i++) {
1197 phys_addr_t phys = __pfn_to_phys(page_to_pfn(pages[i]));
1198 if (ioremap_page_range(p, p + PAGE_SIZE, phys, prot))
1204 unmap_kernel_range((unsigned long)area->addr, size);
1210 * Create a mapping in device IO address space for specified pages
1213 __iommu_create_mapping(struct device *dev, struct page **pages, size_t size)
1215 struct dma_iommu_mapping *mapping = dev->archdata.mapping;
1216 unsigned int count = PAGE_ALIGN(size) >> PAGE_SHIFT;
1217 dma_addr_t dma_addr, iova;
1218 int i, ret = DMA_ERROR_CODE;
1220 dma_addr = __alloc_iova(mapping, size);
1221 if (dma_addr == DMA_ERROR_CODE)
1225 for (i = 0; i < count; ) {
1226 unsigned int next_pfn = page_to_pfn(pages[i]) + 1;
1227 phys_addr_t phys = page_to_phys(pages[i]);
1228 unsigned int len, j;
1230 for (j = i + 1; j < count; j++, next_pfn++)
1231 if (page_to_pfn(pages[j]) != next_pfn)
1234 len = (j - i) << PAGE_SHIFT;
1235 ret = iommu_map(mapping->domain, iova, phys, len,
1236 IOMMU_READ|IOMMU_WRITE);
1244 iommu_unmap(mapping->domain, dma_addr, iova-dma_addr);
1245 __free_iova(mapping, dma_addr, size);
1246 return DMA_ERROR_CODE;
1249 static int __iommu_remove_mapping(struct device *dev, dma_addr_t iova, size_t size)
1251 struct dma_iommu_mapping *mapping = dev->archdata.mapping;
1254 * add optional in-page offset from iova to size and align
1255 * result to page size
1257 size = PAGE_ALIGN((iova & ~PAGE_MASK) + size);
1260 iommu_unmap(mapping->domain, iova, size);
1261 __free_iova(mapping, iova, size);
1265 static struct page **__atomic_get_pages(void *addr)
1267 struct dma_pool *pool = &atomic_pool;
1268 struct page **pages = pool->pages;
1269 int offs = (addr - pool->vaddr) >> PAGE_SHIFT;
1271 return pages + offs;
1274 static struct page **__iommu_get_pages(void *cpu_addr, struct dma_attrs *attrs)
1276 struct vm_struct *area;
1278 if (__in_atomic_pool(cpu_addr, PAGE_SIZE))
1279 return __atomic_get_pages(cpu_addr);
1281 if (dma_get_attr(DMA_ATTR_NO_KERNEL_MAPPING, attrs))
1284 area = find_vm_area(cpu_addr);
1285 if (area && (area->flags & VM_ARM_DMA_CONSISTENT))
1290 static void *__iommu_alloc_atomic(struct device *dev, size_t size,
1296 addr = __alloc_from_pool(size, &page);
1300 *handle = __iommu_create_mapping(dev, &page, size);
1301 if (*handle == DMA_ERROR_CODE)
1307 __free_from_pool(addr, size);
1311 static void __iommu_free_atomic(struct device *dev, void *cpu_addr,
1312 dma_addr_t handle, size_t size)
1314 __iommu_remove_mapping(dev, handle, size);
1315 __free_from_pool(cpu_addr, size);
1318 static void *arm_iommu_alloc_attrs(struct device *dev, size_t size,
1319 dma_addr_t *handle, gfp_t gfp, struct dma_attrs *attrs)
1321 pgprot_t prot = __get_dma_pgprot(attrs, pgprot_kernel);
1322 struct page **pages;
1325 *handle = DMA_ERROR_CODE;
1326 size = PAGE_ALIGN(size);
1328 if (gfp & GFP_ATOMIC)
1329 return __iommu_alloc_atomic(dev, size, handle);
1332 * Following is a work-around (a.k.a. hack) to prevent pages
1333 * with __GFP_COMP being passed to split_page() which cannot
1334 * handle them. The real problem is that this flag probably
1335 * should be 0 on ARM as it is not supported on this
1336 * platform; see CONFIG_HUGETLBFS.
1338 gfp &= ~(__GFP_COMP);
1340 pages = __iommu_alloc_buffer(dev, size, gfp, attrs);
1344 *handle = __iommu_create_mapping(dev, pages, size);
1345 if (*handle == DMA_ERROR_CODE)
1348 if (dma_get_attr(DMA_ATTR_NO_KERNEL_MAPPING, attrs))
1351 addr = __iommu_alloc_remap(pages, size, gfp, prot,
1352 __builtin_return_address(0));
1359 __iommu_remove_mapping(dev, *handle, size);
1361 __iommu_free_buffer(dev, pages, size, attrs);
1365 static int arm_iommu_mmap_attrs(struct device *dev, struct vm_area_struct *vma,
1366 void *cpu_addr, dma_addr_t dma_addr, size_t size,
1367 struct dma_attrs *attrs)
1369 unsigned long uaddr = vma->vm_start;
1370 unsigned long usize = vma->vm_end - vma->vm_start;
1371 struct page **pages = __iommu_get_pages(cpu_addr, attrs);
1373 vma->vm_page_prot = __get_dma_pgprot(attrs, vma->vm_page_prot);
1379 int ret = vm_insert_page(vma, uaddr, *pages++);
1381 pr_err("Remapping memory failed: %d\n", ret);
1386 } while (usize > 0);
1392 * free a page as defined by the above mapping.
1393 * Must not be called with IRQs disabled.
1395 void arm_iommu_free_attrs(struct device *dev, size_t size, void *cpu_addr,
1396 dma_addr_t handle, struct dma_attrs *attrs)
1398 struct page **pages;
1399 size = PAGE_ALIGN(size);
1401 if (__in_atomic_pool(cpu_addr, size)) {
1402 __iommu_free_atomic(dev, cpu_addr, handle, size);
1406 pages = __iommu_get_pages(cpu_addr, attrs);
1408 WARN(1, "trying to free invalid coherent area: %p\n", cpu_addr);
1412 if (!dma_get_attr(DMA_ATTR_NO_KERNEL_MAPPING, attrs)) {
1413 unmap_kernel_range((unsigned long)cpu_addr, size);
1417 __iommu_remove_mapping(dev, handle, size);
1418 __iommu_free_buffer(dev, pages, size, attrs);
1421 static int arm_iommu_get_sgtable(struct device *dev, struct sg_table *sgt,
1422 void *cpu_addr, dma_addr_t dma_addr,
1423 size_t size, struct dma_attrs *attrs)
1425 unsigned int count = PAGE_ALIGN(size) >> PAGE_SHIFT;
1426 struct page **pages = __iommu_get_pages(cpu_addr, attrs);
1431 return sg_alloc_table_from_pages(sgt, pages, count, 0, size,
1435 static int __dma_direction_to_prot(enum dma_data_direction dir)
1440 case DMA_BIDIRECTIONAL:
1441 prot = IOMMU_READ | IOMMU_WRITE;
1446 case DMA_FROM_DEVICE:
1457 * Map a part of the scatter-gather list into contiguous io address space
1459 static int __map_sg_chunk(struct device *dev, struct scatterlist *sg,
1460 size_t size, dma_addr_t *handle,
1461 enum dma_data_direction dir, struct dma_attrs *attrs,
1464 struct dma_iommu_mapping *mapping = dev->archdata.mapping;
1465 dma_addr_t iova, iova_base;
1468 struct scatterlist *s;
1471 size = PAGE_ALIGN(size);
1472 *handle = DMA_ERROR_CODE;
1474 iova_base = iova = __alloc_iova(mapping, size);
1475 if (iova == DMA_ERROR_CODE)
1478 for (count = 0, s = sg; count < (size >> PAGE_SHIFT); s = sg_next(s)) {
1479 phys_addr_t phys = page_to_phys(sg_page(s));
1480 unsigned int len = PAGE_ALIGN(s->offset + s->length);
1483 !dma_get_attr(DMA_ATTR_SKIP_CPU_SYNC, attrs))
1484 __dma_page_cpu_to_dev(sg_page(s), s->offset, s->length, dir);
1486 prot = __dma_direction_to_prot(dir);
1488 ret = iommu_map(mapping->domain, iova, phys, len, prot);
1491 count += len >> PAGE_SHIFT;
1494 *handle = iova_base;
1498 iommu_unmap(mapping->domain, iova_base, count * PAGE_SIZE);
1499 __free_iova(mapping, iova_base, size);
1503 static int __iommu_map_sg(struct device *dev, struct scatterlist *sg, int nents,
1504 enum dma_data_direction dir, struct dma_attrs *attrs,
1507 struct scatterlist *s = sg, *dma = sg, *start = sg;
1509 unsigned int offset = s->offset;
1510 unsigned int size = s->offset + s->length;
1511 unsigned int max = dma_get_max_seg_size(dev);
1513 for (i = 1; i < nents; i++) {
1516 s->dma_address = DMA_ERROR_CODE;
1519 if (s->offset || (size & ~PAGE_MASK) || size + s->length > max) {
1520 if (__map_sg_chunk(dev, start, size, &dma->dma_address,
1521 dir, attrs, is_coherent) < 0)
1524 dma->dma_address += offset;
1525 dma->dma_length = size - offset;
1527 size = offset = s->offset;
1534 if (__map_sg_chunk(dev, start, size, &dma->dma_address, dir, attrs,
1538 dma->dma_address += offset;
1539 dma->dma_length = size - offset;
1544 for_each_sg(sg, s, count, i)
1545 __iommu_remove_mapping(dev, sg_dma_address(s), sg_dma_len(s));
1550 * arm_coherent_iommu_map_sg - map a set of SG buffers for streaming mode DMA
1551 * @dev: valid struct device pointer
1552 * @sg: list of buffers
1553 * @nents: number of buffers to map
1554 * @dir: DMA transfer direction
1556 * Map a set of i/o coherent buffers described by scatterlist in streaming
1557 * mode for DMA. The scatter gather list elements are merged together (if
1558 * possible) and tagged with the appropriate dma address and length. They are
1559 * obtained via sg_dma_{address,length}.
1561 int arm_coherent_iommu_map_sg(struct device *dev, struct scatterlist *sg,
1562 int nents, enum dma_data_direction dir, struct dma_attrs *attrs)
1564 return __iommu_map_sg(dev, sg, nents, dir, attrs, true);
1568 * arm_iommu_map_sg - map a set of SG buffers for streaming mode DMA
1569 * @dev: valid struct device pointer
1570 * @sg: list of buffers
1571 * @nents: number of buffers to map
1572 * @dir: DMA transfer direction
1574 * Map a set of buffers described by scatterlist in streaming mode for DMA.
1575 * The scatter gather list elements are merged together (if possible) and
1576 * tagged with the appropriate dma address and length. They are obtained via
1577 * sg_dma_{address,length}.
1579 int arm_iommu_map_sg(struct device *dev, struct scatterlist *sg,
1580 int nents, enum dma_data_direction dir, struct dma_attrs *attrs)
1582 return __iommu_map_sg(dev, sg, nents, dir, attrs, false);
1585 static void __iommu_unmap_sg(struct device *dev, struct scatterlist *sg,
1586 int nents, enum dma_data_direction dir, struct dma_attrs *attrs,
1589 struct scatterlist *s;
1592 for_each_sg(sg, s, nents, i) {
1594 __iommu_remove_mapping(dev, sg_dma_address(s),
1597 !dma_get_attr(DMA_ATTR_SKIP_CPU_SYNC, attrs))
1598 __dma_page_dev_to_cpu(sg_page(s), s->offset,
1604 * arm_coherent_iommu_unmap_sg - unmap a set of SG buffers mapped by dma_map_sg
1605 * @dev: valid struct device pointer
1606 * @sg: list of buffers
1607 * @nents: number of buffers to unmap (same as was passed to dma_map_sg)
1608 * @dir: DMA transfer direction (same as was passed to dma_map_sg)
1610 * Unmap a set of streaming mode DMA translations. Again, CPU access
1611 * rules concerning calls here are the same as for dma_unmap_single().
1613 void arm_coherent_iommu_unmap_sg(struct device *dev, struct scatterlist *sg,
1614 int nents, enum dma_data_direction dir, struct dma_attrs *attrs)
1616 __iommu_unmap_sg(dev, sg, nents, dir, attrs, true);
1620 * arm_iommu_unmap_sg - unmap a set of SG buffers mapped by dma_map_sg
1621 * @dev: valid struct device pointer
1622 * @sg: list of buffers
1623 * @nents: number of buffers to unmap (same as was passed to dma_map_sg)
1624 * @dir: DMA transfer direction (same as was passed to dma_map_sg)
1626 * Unmap a set of streaming mode DMA translations. Again, CPU access
1627 * rules concerning calls here are the same as for dma_unmap_single().
1629 void arm_iommu_unmap_sg(struct device *dev, struct scatterlist *sg, int nents,
1630 enum dma_data_direction dir, struct dma_attrs *attrs)
1632 __iommu_unmap_sg(dev, sg, nents, dir, attrs, false);
1636 * arm_iommu_sync_sg_for_cpu
1637 * @dev: valid struct device pointer
1638 * @sg: list of buffers
1639 * @nents: number of buffers to map (returned from dma_map_sg)
1640 * @dir: DMA transfer direction (same as was passed to dma_map_sg)
1642 void arm_iommu_sync_sg_for_cpu(struct device *dev, struct scatterlist *sg,
1643 int nents, enum dma_data_direction dir)
1645 struct scatterlist *s;
1648 for_each_sg(sg, s, nents, i)
1649 __dma_page_dev_to_cpu(sg_page(s), s->offset, s->length, dir);
1654 * arm_iommu_sync_sg_for_device
1655 * @dev: valid struct device pointer
1656 * @sg: list of buffers
1657 * @nents: number of buffers to map (returned from dma_map_sg)
1658 * @dir: DMA transfer direction (same as was passed to dma_map_sg)
1660 void arm_iommu_sync_sg_for_device(struct device *dev, struct scatterlist *sg,
1661 int nents, enum dma_data_direction dir)
1663 struct scatterlist *s;
1666 for_each_sg(sg, s, nents, i)
1667 __dma_page_cpu_to_dev(sg_page(s), s->offset, s->length, dir);
1672 * arm_coherent_iommu_map_page
1673 * @dev: valid struct device pointer
1674 * @page: page that buffer resides in
1675 * @offset: offset into page for start of buffer
1676 * @size: size of buffer to map
1677 * @dir: DMA transfer direction
1679 * Coherent IOMMU aware version of arm_dma_map_page()
1681 static dma_addr_t arm_coherent_iommu_map_page(struct device *dev, struct page *page,
1682 unsigned long offset, size_t size, enum dma_data_direction dir,
1683 struct dma_attrs *attrs)
1685 struct dma_iommu_mapping *mapping = dev->archdata.mapping;
1686 dma_addr_t dma_addr;
1687 int ret, prot, len = PAGE_ALIGN(size + offset);
1689 dma_addr = __alloc_iova(mapping, len);
1690 if (dma_addr == DMA_ERROR_CODE)
1693 prot = __dma_direction_to_prot(dir);
1695 ret = iommu_map(mapping->domain, dma_addr, page_to_phys(page), len, prot);
1699 return dma_addr + offset;
1701 __free_iova(mapping, dma_addr, len);
1702 return DMA_ERROR_CODE;
1706 * arm_iommu_map_page
1707 * @dev: valid struct device pointer
1708 * @page: page that buffer resides in
1709 * @offset: offset into page for start of buffer
1710 * @size: size of buffer to map
1711 * @dir: DMA transfer direction
1713 * IOMMU aware version of arm_dma_map_page()
1715 static dma_addr_t arm_iommu_map_page(struct device *dev, struct page *page,
1716 unsigned long offset, size_t size, enum dma_data_direction dir,
1717 struct dma_attrs *attrs)
1719 if (!dma_get_attr(DMA_ATTR_SKIP_CPU_SYNC, attrs))
1720 __dma_page_cpu_to_dev(page, offset, size, dir);
1722 return arm_coherent_iommu_map_page(dev, page, offset, size, dir, attrs);
1726 * arm_coherent_iommu_unmap_page
1727 * @dev: valid struct device pointer
1728 * @handle: DMA address of buffer
1729 * @size: size of buffer (same as passed to dma_map_page)
1730 * @dir: DMA transfer direction (same as passed to dma_map_page)
1732 * Coherent IOMMU aware version of arm_dma_unmap_page()
1734 static void arm_coherent_iommu_unmap_page(struct device *dev, dma_addr_t handle,
1735 size_t size, enum dma_data_direction dir,
1736 struct dma_attrs *attrs)
1738 struct dma_iommu_mapping *mapping = dev->archdata.mapping;
1739 dma_addr_t iova = handle & PAGE_MASK;
1740 int offset = handle & ~PAGE_MASK;
1741 int len = PAGE_ALIGN(size + offset);
1746 iommu_unmap(mapping->domain, iova, len);
1747 __free_iova(mapping, iova, len);
1751 * arm_iommu_unmap_page
1752 * @dev: valid struct device pointer
1753 * @handle: DMA address of buffer
1754 * @size: size of buffer (same as passed to dma_map_page)
1755 * @dir: DMA transfer direction (same as passed to dma_map_page)
1757 * IOMMU aware version of arm_dma_unmap_page()
1759 static void arm_iommu_unmap_page(struct device *dev, dma_addr_t handle,
1760 size_t size, enum dma_data_direction dir,
1761 struct dma_attrs *attrs)
1763 struct dma_iommu_mapping *mapping = dev->archdata.mapping;
1764 dma_addr_t iova = handle & PAGE_MASK;
1765 struct page *page = phys_to_page(iommu_iova_to_phys(mapping->domain, iova));
1766 int offset = handle & ~PAGE_MASK;
1767 int len = PAGE_ALIGN(size + offset);
1772 if (!dma_get_attr(DMA_ATTR_SKIP_CPU_SYNC, attrs))
1773 __dma_page_dev_to_cpu(page, offset, size, dir);
1775 iommu_unmap(mapping->domain, iova, len);
1776 __free_iova(mapping, iova, len);
1779 static void arm_iommu_sync_single_for_cpu(struct device *dev,
1780 dma_addr_t handle, size_t size, enum dma_data_direction dir)
1782 struct dma_iommu_mapping *mapping = dev->archdata.mapping;
1783 dma_addr_t iova = handle & PAGE_MASK;
1784 struct page *page = phys_to_page(iommu_iova_to_phys(mapping->domain, iova));
1785 unsigned int offset = handle & ~PAGE_MASK;
1790 __dma_page_dev_to_cpu(page, offset, size, dir);
1793 static void arm_iommu_sync_single_for_device(struct device *dev,
1794 dma_addr_t handle, size_t size, enum dma_data_direction dir)
1796 struct dma_iommu_mapping *mapping = dev->archdata.mapping;
1797 dma_addr_t iova = handle & PAGE_MASK;
1798 struct page *page = phys_to_page(iommu_iova_to_phys(mapping->domain, iova));
1799 unsigned int offset = handle & ~PAGE_MASK;
1804 __dma_page_cpu_to_dev(page, offset, size, dir);
1807 struct dma_map_ops iommu_ops = {
1808 .alloc = arm_iommu_alloc_attrs,
1809 .free = arm_iommu_free_attrs,
1810 .mmap = arm_iommu_mmap_attrs,
1811 .get_sgtable = arm_iommu_get_sgtable,
1813 .map_page = arm_iommu_map_page,
1814 .unmap_page = arm_iommu_unmap_page,
1815 .sync_single_for_cpu = arm_iommu_sync_single_for_cpu,
1816 .sync_single_for_device = arm_iommu_sync_single_for_device,
1818 .map_sg = arm_iommu_map_sg,
1819 .unmap_sg = arm_iommu_unmap_sg,
1820 .sync_sg_for_cpu = arm_iommu_sync_sg_for_cpu,
1821 .sync_sg_for_device = arm_iommu_sync_sg_for_device,
1823 .set_dma_mask = arm_dma_set_mask,
1826 struct dma_map_ops iommu_coherent_ops = {
1827 .alloc = arm_iommu_alloc_attrs,
1828 .free = arm_iommu_free_attrs,
1829 .mmap = arm_iommu_mmap_attrs,
1830 .get_sgtable = arm_iommu_get_sgtable,
1832 .map_page = arm_coherent_iommu_map_page,
1833 .unmap_page = arm_coherent_iommu_unmap_page,
1835 .map_sg = arm_coherent_iommu_map_sg,
1836 .unmap_sg = arm_coherent_iommu_unmap_sg,
1838 .set_dma_mask = arm_dma_set_mask,
1842 * arm_iommu_create_mapping
1843 * @bus: pointer to the bus holding the client device (for IOMMU calls)
1844 * @base: start address of the valid IO address space
1845 * @size: size of the valid IO address space
1846 * @order: accuracy of the IO addresses allocations
1848 * Creates a mapping structure which holds information about used/unused
1849 * IO address ranges, which is required to perform memory allocation and
1850 * mapping with IOMMU aware functions.
1852 * The client device need to be attached to the mapping with
1853 * arm_iommu_attach_device function.
1855 struct dma_iommu_mapping *
1856 arm_iommu_create_mapping(struct bus_type *bus, dma_addr_t base, size_t size,
1859 unsigned int count = size >> (PAGE_SHIFT + order);
1860 unsigned int bitmap_size = BITS_TO_LONGS(count) * sizeof(long);
1861 struct dma_iommu_mapping *mapping;
1865 return ERR_PTR(-EINVAL);
1867 mapping = kzalloc(sizeof(struct dma_iommu_mapping), GFP_KERNEL);
1871 mapping->bitmap = kzalloc(bitmap_size, GFP_KERNEL);
1872 if (!mapping->bitmap)
1875 mapping->base = base;
1876 mapping->bits = BITS_PER_BYTE * bitmap_size;
1877 mapping->order = order;
1878 spin_lock_init(&mapping->lock);
1880 mapping->domain = iommu_domain_alloc(bus);
1881 if (!mapping->domain)
1884 kref_init(&mapping->kref);
1887 kfree(mapping->bitmap);
1891 return ERR_PTR(err);
1893 EXPORT_SYMBOL_GPL(arm_iommu_create_mapping);
1895 static void release_iommu_mapping(struct kref *kref)
1897 struct dma_iommu_mapping *mapping =
1898 container_of(kref, struct dma_iommu_mapping, kref);
1900 iommu_domain_free(mapping->domain);
1901 kfree(mapping->bitmap);
1905 void arm_iommu_release_mapping(struct dma_iommu_mapping *mapping)
1908 kref_put(&mapping->kref, release_iommu_mapping);
1910 EXPORT_SYMBOL_GPL(arm_iommu_release_mapping);
1913 * arm_iommu_attach_device
1914 * @dev: valid struct device pointer
1915 * @mapping: io address space mapping structure (returned from
1916 * arm_iommu_create_mapping)
1918 * Attaches specified io address space mapping to the provided device,
1919 * this replaces the dma operations (dma_map_ops pointer) with the
1920 * IOMMU aware version. More than one client might be attached to
1921 * the same io address space mapping.
1923 int arm_iommu_attach_device(struct device *dev,
1924 struct dma_iommu_mapping *mapping)
1928 err = iommu_attach_device(mapping->domain, dev);
1932 kref_get(&mapping->kref);
1933 dev->archdata.mapping = mapping;
1934 set_dma_ops(dev, &iommu_ops);
1936 pr_debug("Attached IOMMU controller to %s device.\n", dev_name(dev));
1939 EXPORT_SYMBOL_GPL(arm_iommu_attach_device);
1942 * arm_iommu_detach_device
1943 * @dev: valid struct device pointer
1945 * Detaches the provided device from a previously attached map.
1946 * This voids the dma operations (dma_map_ops pointer)
1948 void arm_iommu_detach_device(struct device *dev)
1950 struct dma_iommu_mapping *mapping;
1952 mapping = to_dma_iommu_mapping(dev);
1954 dev_warn(dev, "Not attached\n");
1958 iommu_detach_device(mapping->domain, dev);
1959 kref_put(&mapping->kref, release_iommu_mapping);
1960 dev->archdata.mapping = NULL;
1961 set_dma_ops(dev, NULL);
1963 pr_debug("Detached IOMMU controller from %s device.\n", dev_name(dev));
1965 EXPORT_SYMBOL_GPL(arm_iommu_detach_device);