2 * linux/arch/arm/mm/dma-mapping.c
4 * Copyright (C) 2000-2004 Russell King
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 * DMA uncached mapping support.
12 #include <linux/module.h>
14 #include <linux/gfp.h>
15 #include <linux/errno.h>
16 #include <linux/list.h>
17 #include <linux/init.h>
18 #include <linux/device.h>
19 #include <linux/dma-mapping.h>
20 #include <linux/dma-contiguous.h>
21 #include <linux/highmem.h>
22 #include <linux/memblock.h>
23 #include <linux/slab.h>
24 #include <linux/iommu.h>
26 #include <linux/vmalloc.h>
27 #include <linux/sizes.h>
29 #include <asm/memory.h>
30 #include <asm/highmem.h>
31 #include <asm/cacheflush.h>
32 #include <asm/tlbflush.h>
33 #include <asm/mach/arch.h>
34 #include <asm/dma-iommu.h>
35 #include <asm/mach/map.h>
36 #include <asm/system_info.h>
37 #include <asm/dma-contiguous.h>
42 * The DMA API is built upon the notion of "buffer ownership". A buffer
43 * is either exclusively owned by the CPU (and therefore may be accessed
44 * by it) or exclusively owned by the DMA device. These helper functions
45 * represent the transitions between these two ownership states.
47 * Note, however, that on later ARMs, this notion does not work due to
48 * speculative prefetches. We model our approach on the assumption that
49 * the CPU does do speculative prefetches, which means we clean caches
50 * before transfers and delay cache invalidation until transfer completion.
53 static void __dma_page_cpu_to_dev(struct page *, unsigned long,
54 size_t, enum dma_data_direction);
55 static void __dma_page_dev_to_cpu(struct page *, unsigned long,
56 size_t, enum dma_data_direction);
59 * arm_dma_map_page - map a portion of a page for streaming DMA
60 * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices
61 * @page: page that buffer resides in
62 * @offset: offset into page for start of buffer
63 * @size: size of buffer to map
64 * @dir: DMA transfer direction
66 * Ensure that any data held in the cache is appropriately discarded
69 * The device owns this memory once this call has completed. The CPU
70 * can regain ownership by calling dma_unmap_page().
72 static dma_addr_t arm_dma_map_page(struct device *dev, struct page *page,
73 unsigned long offset, size_t size, enum dma_data_direction dir,
74 struct dma_attrs *attrs)
76 if (!dma_get_attr(DMA_ATTR_SKIP_CPU_SYNC, attrs))
77 __dma_page_cpu_to_dev(page, offset, size, dir);
78 return pfn_to_dma(dev, page_to_pfn(page)) + offset;
81 static dma_addr_t arm_coherent_dma_map_page(struct device *dev, struct page *page,
82 unsigned long offset, size_t size, enum dma_data_direction dir,
83 struct dma_attrs *attrs)
85 return pfn_to_dma(dev, page_to_pfn(page)) + offset;
89 * arm_dma_unmap_page - unmap a buffer previously mapped through dma_map_page()
90 * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices
91 * @handle: DMA address of buffer
92 * @size: size of buffer (same as passed to dma_map_page)
93 * @dir: DMA transfer direction (same as passed to dma_map_page)
95 * Unmap a page streaming mode DMA translation. The handle and size
96 * must match what was provided in the previous dma_map_page() call.
97 * All other usages are undefined.
99 * After this call, reads by the CPU to the buffer are guaranteed to see
100 * whatever the device wrote there.
102 static void arm_dma_unmap_page(struct device *dev, dma_addr_t handle,
103 size_t size, enum dma_data_direction dir,
104 struct dma_attrs *attrs)
106 if (!dma_get_attr(DMA_ATTR_SKIP_CPU_SYNC, attrs))
107 __dma_page_dev_to_cpu(pfn_to_page(dma_to_pfn(dev, handle)),
108 handle & ~PAGE_MASK, size, dir);
111 static void arm_dma_sync_single_for_cpu(struct device *dev,
112 dma_addr_t handle, size_t size, enum dma_data_direction dir)
114 unsigned int offset = handle & (PAGE_SIZE - 1);
115 struct page *page = pfn_to_page(dma_to_pfn(dev, handle-offset));
116 __dma_page_dev_to_cpu(page, offset, size, dir);
119 static void arm_dma_sync_single_for_device(struct device *dev,
120 dma_addr_t handle, size_t size, enum dma_data_direction dir)
122 unsigned int offset = handle & (PAGE_SIZE - 1);
123 struct page *page = pfn_to_page(dma_to_pfn(dev, handle-offset));
124 __dma_page_cpu_to_dev(page, offset, size, dir);
127 struct dma_map_ops arm_dma_ops = {
128 .alloc = arm_dma_alloc,
129 .free = arm_dma_free,
130 .mmap = arm_dma_mmap,
131 .get_sgtable = arm_dma_get_sgtable,
132 .map_page = arm_dma_map_page,
133 .unmap_page = arm_dma_unmap_page,
134 .map_sg = arm_dma_map_sg,
135 .unmap_sg = arm_dma_unmap_sg,
136 .sync_single_for_cpu = arm_dma_sync_single_for_cpu,
137 .sync_single_for_device = arm_dma_sync_single_for_device,
138 .sync_sg_for_cpu = arm_dma_sync_sg_for_cpu,
139 .sync_sg_for_device = arm_dma_sync_sg_for_device,
140 .set_dma_mask = arm_dma_set_mask,
142 EXPORT_SYMBOL(arm_dma_ops);
144 static void *arm_coherent_dma_alloc(struct device *dev, size_t size,
145 dma_addr_t *handle, gfp_t gfp, struct dma_attrs *attrs);
146 static void arm_coherent_dma_free(struct device *dev, size_t size, void *cpu_addr,
147 dma_addr_t handle, struct dma_attrs *attrs);
149 struct dma_map_ops arm_coherent_dma_ops = {
150 .alloc = arm_coherent_dma_alloc,
151 .free = arm_coherent_dma_free,
152 .mmap = arm_dma_mmap,
153 .get_sgtable = arm_dma_get_sgtable,
154 .map_page = arm_coherent_dma_map_page,
155 .map_sg = arm_dma_map_sg,
156 .set_dma_mask = arm_dma_set_mask,
158 EXPORT_SYMBOL(arm_coherent_dma_ops);
160 static u64 get_coherent_dma_mask(struct device *dev)
162 u64 mask = (u64)arm_dma_limit;
165 mask = dev->coherent_dma_mask;
168 * Sanity check the DMA mask - it must be non-zero, and
169 * must be able to be satisfied by a DMA allocation.
172 dev_warn(dev, "coherent DMA mask is unset\n");
176 if ((~mask) & (u64)arm_dma_limit) {
177 dev_warn(dev, "coherent DMA mask %#llx is smaller "
178 "than system GFP_DMA mask %#llx\n",
179 mask, (u64)arm_dma_limit);
187 static void __dma_clear_buffer(struct page *page, size_t size)
190 * Ensure that the allocated pages are zeroed, and that any data
191 * lurking in the kernel direct-mapped region is invalidated.
193 if (PageHighMem(page)) {
194 phys_addr_t base = __pfn_to_phys(page_to_pfn(page));
195 phys_addr_t end = base + size;
197 void *ptr = kmap_atomic(page);
198 memset(ptr, 0, PAGE_SIZE);
199 dmac_flush_range(ptr, ptr + PAGE_SIZE);
204 outer_flush_range(base, end);
206 void *ptr = page_address(page);
207 memset(ptr, 0, size);
208 dmac_flush_range(ptr, ptr + size);
209 outer_flush_range(__pa(ptr), __pa(ptr) + size);
214 * Allocate a DMA buffer for 'dev' of size 'size' using the
215 * specified gfp mask. Note that 'size' must be page aligned.
217 static struct page *__dma_alloc_buffer(struct device *dev, size_t size, gfp_t gfp)
219 unsigned long order = get_order(size);
220 struct page *page, *p, *e;
222 page = alloc_pages(gfp, order);
227 * Now split the huge page and free the excess pages
229 split_page(page, order);
230 for (p = page + (size >> PAGE_SHIFT), e = page + (1 << order); p < e; p++)
233 __dma_clear_buffer(page, size);
239 * Free a DMA buffer. 'size' must be page aligned.
241 static void __dma_free_buffer(struct page *page, size_t size)
243 struct page *e = page + (size >> PAGE_SHIFT);
252 #ifdef CONFIG_HUGETLB_PAGE
253 #error ARM Coherent DMA allocator does not (yet) support huge TLB
256 static void *__alloc_from_contiguous(struct device *dev, size_t size,
257 pgprot_t prot, struct page **ret_page,
260 static void *__alloc_remap_buffer(struct device *dev, size_t size, gfp_t gfp,
261 pgprot_t prot, struct page **ret_page,
265 __dma_alloc_remap(struct page *page, size_t size, gfp_t gfp, pgprot_t prot,
268 struct vm_struct *area;
272 * DMA allocation can be mapped to user space, so lets
273 * set VM_USERMAP flags too.
275 area = get_vm_area_caller(size, VM_ARM_DMA_CONSISTENT | VM_USERMAP,
279 addr = (unsigned long)area->addr;
280 area->phys_addr = __pfn_to_phys(page_to_pfn(page));
282 if (ioremap_page_range(addr, addr + size, area->phys_addr, prot)) {
283 vunmap((void *)addr);
289 static void __dma_free_remap(void *cpu_addr, size_t size)
291 unsigned int flags = VM_ARM_DMA_CONSISTENT | VM_USERMAP;
292 struct vm_struct *area = find_vm_area(cpu_addr);
293 if (!area || (area->flags & flags) != flags) {
294 WARN(1, "trying to free invalid coherent area: %p\n", cpu_addr);
297 unmap_kernel_range((unsigned long)cpu_addr, size);
301 #define DEFAULT_DMA_COHERENT_POOL_SIZE SZ_256K
306 unsigned long *bitmap;
307 unsigned long nr_pages;
312 static struct dma_pool atomic_pool = {
313 .size = DEFAULT_DMA_COHERENT_POOL_SIZE,
316 static int __init early_coherent_pool(char *p)
318 atomic_pool.size = memparse(p, &p);
321 early_param("coherent_pool", early_coherent_pool);
323 void __init init_dma_coherent_pool_size(unsigned long size)
326 * Catch any attempt to set the pool size too late.
328 BUG_ON(atomic_pool.vaddr);
331 * Set architecture specific coherent pool size only if
332 * it has not been changed by kernel command line parameter.
334 if (atomic_pool.size == DEFAULT_DMA_COHERENT_POOL_SIZE)
335 atomic_pool.size = size;
339 * Initialise the coherent pool for atomic allocations.
341 static int __init atomic_pool_init(void)
343 struct dma_pool *pool = &atomic_pool;
344 pgprot_t prot = pgprot_dmacoherent(pgprot_kernel);
345 gfp_t gfp = GFP_KERNEL | GFP_DMA;
346 unsigned long nr_pages = pool->size >> PAGE_SHIFT;
347 unsigned long *bitmap;
351 int bitmap_size = BITS_TO_LONGS(nr_pages) * sizeof(long);
353 bitmap = kzalloc(bitmap_size, GFP_KERNEL);
357 pages = kzalloc(nr_pages * sizeof(struct page *), GFP_KERNEL);
361 if (IS_ENABLED(CONFIG_CMA))
362 ptr = __alloc_from_contiguous(NULL, pool->size, prot, &page,
365 ptr = __alloc_remap_buffer(NULL, pool->size, gfp, prot, &page,
370 for (i = 0; i < nr_pages; i++)
373 spin_lock_init(&pool->lock);
376 pool->bitmap = bitmap;
377 pool->nr_pages = nr_pages;
378 pr_info("DMA: preallocated %u KiB pool for atomic coherent allocations\n",
379 (unsigned)pool->size / 1024);
387 pr_err("DMA: failed to allocate %u KiB pool for atomic coherent allocation\n",
388 (unsigned)pool->size / 1024);
392 * CMA is activated by core_initcall, so we must be called after it.
394 postcore_initcall(atomic_pool_init);
396 struct dma_contig_early_reserve {
401 static struct dma_contig_early_reserve dma_mmu_remap[MAX_CMA_AREAS] __initdata;
403 static int dma_mmu_remap_num __initdata;
405 void __init dma_contiguous_early_fixup(phys_addr_t base, unsigned long size)
407 dma_mmu_remap[dma_mmu_remap_num].base = base;
408 dma_mmu_remap[dma_mmu_remap_num].size = size;
412 void __init dma_contiguous_remap(void)
415 for (i = 0; i < dma_mmu_remap_num; i++) {
416 phys_addr_t start = dma_mmu_remap[i].base;
417 phys_addr_t end = start + dma_mmu_remap[i].size;
421 if (end > arm_lowmem_limit)
422 end = arm_lowmem_limit;
426 map.pfn = __phys_to_pfn(start);
427 map.virtual = __phys_to_virt(start);
428 map.length = end - start;
429 map.type = MT_MEMORY_DMA_READY;
432 * Clear previous low-memory mapping to ensure that the
433 * TLB does not see any conflicting entries, then flush
434 * the TLB of the old entries before creating new mappings.
436 * This ensures that any speculatively loaded TLB entries
437 * (even though they may be rare) can not cause any problems,
438 * and ensures that this code is architecturally compliant.
440 for (addr = __phys_to_virt(start); addr < __phys_to_virt(end);
442 pmd_clear(pmd_off_k(addr));
444 flush_tlb_kernel_range(__phys_to_virt(start),
445 __phys_to_virt(end));
447 iotable_init(&map, 1);
451 static int __dma_update_pte(pte_t *pte, pgtable_t token, unsigned long addr,
454 struct page *page = virt_to_page(addr);
455 pgprot_t prot = *(pgprot_t *)data;
457 set_pte_ext(pte, mk_pte(page, prot), 0);
461 static void __dma_remap(struct page *page, size_t size, pgprot_t prot)
463 unsigned long start = (unsigned long) page_address(page);
464 unsigned end = start + size;
466 apply_to_page_range(&init_mm, start, size, __dma_update_pte, &prot);
468 flush_tlb_kernel_range(start, end);
471 static void *__alloc_remap_buffer(struct device *dev, size_t size, gfp_t gfp,
472 pgprot_t prot, struct page **ret_page,
477 page = __dma_alloc_buffer(dev, size, gfp);
481 ptr = __dma_alloc_remap(page, size, gfp, prot, caller);
483 __dma_free_buffer(page, size);
491 static void *__alloc_from_pool(size_t size, struct page **ret_page)
493 struct dma_pool *pool = &atomic_pool;
494 unsigned int count = PAGE_ALIGN(size) >> PAGE_SHIFT;
498 unsigned long align_mask;
501 WARN(1, "coherent pool not initialised!\n");
506 * Align the region allocation - allocations from pool are rather
507 * small, so align them to their order in pages, minimum is a page
508 * size. This helps reduce fragmentation of the DMA space.
510 align_mask = (1 << get_order(size)) - 1;
512 spin_lock_irqsave(&pool->lock, flags);
513 pageno = bitmap_find_next_zero_area(pool->bitmap, pool->nr_pages,
514 0, count, align_mask);
515 if (pageno < pool->nr_pages) {
516 bitmap_set(pool->bitmap, pageno, count);
517 ptr = pool->vaddr + PAGE_SIZE * pageno;
518 *ret_page = pool->pages[pageno];
520 pr_err_once("ERROR: %u KiB atomic DMA coherent pool is too small!\n"
521 "Please increase it with coherent_pool= kernel parameter!\n",
522 (unsigned)pool->size / 1024);
524 spin_unlock_irqrestore(&pool->lock, flags);
529 static bool __in_atomic_pool(void *start, size_t size)
531 struct dma_pool *pool = &atomic_pool;
532 void *end = start + size;
533 void *pool_start = pool->vaddr;
534 void *pool_end = pool->vaddr + pool->size;
536 if (start < pool_start || start >= pool_end)
542 WARN(1, "Wrong coherent size(%p-%p) from atomic pool(%p-%p)\n",
543 start, end - 1, pool_start, pool_end - 1);
548 static int __free_from_pool(void *start, size_t size)
550 struct dma_pool *pool = &atomic_pool;
551 unsigned long pageno, count;
554 if (!__in_atomic_pool(start, size))
557 pageno = (start - pool->vaddr) >> PAGE_SHIFT;
558 count = size >> PAGE_SHIFT;
560 spin_lock_irqsave(&pool->lock, flags);
561 bitmap_clear(pool->bitmap, pageno, count);
562 spin_unlock_irqrestore(&pool->lock, flags);
567 static void *__alloc_from_contiguous(struct device *dev, size_t size,
568 pgprot_t prot, struct page **ret_page,
571 unsigned long order = get_order(size);
572 size_t count = size >> PAGE_SHIFT;
576 page = dma_alloc_from_contiguous(dev, count, order);
580 __dma_clear_buffer(page, size);
582 if (PageHighMem(page)) {
583 ptr = __dma_alloc_remap(page, size, GFP_KERNEL, prot, caller);
585 dma_release_from_contiguous(dev, page, count);
589 __dma_remap(page, size, prot);
590 ptr = page_address(page);
596 static void __free_from_contiguous(struct device *dev, struct page *page,
597 void *cpu_addr, size_t size)
599 if (PageHighMem(page))
600 __dma_free_remap(cpu_addr, size);
602 __dma_remap(page, size, pgprot_kernel);
603 dma_release_from_contiguous(dev, page, size >> PAGE_SHIFT);
606 static inline pgprot_t __get_dma_pgprot(struct dma_attrs *attrs, pgprot_t prot)
608 prot = dma_get_attr(DMA_ATTR_WRITE_COMBINE, attrs) ?
609 pgprot_writecombine(prot) :
610 pgprot_dmacoherent(prot);
616 #else /* !CONFIG_MMU */
620 #define __get_dma_pgprot(attrs, prot) __pgprot(0)
621 #define __alloc_remap_buffer(dev, size, gfp, prot, ret, c) NULL
622 #define __alloc_from_pool(size, ret_page) NULL
623 #define __alloc_from_contiguous(dev, size, prot, ret, c) NULL
624 #define __free_from_pool(cpu_addr, size) 0
625 #define __free_from_contiguous(dev, page, cpu_addr, size) do { } while (0)
626 #define __dma_free_remap(cpu_addr, size) do { } while (0)
628 #endif /* CONFIG_MMU */
630 static void *__alloc_simple_buffer(struct device *dev, size_t size, gfp_t gfp,
631 struct page **ret_page)
634 page = __dma_alloc_buffer(dev, size, gfp);
639 return page_address(page);
644 static void *__dma_alloc(struct device *dev, size_t size, dma_addr_t *handle,
645 gfp_t gfp, pgprot_t prot, bool is_coherent, const void *caller)
647 u64 mask = get_coherent_dma_mask(dev);
648 struct page *page = NULL;
651 #ifdef CONFIG_DMA_API_DEBUG
652 u64 limit = (mask + 1) & ~mask;
653 if (limit && size >= limit) {
654 dev_warn(dev, "coherent allocation too big (requested %#x mask %#llx)\n",
663 if (mask < 0xffffffffULL)
667 * Following is a work-around (a.k.a. hack) to prevent pages
668 * with __GFP_COMP being passed to split_page() which cannot
669 * handle them. The real problem is that this flag probably
670 * should be 0 on ARM as it is not supported on this
671 * platform; see CONFIG_HUGETLBFS.
673 gfp &= ~(__GFP_COMP);
675 *handle = DMA_ERROR_CODE;
676 size = PAGE_ALIGN(size);
678 if (is_coherent || nommu())
679 addr = __alloc_simple_buffer(dev, size, gfp, &page);
680 else if (!(gfp & __GFP_WAIT))
681 addr = __alloc_from_pool(size, &page);
682 else if (!IS_ENABLED(CONFIG_CMA))
683 addr = __alloc_remap_buffer(dev, size, gfp, prot, &page, caller);
685 addr = __alloc_from_contiguous(dev, size, prot, &page, caller);
688 *handle = pfn_to_dma(dev, page_to_pfn(page));
694 * Allocate DMA-coherent memory space and return both the kernel remapped
695 * virtual and bus address for that space.
697 void *arm_dma_alloc(struct device *dev, size_t size, dma_addr_t *handle,
698 gfp_t gfp, struct dma_attrs *attrs)
700 pgprot_t prot = __get_dma_pgprot(attrs, pgprot_kernel);
703 if (dma_alloc_from_coherent(dev, size, handle, &memory))
706 return __dma_alloc(dev, size, handle, gfp, prot, false,
707 __builtin_return_address(0));
710 static void *arm_coherent_dma_alloc(struct device *dev, size_t size,
711 dma_addr_t *handle, gfp_t gfp, struct dma_attrs *attrs)
713 pgprot_t prot = __get_dma_pgprot(attrs, pgprot_kernel);
716 if (dma_alloc_from_coherent(dev, size, handle, &memory))
719 return __dma_alloc(dev, size, handle, gfp, prot, true,
720 __builtin_return_address(0));
724 * Create userspace mapping for the DMA-coherent memory.
726 int arm_dma_mmap(struct device *dev, struct vm_area_struct *vma,
727 void *cpu_addr, dma_addr_t dma_addr, size_t size,
728 struct dma_attrs *attrs)
732 unsigned long nr_vma_pages = (vma->vm_end - vma->vm_start) >> PAGE_SHIFT;
733 unsigned long nr_pages = PAGE_ALIGN(size) >> PAGE_SHIFT;
734 unsigned long pfn = dma_to_pfn(dev, dma_addr);
735 unsigned long off = vma->vm_pgoff;
737 vma->vm_page_prot = __get_dma_pgprot(attrs, vma->vm_page_prot);
739 if (dma_mmap_from_coherent(dev, vma, cpu_addr, size, &ret))
742 if (off < nr_pages && nr_vma_pages <= (nr_pages - off)) {
743 ret = remap_pfn_range(vma, vma->vm_start,
745 vma->vm_end - vma->vm_start,
748 #endif /* CONFIG_MMU */
754 * Free a buffer as defined by the above mapping.
756 static void __arm_dma_free(struct device *dev, size_t size, void *cpu_addr,
757 dma_addr_t handle, struct dma_attrs *attrs,
760 struct page *page = pfn_to_page(dma_to_pfn(dev, handle));
762 if (dma_release_from_coherent(dev, get_order(size), cpu_addr))
765 size = PAGE_ALIGN(size);
767 if (is_coherent || nommu()) {
768 __dma_free_buffer(page, size);
769 } else if (__free_from_pool(cpu_addr, size)) {
771 } else if (!IS_ENABLED(CONFIG_CMA)) {
772 __dma_free_remap(cpu_addr, size);
773 __dma_free_buffer(page, size);
776 * Non-atomic allocations cannot be freed with IRQs disabled
778 WARN_ON(irqs_disabled());
779 __free_from_contiguous(dev, page, cpu_addr, size);
783 void arm_dma_free(struct device *dev, size_t size, void *cpu_addr,
784 dma_addr_t handle, struct dma_attrs *attrs)
786 __arm_dma_free(dev, size, cpu_addr, handle, attrs, false);
789 static void arm_coherent_dma_free(struct device *dev, size_t size, void *cpu_addr,
790 dma_addr_t handle, struct dma_attrs *attrs)
792 __arm_dma_free(dev, size, cpu_addr, handle, attrs, true);
795 int arm_dma_get_sgtable(struct device *dev, struct sg_table *sgt,
796 void *cpu_addr, dma_addr_t handle, size_t size,
797 struct dma_attrs *attrs)
799 struct page *page = pfn_to_page(dma_to_pfn(dev, handle));
802 ret = sg_alloc_table(sgt, 1, GFP_KERNEL);
806 sg_set_page(sgt->sgl, page, PAGE_ALIGN(size), 0);
810 static void dma_cache_maint_page(struct page *page, unsigned long offset,
811 size_t size, enum dma_data_direction dir,
812 void (*op)(const void *, size_t, int))
817 pfn = page_to_pfn(page) + offset / PAGE_SIZE;
821 * A single sg entry may refer to multiple physically contiguous
822 * pages. But we still need to process highmem pages individually.
823 * If highmem is not configured then the bulk of this loop gets
830 page = pfn_to_page(pfn);
832 if (PageHighMem(page)) {
833 if (len + offset > PAGE_SIZE)
834 len = PAGE_SIZE - offset;
836 if (cache_is_vipt_nonaliasing()) {
837 vaddr = kmap_atomic(page);
838 op(vaddr + offset, len, dir);
839 kunmap_atomic(vaddr);
841 vaddr = kmap_high_get(page);
843 op(vaddr + offset, len, dir);
848 vaddr = page_address(page) + offset;
858 * Make an area consistent for devices.
859 * Note: Drivers should NOT use this function directly, as it will break
860 * platforms with CONFIG_DMABOUNCE.
861 * Use the driver DMA support - see dma-mapping.h (dma_sync_*)
863 static void __dma_page_cpu_to_dev(struct page *page, unsigned long off,
864 size_t size, enum dma_data_direction dir)
868 dma_cache_maint_page(page, off, size, dir, dmac_map_area);
870 paddr = page_to_phys(page) + off;
871 if (dir == DMA_FROM_DEVICE) {
872 outer_inv_range(paddr, paddr + size);
874 outer_clean_range(paddr, paddr + size);
876 /* FIXME: non-speculating: flush on bidirectional mappings? */
879 static void __dma_page_dev_to_cpu(struct page *page, unsigned long off,
880 size_t size, enum dma_data_direction dir)
882 unsigned long paddr = page_to_phys(page) + off;
884 /* FIXME: non-speculating: not required */
885 /* don't bother invalidating if DMA to device */
886 if (dir != DMA_TO_DEVICE)
887 outer_inv_range(paddr, paddr + size);
889 dma_cache_maint_page(page, off, size, dir, dmac_unmap_area);
892 * Mark the D-cache clean for this page to avoid extra flushing.
894 if (dir != DMA_TO_DEVICE && off == 0 && size >= PAGE_SIZE)
895 set_bit(PG_dcache_clean, &page->flags);
899 * arm_dma_map_sg - map a set of SG buffers for streaming mode DMA
900 * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices
901 * @sg: list of buffers
902 * @nents: number of buffers to map
903 * @dir: DMA transfer direction
905 * Map a set of buffers described by scatterlist in streaming mode for DMA.
906 * This is the scatter-gather version of the dma_map_single interface.
907 * Here the scatter gather list elements are each tagged with the
908 * appropriate dma address and length. They are obtained via
909 * sg_dma_{address,length}.
911 * Device ownership issues as mentioned for dma_map_single are the same
914 int arm_dma_map_sg(struct device *dev, struct scatterlist *sg, int nents,
915 enum dma_data_direction dir, struct dma_attrs *attrs)
917 struct dma_map_ops *ops = get_dma_ops(dev);
918 struct scatterlist *s;
921 for_each_sg(sg, s, nents, i) {
922 #ifdef CONFIG_NEED_SG_DMA_LENGTH
923 s->dma_length = s->length;
925 s->dma_address = ops->map_page(dev, sg_page(s), s->offset,
926 s->length, dir, attrs);
927 if (dma_mapping_error(dev, s->dma_address))
933 for_each_sg(sg, s, i, j)
934 ops->unmap_page(dev, sg_dma_address(s), sg_dma_len(s), dir, attrs);
939 * arm_dma_unmap_sg - unmap a set of SG buffers mapped by dma_map_sg
940 * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices
941 * @sg: list of buffers
942 * @nents: number of buffers to unmap (same as was passed to dma_map_sg)
943 * @dir: DMA transfer direction (same as was passed to dma_map_sg)
945 * Unmap a set of streaming mode DMA translations. Again, CPU access
946 * rules concerning calls here are the same as for dma_unmap_single().
948 void arm_dma_unmap_sg(struct device *dev, struct scatterlist *sg, int nents,
949 enum dma_data_direction dir, struct dma_attrs *attrs)
951 struct dma_map_ops *ops = get_dma_ops(dev);
952 struct scatterlist *s;
956 for_each_sg(sg, s, nents, i)
957 ops->unmap_page(dev, sg_dma_address(s), sg_dma_len(s), dir, attrs);
961 * arm_dma_sync_sg_for_cpu
962 * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices
963 * @sg: list of buffers
964 * @nents: number of buffers to map (returned from dma_map_sg)
965 * @dir: DMA transfer direction (same as was passed to dma_map_sg)
967 void arm_dma_sync_sg_for_cpu(struct device *dev, struct scatterlist *sg,
968 int nents, enum dma_data_direction dir)
970 struct dma_map_ops *ops = get_dma_ops(dev);
971 struct scatterlist *s;
974 for_each_sg(sg, s, nents, i)
975 ops->sync_single_for_cpu(dev, sg_dma_address(s), s->length,
980 * arm_dma_sync_sg_for_device
981 * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices
982 * @sg: list of buffers
983 * @nents: number of buffers to map (returned from dma_map_sg)
984 * @dir: DMA transfer direction (same as was passed to dma_map_sg)
986 void arm_dma_sync_sg_for_device(struct device *dev, struct scatterlist *sg,
987 int nents, enum dma_data_direction dir)
989 struct dma_map_ops *ops = get_dma_ops(dev);
990 struct scatterlist *s;
993 for_each_sg(sg, s, nents, i)
994 ops->sync_single_for_device(dev, sg_dma_address(s), s->length,
999 * Return whether the given device DMA address mask can be supported
1000 * properly. For example, if your device can only drive the low 24-bits
1001 * during bus mastering, then you would pass 0x00ffffff as the mask
1004 int dma_supported(struct device *dev, u64 mask)
1006 if (mask < (u64)arm_dma_limit)
1010 EXPORT_SYMBOL(dma_supported);
1012 int arm_dma_set_mask(struct device *dev, u64 dma_mask)
1014 if (!dev->dma_mask || !dma_supported(dev, dma_mask))
1017 *dev->dma_mask = dma_mask;
1022 #define PREALLOC_DMA_DEBUG_ENTRIES 4096
1024 static int __init dma_debug_do_init(void)
1026 dma_debug_init(PREALLOC_DMA_DEBUG_ENTRIES);
1029 fs_initcall(dma_debug_do_init);
1031 #ifdef CONFIG_ARM_DMA_USE_IOMMU
1035 static inline dma_addr_t __alloc_iova(struct dma_iommu_mapping *mapping,
1038 unsigned int order = get_order(size);
1039 unsigned int align = 0;
1040 unsigned int count, start;
1041 unsigned long flags;
1043 if (order > CONFIG_ARM_DMA_IOMMU_ALIGNMENT)
1044 order = CONFIG_ARM_DMA_IOMMU_ALIGNMENT;
1046 count = ((PAGE_ALIGN(size) >> PAGE_SHIFT) +
1047 (1 << mapping->order) - 1) >> mapping->order;
1049 if (order > mapping->order)
1050 align = (1 << (order - mapping->order)) - 1;
1052 spin_lock_irqsave(&mapping->lock, flags);
1053 start = bitmap_find_next_zero_area(mapping->bitmap, mapping->bits, 0,
1055 if (start > mapping->bits) {
1056 spin_unlock_irqrestore(&mapping->lock, flags);
1057 return DMA_ERROR_CODE;
1060 bitmap_set(mapping->bitmap, start, count);
1061 spin_unlock_irqrestore(&mapping->lock, flags);
1063 return mapping->base + (start << (mapping->order + PAGE_SHIFT));
1066 static inline void __free_iova(struct dma_iommu_mapping *mapping,
1067 dma_addr_t addr, size_t size)
1069 unsigned int start = (addr - mapping->base) >>
1070 (mapping->order + PAGE_SHIFT);
1071 unsigned int count = ((size >> PAGE_SHIFT) +
1072 (1 << mapping->order) - 1) >> mapping->order;
1073 unsigned long flags;
1075 spin_lock_irqsave(&mapping->lock, flags);
1076 bitmap_clear(mapping->bitmap, start, count);
1077 spin_unlock_irqrestore(&mapping->lock, flags);
1080 static struct page **__iommu_alloc_buffer(struct device *dev, size_t size,
1081 gfp_t gfp, struct dma_attrs *attrs)
1083 struct page **pages;
1084 int count = size >> PAGE_SHIFT;
1085 int array_size = count * sizeof(struct page *);
1088 if (array_size <= PAGE_SIZE)
1089 pages = kzalloc(array_size, gfp);
1091 pages = vzalloc(array_size);
1095 if (dma_get_attr(DMA_ATTR_FORCE_CONTIGUOUS, attrs))
1097 unsigned long order = get_order(size);
1100 page = dma_alloc_from_contiguous(dev, count, order);
1104 __dma_clear_buffer(page, size);
1106 for (i = 0; i < count; i++)
1107 pages[i] = page + i;
1113 * IOMMU can map any pages, so himem can also be used here
1115 gfp |= __GFP_NOWARN | __GFP_HIGHMEM;
1118 int j, order = __fls(count);
1120 pages[i] = alloc_pages(gfp, order);
1121 while (!pages[i] && order)
1122 pages[i] = alloc_pages(gfp, --order);
1127 split_page(pages[i], order);
1130 pages[i + j] = pages[i] + j;
1133 __dma_clear_buffer(pages[i], PAGE_SIZE << order);
1135 count -= 1 << order;
1142 __free_pages(pages[i], 0);
1143 if (array_size <= PAGE_SIZE)
1150 static int __iommu_free_buffer(struct device *dev, struct page **pages,
1151 size_t size, struct dma_attrs *attrs)
1153 int count = size >> PAGE_SHIFT;
1154 int array_size = count * sizeof(struct page *);
1157 if (dma_get_attr(DMA_ATTR_FORCE_CONTIGUOUS, attrs)) {
1158 dma_release_from_contiguous(dev, pages[0], count);
1160 for (i = 0; i < count; i++)
1162 __free_pages(pages[i], 0);
1165 if (array_size <= PAGE_SIZE)
1173 * Create a CPU mapping for a specified pages
1176 __iommu_alloc_remap(struct page **pages, size_t size, gfp_t gfp, pgprot_t prot,
1179 unsigned int i, nr_pages = PAGE_ALIGN(size) >> PAGE_SHIFT;
1180 struct vm_struct *area;
1183 area = get_vm_area_caller(size, VM_ARM_DMA_CONSISTENT | VM_USERMAP,
1188 area->pages = pages;
1189 area->nr_pages = nr_pages;
1190 p = (unsigned long)area->addr;
1192 for (i = 0; i < nr_pages; i++) {
1193 phys_addr_t phys = __pfn_to_phys(page_to_pfn(pages[i]));
1194 if (ioremap_page_range(p, p + PAGE_SIZE, phys, prot))
1200 unmap_kernel_range((unsigned long)area->addr, size);
1206 * Create a mapping in device IO address space for specified pages
1209 __iommu_create_mapping(struct device *dev, struct page **pages, size_t size)
1211 struct dma_iommu_mapping *mapping = dev->archdata.mapping;
1212 unsigned int count = PAGE_ALIGN(size) >> PAGE_SHIFT;
1213 dma_addr_t dma_addr, iova;
1214 int i, ret = DMA_ERROR_CODE;
1216 dma_addr = __alloc_iova(mapping, size);
1217 if (dma_addr == DMA_ERROR_CODE)
1221 for (i = 0; i < count; ) {
1222 unsigned int next_pfn = page_to_pfn(pages[i]) + 1;
1223 phys_addr_t phys = page_to_phys(pages[i]);
1224 unsigned int len, j;
1226 for (j = i + 1; j < count; j++, next_pfn++)
1227 if (page_to_pfn(pages[j]) != next_pfn)
1230 len = (j - i) << PAGE_SHIFT;
1231 ret = iommu_map(mapping->domain, iova, phys, len, 0);
1239 iommu_unmap(mapping->domain, dma_addr, iova-dma_addr);
1240 __free_iova(mapping, dma_addr, size);
1241 return DMA_ERROR_CODE;
1244 static int __iommu_remove_mapping(struct device *dev, dma_addr_t iova, size_t size)
1246 struct dma_iommu_mapping *mapping = dev->archdata.mapping;
1249 * add optional in-page offset from iova to size and align
1250 * result to page size
1252 size = PAGE_ALIGN((iova & ~PAGE_MASK) + size);
1255 iommu_unmap(mapping->domain, iova, size);
1256 __free_iova(mapping, iova, size);
1260 static struct page **__atomic_get_pages(void *addr)
1262 struct dma_pool *pool = &atomic_pool;
1263 struct page **pages = pool->pages;
1264 int offs = (addr - pool->vaddr) >> PAGE_SHIFT;
1266 return pages + offs;
1269 static struct page **__iommu_get_pages(void *cpu_addr, struct dma_attrs *attrs)
1271 struct vm_struct *area;
1273 if (__in_atomic_pool(cpu_addr, PAGE_SIZE))
1274 return __atomic_get_pages(cpu_addr);
1276 if (dma_get_attr(DMA_ATTR_NO_KERNEL_MAPPING, attrs))
1279 area = find_vm_area(cpu_addr);
1280 if (area && (area->flags & VM_ARM_DMA_CONSISTENT))
1285 static void *__iommu_alloc_atomic(struct device *dev, size_t size,
1291 addr = __alloc_from_pool(size, &page);
1295 *handle = __iommu_create_mapping(dev, &page, size);
1296 if (*handle == DMA_ERROR_CODE)
1302 __free_from_pool(addr, size);
1306 static void __iommu_free_atomic(struct device *dev, void *cpu_addr,
1307 dma_addr_t handle, size_t size)
1309 __iommu_remove_mapping(dev, handle, size);
1310 __free_from_pool(cpu_addr, size);
1313 static void *arm_iommu_alloc_attrs(struct device *dev, size_t size,
1314 dma_addr_t *handle, gfp_t gfp, struct dma_attrs *attrs)
1316 pgprot_t prot = __get_dma_pgprot(attrs, pgprot_kernel);
1317 struct page **pages;
1320 *handle = DMA_ERROR_CODE;
1321 size = PAGE_ALIGN(size);
1323 if (!(gfp & __GFP_WAIT))
1324 return __iommu_alloc_atomic(dev, size, handle);
1326 pages = __iommu_alloc_buffer(dev, size, gfp, attrs);
1330 *handle = __iommu_create_mapping(dev, pages, size);
1331 if (*handle == DMA_ERROR_CODE)
1334 if (dma_get_attr(DMA_ATTR_NO_KERNEL_MAPPING, attrs))
1337 addr = __iommu_alloc_remap(pages, size, gfp, prot,
1338 __builtin_return_address(0));
1345 __iommu_remove_mapping(dev, *handle, size);
1347 __iommu_free_buffer(dev, pages, size, attrs);
1351 static int arm_iommu_mmap_attrs(struct device *dev, struct vm_area_struct *vma,
1352 void *cpu_addr, dma_addr_t dma_addr, size_t size,
1353 struct dma_attrs *attrs)
1355 unsigned long uaddr = vma->vm_start;
1356 unsigned long usize = vma->vm_end - vma->vm_start;
1357 struct page **pages = __iommu_get_pages(cpu_addr, attrs);
1359 vma->vm_page_prot = __get_dma_pgprot(attrs, vma->vm_page_prot);
1365 int ret = vm_insert_page(vma, uaddr, *pages++);
1367 pr_err("Remapping memory failed: %d\n", ret);
1372 } while (usize > 0);
1378 * free a page as defined by the above mapping.
1379 * Must not be called with IRQs disabled.
1381 void arm_iommu_free_attrs(struct device *dev, size_t size, void *cpu_addr,
1382 dma_addr_t handle, struct dma_attrs *attrs)
1384 struct page **pages = __iommu_get_pages(cpu_addr, attrs);
1385 size = PAGE_ALIGN(size);
1388 WARN(1, "trying to free invalid coherent area: %p\n", cpu_addr);
1392 if (__in_atomic_pool(cpu_addr, size)) {
1393 __iommu_free_atomic(dev, cpu_addr, handle, size);
1397 if (!dma_get_attr(DMA_ATTR_NO_KERNEL_MAPPING, attrs)) {
1398 unmap_kernel_range((unsigned long)cpu_addr, size);
1402 __iommu_remove_mapping(dev, handle, size);
1403 __iommu_free_buffer(dev, pages, size, attrs);
1406 static int arm_iommu_get_sgtable(struct device *dev, struct sg_table *sgt,
1407 void *cpu_addr, dma_addr_t dma_addr,
1408 size_t size, struct dma_attrs *attrs)
1410 unsigned int count = PAGE_ALIGN(size) >> PAGE_SHIFT;
1411 struct page **pages = __iommu_get_pages(cpu_addr, attrs);
1416 return sg_alloc_table_from_pages(sgt, pages, count, 0, size,
1421 * Map a part of the scatter-gather list into contiguous io address space
1423 static int __map_sg_chunk(struct device *dev, struct scatterlist *sg,
1424 size_t size, dma_addr_t *handle,
1425 enum dma_data_direction dir, struct dma_attrs *attrs,
1428 struct dma_iommu_mapping *mapping = dev->archdata.mapping;
1429 dma_addr_t iova, iova_base;
1432 struct scatterlist *s;
1434 size = PAGE_ALIGN(size);
1435 *handle = DMA_ERROR_CODE;
1437 iova_base = iova = __alloc_iova(mapping, size);
1438 if (iova == DMA_ERROR_CODE)
1441 for (count = 0, s = sg; count < (size >> PAGE_SHIFT); s = sg_next(s)) {
1442 phys_addr_t phys = page_to_phys(sg_page(s));
1443 unsigned int len = PAGE_ALIGN(s->offset + s->length);
1446 !dma_get_attr(DMA_ATTR_SKIP_CPU_SYNC, attrs))
1447 __dma_page_cpu_to_dev(sg_page(s), s->offset, s->length, dir);
1449 ret = iommu_map(mapping->domain, iova, phys, len, 0);
1452 count += len >> PAGE_SHIFT;
1455 *handle = iova_base;
1459 iommu_unmap(mapping->domain, iova_base, count * PAGE_SIZE);
1460 __free_iova(mapping, iova_base, size);
1464 static int __iommu_map_sg(struct device *dev, struct scatterlist *sg, int nents,
1465 enum dma_data_direction dir, struct dma_attrs *attrs,
1468 struct scatterlist *s = sg, *dma = sg, *start = sg;
1470 unsigned int offset = s->offset;
1471 unsigned int size = s->offset + s->length;
1472 unsigned int max = dma_get_max_seg_size(dev);
1474 for (i = 1; i < nents; i++) {
1477 s->dma_address = DMA_ERROR_CODE;
1480 if (s->offset || (size & ~PAGE_MASK) || size + s->length > max) {
1481 if (__map_sg_chunk(dev, start, size, &dma->dma_address,
1482 dir, attrs, is_coherent) < 0)
1485 dma->dma_address += offset;
1486 dma->dma_length = size - offset;
1488 size = offset = s->offset;
1495 if (__map_sg_chunk(dev, start, size, &dma->dma_address, dir, attrs,
1499 dma->dma_address += offset;
1500 dma->dma_length = size - offset;
1505 for_each_sg(sg, s, count, i)
1506 __iommu_remove_mapping(dev, sg_dma_address(s), sg_dma_len(s));
1511 * arm_coherent_iommu_map_sg - map a set of SG buffers for streaming mode DMA
1512 * @dev: valid struct device pointer
1513 * @sg: list of buffers
1514 * @nents: number of buffers to map
1515 * @dir: DMA transfer direction
1517 * Map a set of i/o coherent buffers described by scatterlist in streaming
1518 * mode for DMA. The scatter gather list elements are merged together (if
1519 * possible) and tagged with the appropriate dma address and length. They are
1520 * obtained via sg_dma_{address,length}.
1522 int arm_coherent_iommu_map_sg(struct device *dev, struct scatterlist *sg,
1523 int nents, enum dma_data_direction dir, struct dma_attrs *attrs)
1525 return __iommu_map_sg(dev, sg, nents, dir, attrs, true);
1529 * arm_iommu_map_sg - map a set of SG buffers for streaming mode DMA
1530 * @dev: valid struct device pointer
1531 * @sg: list of buffers
1532 * @nents: number of buffers to map
1533 * @dir: DMA transfer direction
1535 * Map a set of buffers described by scatterlist in streaming mode for DMA.
1536 * The scatter gather list elements are merged together (if possible) and
1537 * tagged with the appropriate dma address and length. They are obtained via
1538 * sg_dma_{address,length}.
1540 int arm_iommu_map_sg(struct device *dev, struct scatterlist *sg,
1541 int nents, enum dma_data_direction dir, struct dma_attrs *attrs)
1543 return __iommu_map_sg(dev, sg, nents, dir, attrs, false);
1546 static void __iommu_unmap_sg(struct device *dev, struct scatterlist *sg,
1547 int nents, enum dma_data_direction dir, struct dma_attrs *attrs,
1550 struct scatterlist *s;
1553 for_each_sg(sg, s, nents, i) {
1555 __iommu_remove_mapping(dev, sg_dma_address(s),
1558 !dma_get_attr(DMA_ATTR_SKIP_CPU_SYNC, attrs))
1559 __dma_page_dev_to_cpu(sg_page(s), s->offset,
1565 * arm_coherent_iommu_unmap_sg - unmap a set of SG buffers mapped by dma_map_sg
1566 * @dev: valid struct device pointer
1567 * @sg: list of buffers
1568 * @nents: number of buffers to unmap (same as was passed to dma_map_sg)
1569 * @dir: DMA transfer direction (same as was passed to dma_map_sg)
1571 * Unmap a set of streaming mode DMA translations. Again, CPU access
1572 * rules concerning calls here are the same as for dma_unmap_single().
1574 void arm_coherent_iommu_unmap_sg(struct device *dev, struct scatterlist *sg,
1575 int nents, enum dma_data_direction dir, struct dma_attrs *attrs)
1577 __iommu_unmap_sg(dev, sg, nents, dir, attrs, true);
1581 * arm_iommu_unmap_sg - unmap a set of SG buffers mapped by dma_map_sg
1582 * @dev: valid struct device pointer
1583 * @sg: list of buffers
1584 * @nents: number of buffers to unmap (same as was passed to dma_map_sg)
1585 * @dir: DMA transfer direction (same as was passed to dma_map_sg)
1587 * Unmap a set of streaming mode DMA translations. Again, CPU access
1588 * rules concerning calls here are the same as for dma_unmap_single().
1590 void arm_iommu_unmap_sg(struct device *dev, struct scatterlist *sg, int nents,
1591 enum dma_data_direction dir, struct dma_attrs *attrs)
1593 __iommu_unmap_sg(dev, sg, nents, dir, attrs, false);
1597 * arm_iommu_sync_sg_for_cpu
1598 * @dev: valid struct device pointer
1599 * @sg: list of buffers
1600 * @nents: number of buffers to map (returned from dma_map_sg)
1601 * @dir: DMA transfer direction (same as was passed to dma_map_sg)
1603 void arm_iommu_sync_sg_for_cpu(struct device *dev, struct scatterlist *sg,
1604 int nents, enum dma_data_direction dir)
1606 struct scatterlist *s;
1609 for_each_sg(sg, s, nents, i)
1610 __dma_page_dev_to_cpu(sg_page(s), s->offset, s->length, dir);
1615 * arm_iommu_sync_sg_for_device
1616 * @dev: valid struct device pointer
1617 * @sg: list of buffers
1618 * @nents: number of buffers to map (returned from dma_map_sg)
1619 * @dir: DMA transfer direction (same as was passed to dma_map_sg)
1621 void arm_iommu_sync_sg_for_device(struct device *dev, struct scatterlist *sg,
1622 int nents, enum dma_data_direction dir)
1624 struct scatterlist *s;
1627 for_each_sg(sg, s, nents, i)
1628 __dma_page_cpu_to_dev(sg_page(s), s->offset, s->length, dir);
1633 * arm_coherent_iommu_map_page
1634 * @dev: valid struct device pointer
1635 * @page: page that buffer resides in
1636 * @offset: offset into page for start of buffer
1637 * @size: size of buffer to map
1638 * @dir: DMA transfer direction
1640 * Coherent IOMMU aware version of arm_dma_map_page()
1642 static dma_addr_t arm_coherent_iommu_map_page(struct device *dev, struct page *page,
1643 unsigned long offset, size_t size, enum dma_data_direction dir,
1644 struct dma_attrs *attrs)
1646 struct dma_iommu_mapping *mapping = dev->archdata.mapping;
1647 dma_addr_t dma_addr;
1648 int ret, len = PAGE_ALIGN(size + offset);
1650 dma_addr = __alloc_iova(mapping, len);
1651 if (dma_addr == DMA_ERROR_CODE)
1654 ret = iommu_map(mapping->domain, dma_addr, page_to_phys(page), len, 0);
1658 return dma_addr + offset;
1660 __free_iova(mapping, dma_addr, len);
1661 return DMA_ERROR_CODE;
1665 * arm_iommu_map_page
1666 * @dev: valid struct device pointer
1667 * @page: page that buffer resides in
1668 * @offset: offset into page for start of buffer
1669 * @size: size of buffer to map
1670 * @dir: DMA transfer direction
1672 * IOMMU aware version of arm_dma_map_page()
1674 static dma_addr_t arm_iommu_map_page(struct device *dev, struct page *page,
1675 unsigned long offset, size_t size, enum dma_data_direction dir,
1676 struct dma_attrs *attrs)
1678 if (!dma_get_attr(DMA_ATTR_SKIP_CPU_SYNC, attrs))
1679 __dma_page_cpu_to_dev(page, offset, size, dir);
1681 return arm_coherent_iommu_map_page(dev, page, offset, size, dir, attrs);
1685 * arm_coherent_iommu_unmap_page
1686 * @dev: valid struct device pointer
1687 * @handle: DMA address of buffer
1688 * @size: size of buffer (same as passed to dma_map_page)
1689 * @dir: DMA transfer direction (same as passed to dma_map_page)
1691 * Coherent IOMMU aware version of arm_dma_unmap_page()
1693 static void arm_coherent_iommu_unmap_page(struct device *dev, dma_addr_t handle,
1694 size_t size, enum dma_data_direction dir,
1695 struct dma_attrs *attrs)
1697 struct dma_iommu_mapping *mapping = dev->archdata.mapping;
1698 dma_addr_t iova = handle & PAGE_MASK;
1699 int offset = handle & ~PAGE_MASK;
1700 int len = PAGE_ALIGN(size + offset);
1705 iommu_unmap(mapping->domain, iova, len);
1706 __free_iova(mapping, iova, len);
1710 * arm_iommu_unmap_page
1711 * @dev: valid struct device pointer
1712 * @handle: DMA address of buffer
1713 * @size: size of buffer (same as passed to dma_map_page)
1714 * @dir: DMA transfer direction (same as passed to dma_map_page)
1716 * IOMMU aware version of arm_dma_unmap_page()
1718 static void arm_iommu_unmap_page(struct device *dev, dma_addr_t handle,
1719 size_t size, enum dma_data_direction dir,
1720 struct dma_attrs *attrs)
1722 struct dma_iommu_mapping *mapping = dev->archdata.mapping;
1723 dma_addr_t iova = handle & PAGE_MASK;
1724 struct page *page = phys_to_page(iommu_iova_to_phys(mapping->domain, iova));
1725 int offset = handle & ~PAGE_MASK;
1726 int len = PAGE_ALIGN(size + offset);
1731 if (!dma_get_attr(DMA_ATTR_SKIP_CPU_SYNC, attrs))
1732 __dma_page_dev_to_cpu(page, offset, size, dir);
1734 iommu_unmap(mapping->domain, iova, len);
1735 __free_iova(mapping, iova, len);
1738 static void arm_iommu_sync_single_for_cpu(struct device *dev,
1739 dma_addr_t handle, size_t size, enum dma_data_direction dir)
1741 struct dma_iommu_mapping *mapping = dev->archdata.mapping;
1742 dma_addr_t iova = handle & PAGE_MASK;
1743 struct page *page = phys_to_page(iommu_iova_to_phys(mapping->domain, iova));
1744 unsigned int offset = handle & ~PAGE_MASK;
1749 __dma_page_dev_to_cpu(page, offset, size, dir);
1752 static void arm_iommu_sync_single_for_device(struct device *dev,
1753 dma_addr_t handle, size_t size, enum dma_data_direction dir)
1755 struct dma_iommu_mapping *mapping = dev->archdata.mapping;
1756 dma_addr_t iova = handle & PAGE_MASK;
1757 struct page *page = phys_to_page(iommu_iova_to_phys(mapping->domain, iova));
1758 unsigned int offset = handle & ~PAGE_MASK;
1763 __dma_page_cpu_to_dev(page, offset, size, dir);
1766 struct dma_map_ops iommu_ops = {
1767 .alloc = arm_iommu_alloc_attrs,
1768 .free = arm_iommu_free_attrs,
1769 .mmap = arm_iommu_mmap_attrs,
1770 .get_sgtable = arm_iommu_get_sgtable,
1772 .map_page = arm_iommu_map_page,
1773 .unmap_page = arm_iommu_unmap_page,
1774 .sync_single_for_cpu = arm_iommu_sync_single_for_cpu,
1775 .sync_single_for_device = arm_iommu_sync_single_for_device,
1777 .map_sg = arm_iommu_map_sg,
1778 .unmap_sg = arm_iommu_unmap_sg,
1779 .sync_sg_for_cpu = arm_iommu_sync_sg_for_cpu,
1780 .sync_sg_for_device = arm_iommu_sync_sg_for_device,
1782 .set_dma_mask = arm_dma_set_mask,
1785 struct dma_map_ops iommu_coherent_ops = {
1786 .alloc = arm_iommu_alloc_attrs,
1787 .free = arm_iommu_free_attrs,
1788 .mmap = arm_iommu_mmap_attrs,
1789 .get_sgtable = arm_iommu_get_sgtable,
1791 .map_page = arm_coherent_iommu_map_page,
1792 .unmap_page = arm_coherent_iommu_unmap_page,
1794 .map_sg = arm_coherent_iommu_map_sg,
1795 .unmap_sg = arm_coherent_iommu_unmap_sg,
1797 .set_dma_mask = arm_dma_set_mask,
1801 * arm_iommu_create_mapping
1802 * @bus: pointer to the bus holding the client device (for IOMMU calls)
1803 * @base: start address of the valid IO address space
1804 * @size: size of the valid IO address space
1805 * @order: accuracy of the IO addresses allocations
1807 * Creates a mapping structure which holds information about used/unused
1808 * IO address ranges, which is required to perform memory allocation and
1809 * mapping with IOMMU aware functions.
1811 * The client device need to be attached to the mapping with
1812 * arm_iommu_attach_device function.
1814 struct dma_iommu_mapping *
1815 arm_iommu_create_mapping(struct bus_type *bus, dma_addr_t base, size_t size,
1818 unsigned int count = size >> (PAGE_SHIFT + order);
1819 unsigned int bitmap_size = BITS_TO_LONGS(count) * sizeof(long);
1820 struct dma_iommu_mapping *mapping;
1824 return ERR_PTR(-EINVAL);
1826 mapping = kzalloc(sizeof(struct dma_iommu_mapping), GFP_KERNEL);
1830 mapping->bitmap = kzalloc(bitmap_size, GFP_KERNEL);
1831 if (!mapping->bitmap)
1834 mapping->base = base;
1835 mapping->bits = BITS_PER_BYTE * bitmap_size;
1836 mapping->order = order;
1837 spin_lock_init(&mapping->lock);
1839 mapping->domain = iommu_domain_alloc(bus);
1840 if (!mapping->domain)
1843 kref_init(&mapping->kref);
1846 kfree(mapping->bitmap);
1850 return ERR_PTR(err);
1852 EXPORT_SYMBOL_GPL(arm_iommu_create_mapping);
1854 static void release_iommu_mapping(struct kref *kref)
1856 struct dma_iommu_mapping *mapping =
1857 container_of(kref, struct dma_iommu_mapping, kref);
1859 iommu_domain_free(mapping->domain);
1860 kfree(mapping->bitmap);
1864 void arm_iommu_release_mapping(struct dma_iommu_mapping *mapping)
1867 kref_put(&mapping->kref, release_iommu_mapping);
1869 EXPORT_SYMBOL_GPL(arm_iommu_release_mapping);
1872 * arm_iommu_attach_device
1873 * @dev: valid struct device pointer
1874 * @mapping: io address space mapping structure (returned from
1875 * arm_iommu_create_mapping)
1877 * Attaches specified io address space mapping to the provided device,
1878 * this replaces the dma operations (dma_map_ops pointer) with the
1879 * IOMMU aware version. More than one client might be attached to
1880 * the same io address space mapping.
1882 int arm_iommu_attach_device(struct device *dev,
1883 struct dma_iommu_mapping *mapping)
1887 err = iommu_attach_device(mapping->domain, dev);
1891 kref_get(&mapping->kref);
1892 dev->archdata.mapping = mapping;
1893 set_dma_ops(dev, &iommu_ops);
1895 pr_debug("Attached IOMMU controller to %s device.\n", dev_name(dev));
1898 EXPORT_SYMBOL_GPL(arm_iommu_attach_device);
1901 * arm_iommu_detach_device
1902 * @dev: valid struct device pointer
1904 * Detaches the provided device from a previously attached map.
1905 * This voids the dma operations (dma_map_ops pointer)
1907 void arm_iommu_detach_device(struct device *dev)
1909 struct dma_iommu_mapping *mapping;
1911 mapping = to_dma_iommu_mapping(dev);
1913 dev_warn(dev, "Not attached\n");
1917 iommu_detach_device(mapping->domain, dev);
1918 kref_put(&mapping->kref, release_iommu_mapping);
1920 set_dma_ops(dev, NULL);
1922 pr_debug("Detached IOMMU controller from %s device.\n", dev_name(dev));
1924 EXPORT_SYMBOL_GPL(arm_iommu_detach_device);