2 * arch/arm/include/asm/tc2_pm_setup.S
4 * Created by: Nicolas Pitre, October 2012
5 ( (based on dcscb_setup.S by Dave Martin)
6 * Copyright: (C) 2012 Linaro Limited
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
14 #include <linux/linkage.h>
18 #define SPC_PHYS_BASE 0x7FFF0000
19 #define SPC_WAKE_INT_STAT 0xb2c
21 #define SNOOP_CTL_A15 0x404
22 #define SNOOP_CTL_A7 0x504
24 #define A15_SNOOP_MASK (0x3 << 7)
25 #define A7_SNOOP_MASK (0x1 << 13)
27 #define A15_BX_ADDR0 0xB68
31 mrc p15, 0, r0, c0, c0, 5
32 ubfx r1, r0, #0, #4 @ r1 = cpu
33 ubfx r2, r0, #8, #4 @ r2 = cluster
34 add r1, r1, r2, lsl #2 @ r1 = index of CPU in WAKE_INT_STAT
35 ldr r3, =SPC_PHYS_BASE + SPC_WAKE_INT_STAT
39 wfieq @ if no pending IRQ reenters wfi
44 * Enable cluster-level coherency, in preparation for turning on the MMU.
45 * The ACTLR SMP bit does not need to be set here, because cpu_resume()
46 * already restores that.
49 ENTRY(tc2_pm_power_up_setup)
54 b cci_enable_port_for_self
56 2: @ Clear the BX addr register
57 ldr r3, =SPC_PHYS_BASE + A15_BX_ADDR0
58 mrc p15, 0, r0, c0, c0, 5 @ MPIDR
59 ubfx r1, r0, #8, #4 @ cluster
60 ubfx r0, r0, #0, #4 @ cpu
61 add r3, r3, r1, lsl #4
63 str r1, [r3, r0, lsl #2]
68 ENDPROC(tc2_pm_power_up_setup)