arch/arm/mach-vexpress/ct-ca9x4.c

   1 /*
   2  * Versatile Express Core Tile Cortex A9x4 Support
   3  */
   4 #include <linux/init.h>
   5 #include <linux/gfp.h>
   6 #include <linux/device.h>
   7 #include <linux/dma-mapping.h>
   8 #include <linux/platform_device.h>
   9 #include <linux/amba/bus.h>
  10 #include <linux/amba/clcd.h>
  11 #include <linux/clkdev.h>
  12
  13 #include <asm/pgtable.h>
  14 #include <asm/hardware/arm_timer.h>
  15 #include <asm/hardware/cache-l2x0.h>
  16 #include <asm/hardware/gic.h>
  17 #include <asm/mach-types.h>
  18 #include <asm/pmu.h>
  19 #include <asm/smp_twd.h>
  20
  21 #include <mach/ct-ca9x4.h>
  22
  23 #include <plat/timer-sp.h>
  24
  25 #include <asm/mach/arch.h>
  26 #include <asm/mach/map.h>
  27 #include <asm/mach/time.h>
  28
  29 #include "core.h"
  30
  31 #include <mach/motherboard.h>
  32
  33 #define V2M_PA_CS7      0x10000000
  34
  35 static struct map_desc ct_ca9x4_io_desc[] __initdata = {
  36         {
  37                 .virtual        = __MMIO_P2V(CT_CA9X4_MPIC),
  38                 .pfn            = __phys_to_pfn(CT_CA9X4_MPIC),
  39                 .length         = SZ_16K,
  40                 .type           = MT_DEVICE,
  41         }, {
  42                 .virtual        = __MMIO_P2V(CT_CA9X4_SP804_TIMER),
  43                 .pfn            = __phys_to_pfn(CT_CA9X4_SP804_TIMER),
  44                 .length         = SZ_4K,
  45                 .type           = MT_DEVICE,
  46         }, {
  47                 .virtual        = __MMIO_P2V(CT_CA9X4_L2CC),
  48                 .pfn            = __phys_to_pfn(CT_CA9X4_L2CC),
  49                 .length         = SZ_4K,
  50                 .type           = MT_DEVICE,
  51         },
  52 };
  53
  54 static void __init ct_ca9x4_map_io(void)
  55 {
  56 #ifdef CONFIG_LOCAL_TIMERS
  57         twd_base = MMIO_P2V(A9_MPCORE_TWD);
  58 #endif
  59         v2m_map_io(ct_ca9x4_io_desc, ARRAY_SIZE(ct_ca9x4_io_desc));
  60 }
  61
  62 void __iomem *gic_cpu_base_addr;
  63
  64 static void __init ct_ca9x4_init_irq(void)
  65 {
  66         gic_cpu_base_addr = MMIO_P2V(A9_MPCORE_GIC_CPU);
  67         gic_dist_init(0, MMIO_P2V(A9_MPCORE_GIC_DIST), 29);
  68         gic_cpu_init(0, gic_cpu_base_addr);
  69 }
  70
  71 #if 0
  72 static void __init ct_ca9x4_timer_init(void)
  73 {
  74         writel(0, MMIO_P2V(CT_CA9X4_TIMER0) + TIMER_CTRL);
  75         writel(0, MMIO_P2V(CT_CA9X4_TIMER1) + TIMER_CTRL);
  76
  77         sp804_clocksource_init(MMIO_P2V(CT_CA9X4_TIMER1));
  78         sp804_clockevents_init(MMIO_P2V(CT_CA9X4_TIMER0), IRQ_CT_CA9X4_TIMER0);
  79 }
  80
  81 static struct sys_timer ct_ca9x4_timer = {
  82         .init   = ct_ca9x4_timer_init,
  83 };
  84 #endif
  85
  86 static struct clcd_panel xvga_panel = {
  87         .mode           = {
  88                 .name           = "XVGA",
  89                 .refresh        = 60,
  90                 .xres           = 1024,
  91                 .yres           = 768,
  92                 .pixclock       = 15384,
  93                 .left_margin    = 168,
  94                 .right_margin   = 8,
  95                 .upper_margin   = 29,
  96                 .lower_margin   = 3,
  97                 .hsync_len      = 144,
  98                 .vsync_len      = 6,
  99                 .sync           = 0,
 100                 .vmode          = FB_VMODE_NONINTERLACED,
 101         },
 102         .width          = -1,
 103         .height         = -1,
 104         .tim2           = TIM2_BCD | TIM2_IPC,
 105         .cntl           = CNTL_LCDTFT | CNTL_BGR | CNTL_LCDVCOMP(1),
 106         .bpp            = 16,
 107 };
 108
 109 static void ct_ca9x4_clcd_enable(struct clcd_fb *fb)
 110 {
 111         v2m_cfg_write(SYS_CFG_MUXFPGA | SYS_CFG_SITE_DB1, 0);
 112         v2m_cfg_write(SYS_CFG_DVIMODE | SYS_CFG_SITE_DB1, 2);
 113 }
 114
 115 static int ct_ca9x4_clcd_setup(struct clcd_fb *fb)
 116 {
 117         unsigned long framesize = 1024 * 768 * 2;
 118         dma_addr_t dma;
 119
 120         fb->panel = &xvga_panel;
 121
 122         fb->fb.screen_base = dma_alloc_writecombine(&fb->dev->dev, framesize,
 123                                 &dma, GFP_KERNEL);
 124         if (!fb->fb.screen_base) {
 125                 printk(KERN_ERR "CLCD: unable to map frame buffer\n");
 126                 return -ENOMEM;
 127         }
 128         fb->fb.fix.smem_start = dma;
 129         fb->fb.fix.smem_len = framesize;
 130
 131         return 0;
 132 }
 133
 134 static int ct_ca9x4_clcd_mmap(struct clcd_fb *fb, struct vm_area_struct *vma)
 135 {
 136         return dma_mmap_writecombine(&fb->dev->dev, vma, fb->fb.screen_base,
 137                 fb->fb.fix.smem_start, fb->fb.fix.smem_len);
 138 }
 139
 140 static void ct_ca9x4_clcd_remove(struct clcd_fb *fb)
 141 {
 142         dma_free_writecombine(&fb->dev->dev, fb->fb.fix.smem_len,
 143                 fb->fb.screen_base, fb->fb.fix.smem_start);
 144 }
 145
 146 static struct clcd_board ct_ca9x4_clcd_data = {
 147         .name           = "CT-CA9X4",
 148         .check          = clcdfb_check,
 149         .decode         = clcdfb_decode,
 150         .enable         = ct_ca9x4_clcd_enable,
 151         .setup          = ct_ca9x4_clcd_setup,
 152         .mmap           = ct_ca9x4_clcd_mmap,
 153         .remove         = ct_ca9x4_clcd_remove,
 154 };
 155
 156 static AMBA_DEVICE(clcd, "ct:clcd", CT_CA9X4_CLCDC, &ct_ca9x4_clcd_data);
 157 static AMBA_DEVICE(dmc, "ct:dmc", CT_CA9X4_DMC, NULL);
 158 static AMBA_DEVICE(smc, "ct:smc", CT_CA9X4_SMC, NULL);
 159 static AMBA_DEVICE(gpio, "ct:gpio", CT_CA9X4_GPIO, NULL);
 160
 161 static struct amba_device *ct_ca9x4_amba_devs[] __initdata = {
 162         &clcd_device,
 163         &dmc_device,
 164         &smc_device,
 165         &gpio_device,
 166 };
 167
 168
 169 static long ct_round(struct clk *clk, unsigned long rate)
 170 {
 171         return rate;
 172 }
 173
 174 static int ct_set(struct clk *clk, unsigned long rate)
 175 {
 176         return v2m_cfg_write(SYS_CFG_OSC | SYS_CFG_SITE_DB1 | 1, rate);
 177 }
 178
 179 static const struct clk_ops osc1_clk_ops = {
 180         .round  = ct_round,
 181         .set    = ct_set,
 182 };
 183
 184 static struct clk osc1_clk = {
 185         .ops    = &osc1_clk_ops,
 186         .rate   = 24000000,
 187 };
 188
 189 static struct clk_lookup lookups[] = {
 190         {       /* CLCD */
 191                 .dev_id         = "ct:clcd",
 192                 .clk            = &osc1_clk,
 193         },
 194 };
 195
 196 static struct resource pmu_resources[] = {
 197         [0] = {
 198                 .start  = IRQ_CT_CA9X4_PMU_CPU0,
 199                 .end    = IRQ_CT_CA9X4_PMU_CPU0,
 200                 .flags  = IORESOURCE_IRQ,
 201         },
 202         [1] = {
 203                 .start  = IRQ_CT_CA9X4_PMU_CPU1,
 204                 .end    = IRQ_CT_CA9X4_PMU_CPU1,
 205                 .flags  = IORESOURCE_IRQ,
 206         },
 207         [2] = {
 208                 .start  = IRQ_CT_CA9X4_PMU_CPU2,
 209                 .end    = IRQ_CT_CA9X4_PMU_CPU2,
 210                 .flags  = IORESOURCE_IRQ,
 211         },
 212         [3] = {
 213                 .start  = IRQ_CT_CA9X4_PMU_CPU3,
 214                 .end    = IRQ_CT_CA9X4_PMU_CPU3,
 215                 .flags  = IORESOURCE_IRQ,
 216         },
 217 };
 218
 219 static struct platform_device pmu_device = {
 220         .name           = "arm-pmu",
 221         .id             = ARM_PMU_DEVICE_CPU,
 222         .num_resources  = ARRAY_SIZE(pmu_resources),
 223         .resource       = pmu_resources,
 224 };
 225
 226 static void __init ct_ca9x4_init(void)
 227 {
 228         int i;
 229
 230 #ifdef CONFIG_CACHE_L2X0
 231         void __iomem *l2x0_base = MMIO_P2V(CT_CA9X4_L2CC);
 232
 233         /* set RAM latencies to 1 cycle for this core tile. */
 234         writel(0, l2x0_base + L2X0_TAG_LATENCY_CTRL);
 235         writel(0, l2x0_base + L2X0_DATA_LATENCY_CTRL);
 236
 237         l2x0_init(l2x0_base, 0x00400000, 0xfe0fffff);
 238 #endif
 239
 240         clkdev_add_table(lookups, ARRAY_SIZE(lookups));
 241
 242         for (i = 0; i < ARRAY_SIZE(ct_ca9x4_amba_devs); i++)
 243                 amba_device_register(ct_ca9x4_amba_devs[i], &iomem_resource);
 244
 245         platform_device_register(&pmu_device);
 246 }
 247
 248 MACHINE_START(VEXPRESS, "ARM-Versatile Express CA9x4")
 249         .boot_params    = PHYS_OFFSET + 0x00000100,
 250         .map_io         = ct_ca9x4_map_io,
 251         .init_irq       = ct_ca9x4_init_irq,
 252 #if 0
 253         .timer          = &ct_ca9x4_timer,
 254 #else
 255         .timer          = &v2m_timer,
 256 #endif
 257         .init_machine   = ct_ca9x4_init,
 258 MACHINE_END