2 * linux/arch/arm/mach-versatile/core.c
4 * Copyright (C) 1999 - 2003 ARM Limited
5 * Copyright (C) 2000 Deep Blue Solutions Ltd
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 #include <linux/init.h>
22 #include <linux/device.h>
23 #include <linux/dma-mapping.h>
24 #include <linux/platform_device.h>
25 #include <linux/sysdev.h>
26 #include <linux/interrupt.h>
27 #include <linux/amba/bus.h>
28 #include <linux/amba/clcd.h>
29 #include <linux/amba/pl061.h>
30 #include <linux/amba/mmci.h>
31 #include <linux/amba/pl022.h>
33 #include <linux/gfp.h>
34 #include <linux/clkdev.h>
36 #include <asm/system.h>
39 #include <asm/hardware/arm_timer.h>
40 #include <asm/hardware/icst.h>
41 #include <asm/hardware/vic.h>
42 #include <asm/mach-types.h>
44 #include <asm/mach/arch.h>
45 #include <asm/mach/flash.h>
46 #include <asm/mach/irq.h>
47 #include <asm/mach/time.h>
48 #include <asm/mach/map.h>
49 #include <mach/hardware.h>
50 #include <mach/platform.h>
51 #include <asm/hardware/timer-sp.h>
53 #include <plat/sched_clock.h>
58 * All IO addresses are mapped onto VA 0xFFFx.xxxx, where x.xxxx
61 * Setup a VA for the Versatile Vectored Interrupt Controller.
63 #define VA_VIC_BASE __io_address(VERSATILE_VIC_BASE)
64 #define VA_SIC_BASE __io_address(VERSATILE_SIC_BASE)
66 static void sic_mask_irq(unsigned int irq)
69 writel(1 << irq, VA_SIC_BASE + SIC_IRQ_ENABLE_CLEAR);
72 static void sic_unmask_irq(unsigned int irq)
75 writel(1 << irq, VA_SIC_BASE + SIC_IRQ_ENABLE_SET);
78 static struct irq_chip sic_chip = {
82 .unmask = sic_unmask_irq,
86 sic_handle_irq(unsigned int irq, struct irq_desc *desc)
88 unsigned long status = readl(VA_SIC_BASE + SIC_IRQ_STATUS);
91 do_bad_IRQ(irq, desc);
96 irq = ffs(status) - 1;
97 status &= ~(1 << irq);
101 generic_handle_irq(irq);
106 #define IRQ_MMCI0A IRQ_VICSOURCE22
107 #define IRQ_AACI IRQ_VICSOURCE24
108 #define IRQ_ETH IRQ_VICSOURCE25
109 #define PIC_MASK 0xFFD00000
111 #define IRQ_MMCI0A IRQ_SIC_MMCI0A
112 #define IRQ_AACI IRQ_SIC_AACI
113 #define IRQ_ETH IRQ_SIC_ETH
117 void __init versatile_init_irq(void)
121 vic_init(VA_VIC_BASE, IRQ_VIC_START, ~0, 0);
123 set_irq_chained_handler(IRQ_VICSOURCE31, sic_handle_irq);
125 /* Do second interrupt controller */
126 writel(~0, VA_SIC_BASE + SIC_IRQ_ENABLE_CLEAR);
128 for (i = IRQ_SIC_START; i <= IRQ_SIC_END; i++) {
129 if ((PIC_MASK & (1 << (i - IRQ_SIC_START))) == 0) {
130 set_irq_chip(i, &sic_chip);
131 set_irq_handler(i, handle_level_irq);
132 set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
137 * Interrupts on secondary controller from 0 to 8 are routed to
139 * Interrupts from 21 to 31 are routed directly to the VIC on
140 * the corresponding number on primary controller. This is controlled
141 * by setting PIC_ENABLEx.
143 writel(PIC_MASK, VA_SIC_BASE + SIC_INT_PIC_ENABLE);
146 static struct map_desc versatile_io_desc[] __initdata = {
148 .virtual = IO_ADDRESS(VERSATILE_SYS_BASE),
149 .pfn = __phys_to_pfn(VERSATILE_SYS_BASE),
153 .virtual = IO_ADDRESS(VERSATILE_SIC_BASE),
154 .pfn = __phys_to_pfn(VERSATILE_SIC_BASE),
158 .virtual = IO_ADDRESS(VERSATILE_VIC_BASE),
159 .pfn = __phys_to_pfn(VERSATILE_VIC_BASE),
163 .virtual = IO_ADDRESS(VERSATILE_SCTL_BASE),
164 .pfn = __phys_to_pfn(VERSATILE_SCTL_BASE),
168 #ifdef CONFIG_MACH_VERSATILE_AB
170 .virtual = IO_ADDRESS(VERSATILE_GPIO0_BASE),
171 .pfn = __phys_to_pfn(VERSATILE_GPIO0_BASE),
175 .virtual = IO_ADDRESS(VERSATILE_IB2_BASE),
176 .pfn = __phys_to_pfn(VERSATILE_IB2_BASE),
181 #ifdef CONFIG_DEBUG_LL
183 .virtual = IO_ADDRESS(VERSATILE_UART0_BASE),
184 .pfn = __phys_to_pfn(VERSATILE_UART0_BASE),
191 .virtual = IO_ADDRESS(VERSATILE_PCI_CORE_BASE),
192 .pfn = __phys_to_pfn(VERSATILE_PCI_CORE_BASE),
196 .virtual = (unsigned long)VERSATILE_PCI_VIRT_BASE,
197 .pfn = __phys_to_pfn(VERSATILE_PCI_BASE),
198 .length = VERSATILE_PCI_BASE_SIZE,
201 .virtual = (unsigned long)VERSATILE_PCI_CFG_VIRT_BASE,
202 .pfn = __phys_to_pfn(VERSATILE_PCI_CFG_BASE),
203 .length = VERSATILE_PCI_CFG_BASE_SIZE,
208 .virtual = VERSATILE_PCI_VIRT_MEM_BASE0,
209 .pfn = __phys_to_pfn(VERSATILE_PCI_MEM_BASE0),
213 .virtual = VERSATILE_PCI_VIRT_MEM_BASE1,
214 .pfn = __phys_to_pfn(VERSATILE_PCI_MEM_BASE1),
218 .virtual = VERSATILE_PCI_VIRT_MEM_BASE2,
219 .pfn = __phys_to_pfn(VERSATILE_PCI_MEM_BASE2),
227 void __init versatile_map_io(void)
229 iotable_init(versatile_io_desc, ARRAY_SIZE(versatile_io_desc));
233 #define VERSATILE_FLASHCTRL (__io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_FLASH_OFFSET)
235 static int versatile_flash_init(void)
239 val = __raw_readl(VERSATILE_FLASHCTRL);
240 val &= ~VERSATILE_FLASHPROG_FLVPPEN;
241 __raw_writel(val, VERSATILE_FLASHCTRL);
246 static void versatile_flash_exit(void)
250 val = __raw_readl(VERSATILE_FLASHCTRL);
251 val &= ~VERSATILE_FLASHPROG_FLVPPEN;
252 __raw_writel(val, VERSATILE_FLASHCTRL);
255 static void versatile_flash_set_vpp(int on)
259 val = __raw_readl(VERSATILE_FLASHCTRL);
261 val |= VERSATILE_FLASHPROG_FLVPPEN;
263 val &= ~VERSATILE_FLASHPROG_FLVPPEN;
264 __raw_writel(val, VERSATILE_FLASHCTRL);
267 static struct flash_platform_data versatile_flash_data = {
268 .map_name = "cfi_probe",
270 .init = versatile_flash_init,
271 .exit = versatile_flash_exit,
272 .set_vpp = versatile_flash_set_vpp,
275 static struct resource versatile_flash_resource = {
276 .start = VERSATILE_FLASH_BASE,
277 .end = VERSATILE_FLASH_BASE + VERSATILE_FLASH_SIZE - 1,
278 .flags = IORESOURCE_MEM,
281 static struct platform_device versatile_flash_device = {
285 .platform_data = &versatile_flash_data,
288 .resource = &versatile_flash_resource,
291 static struct resource smc91x_resources[] = {
293 .start = VERSATILE_ETH_BASE,
294 .end = VERSATILE_ETH_BASE + SZ_64K - 1,
295 .flags = IORESOURCE_MEM,
300 .flags = IORESOURCE_IRQ,
304 static struct platform_device smc91x_device = {
307 .num_resources = ARRAY_SIZE(smc91x_resources),
308 .resource = smc91x_resources,
311 static struct resource versatile_i2c_resource = {
312 .start = VERSATILE_I2C_BASE,
313 .end = VERSATILE_I2C_BASE + SZ_4K - 1,
314 .flags = IORESOURCE_MEM,
317 static struct platform_device versatile_i2c_device = {
318 .name = "versatile-i2c",
321 .resource = &versatile_i2c_resource,
324 static struct i2c_board_info versatile_i2c_board_info[] = {
326 I2C_BOARD_INFO("ds1338", 0xd0 >> 1),
330 static int __init versatile_i2c_init(void)
332 return i2c_register_board_info(0, versatile_i2c_board_info,
333 ARRAY_SIZE(versatile_i2c_board_info));
335 arch_initcall(versatile_i2c_init);
337 #define VERSATILE_SYSMCI (__io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_MCI_OFFSET)
339 unsigned int mmc_status(struct device *dev)
341 struct amba_device *adev = container_of(dev, struct amba_device, dev);
344 if (adev->res.start == VERSATILE_MMCI0_BASE)
349 return readl(VERSATILE_SYSMCI) & mask;
352 static struct mmci_platform_data mmc0_plat_data = {
353 .ocr_mask = MMC_VDD_32_33|MMC_VDD_33_34,
354 .status = mmc_status,
359 static struct resource char_lcd_resources[] = {
361 .start = VERSATILE_CHAR_LCD_BASE,
362 .end = (VERSATILE_CHAR_LCD_BASE + SZ_4K - 1),
363 .flags = IORESOURCE_MEM,
367 static struct platform_device char_lcd_device = {
368 .name = "arm-charlcd",
370 .num_resources = ARRAY_SIZE(char_lcd_resources),
371 .resource = char_lcd_resources,
377 static const struct icst_params versatile_oscvco_params = {
379 .vco_max = ICST307_VCO_MAX,
380 .vco_min = ICST307_VCO_MIN,
385 .s2div = icst307_s2div,
386 .idx2s = icst307_idx2s,
389 static void versatile_oscvco_set(struct clk *clk, struct icst_vco vco)
391 void __iomem *sys_lock = __io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_LOCK_OFFSET;
394 val = readl(clk->vcoreg) & ~0x7ffff;
395 val |= vco.v | (vco.r << 9) | (vco.s << 16);
397 writel(0xa05f, sys_lock);
398 writel(val, clk->vcoreg);
402 static const struct clk_ops osc4_clk_ops = {
403 .round = icst_clk_round,
405 .setvco = versatile_oscvco_set,
408 static struct clk osc4_clk = {
409 .ops = &osc4_clk_ops,
410 .params = &versatile_oscvco_params,
414 * These are fixed clocks.
416 static struct clk ref24_clk = {
420 static struct clk dummy_apb_pclk;
422 static struct clk_lookup lookups[] = {
423 { /* AMBA bus clock */
424 .con_id = "apb_pclk",
425 .clk = &dummy_apb_pclk,
462 #define SYS_CLCD_MODE_MASK (3 << 0)
463 #define SYS_CLCD_MODE_888 (0 << 0)
464 #define SYS_CLCD_MODE_5551 (1 << 0)
465 #define SYS_CLCD_MODE_565_RLSB (2 << 0)
466 #define SYS_CLCD_MODE_565_BLSB (3 << 0)
467 #define SYS_CLCD_NLCDIOON (1 << 2)
468 #define SYS_CLCD_VDDPOSSWITCH (1 << 3)
469 #define SYS_CLCD_PWR3V5SWITCH (1 << 4)
470 #define SYS_CLCD_ID_MASK (0x1f << 8)
471 #define SYS_CLCD_ID_SANYO_3_8 (0x00 << 8)
472 #define SYS_CLCD_ID_UNKNOWN_8_4 (0x01 << 8)
473 #define SYS_CLCD_ID_EPSON_2_2 (0x02 << 8)
474 #define SYS_CLCD_ID_SANYO_2_5 (0x07 << 8)
475 #define SYS_CLCD_ID_VGA (0x1f << 8)
477 static struct clcd_panel vga = {
491 .vmode = FB_VMODE_NONINTERLACED,
495 .tim2 = TIM2_BCD | TIM2_IPC,
496 .cntl = CNTL_LCDTFT | CNTL_LCDVCOMP(1),
500 static struct clcd_panel sanyo_3_8_in = {
502 .name = "Sanyo QVGA",
514 .vmode = FB_VMODE_NONINTERLACED,
519 .cntl = CNTL_LCDTFT | CNTL_LCDVCOMP(1),
523 static struct clcd_panel sanyo_2_5_in = {
525 .name = "Sanyo QVGA Portrait",
536 .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
537 .vmode = FB_VMODE_NONINTERLACED,
541 .tim2 = TIM2_IVS | TIM2_IHS | TIM2_IPC,
542 .cntl = CNTL_LCDTFT | CNTL_LCDVCOMP(1),
546 static struct clcd_panel epson_2_2_in = {
548 .name = "Epson QCIF",
560 .vmode = FB_VMODE_NONINTERLACED,
564 .tim2 = TIM2_BCD | TIM2_IPC,
565 .cntl = CNTL_LCDTFT | CNTL_LCDVCOMP(1),
570 * Detect which LCD panel is connected, and return the appropriate
571 * clcd_panel structure. Note: we do not have any information on
572 * the required timings for the 8.4in panel, so we presently assume
575 static struct clcd_panel *versatile_clcd_panel(void)
577 void __iomem *sys_clcd = __io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_CLCD_OFFSET;
578 struct clcd_panel *panel = &vga;
581 val = readl(sys_clcd) & SYS_CLCD_ID_MASK;
582 if (val == SYS_CLCD_ID_SANYO_3_8)
583 panel = &sanyo_3_8_in;
584 else if (val == SYS_CLCD_ID_SANYO_2_5)
585 panel = &sanyo_2_5_in;
586 else if (val == SYS_CLCD_ID_EPSON_2_2)
587 panel = &epson_2_2_in;
588 else if (val == SYS_CLCD_ID_VGA)
591 printk(KERN_ERR "CLCD: unknown LCD panel ID 0x%08x, using VGA\n",
600 * Disable all display connectors on the interface module.
602 static void versatile_clcd_disable(struct clcd_fb *fb)
604 void __iomem *sys_clcd = __io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_CLCD_OFFSET;
607 val = readl(sys_clcd);
608 val &= ~SYS_CLCD_NLCDIOON | SYS_CLCD_PWR3V5SWITCH;
609 writel(val, sys_clcd);
611 #ifdef CONFIG_MACH_VERSATILE_AB
613 * If the LCD is Sanyo 2x5 in on the IB2 board, turn the back-light off
615 if (machine_is_versatile_ab() && fb->panel == &sanyo_2_5_in) {
616 void __iomem *versatile_ib2_ctrl = __io_address(VERSATILE_IB2_CTRL);
619 ctrl = readl(versatile_ib2_ctrl);
621 writel(ctrl, versatile_ib2_ctrl);
627 * Enable the relevant connector on the interface module.
629 static void versatile_clcd_enable(struct clcd_fb *fb)
631 void __iomem *sys_clcd = __io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_CLCD_OFFSET;
634 val = readl(sys_clcd);
635 val &= ~SYS_CLCD_MODE_MASK;
637 switch (fb->fb.var.green.length) {
639 val |= SYS_CLCD_MODE_5551;
642 val |= SYS_CLCD_MODE_565_RLSB;
645 val |= SYS_CLCD_MODE_888;
652 writel(val, sys_clcd);
655 * And now enable the PSUs
657 val |= SYS_CLCD_NLCDIOON | SYS_CLCD_PWR3V5SWITCH;
658 writel(val, sys_clcd);
660 #ifdef CONFIG_MACH_VERSATILE_AB
662 * If the LCD is Sanyo 2x5 in on the IB2 board, turn the back-light on
664 if (machine_is_versatile_ab() && fb->panel == &sanyo_2_5_in) {
665 void __iomem *versatile_ib2_ctrl = __io_address(VERSATILE_IB2_CTRL);
668 ctrl = readl(versatile_ib2_ctrl);
670 writel(ctrl, versatile_ib2_ctrl);
675 static unsigned long framesize = SZ_1M;
677 static int versatile_clcd_setup(struct clcd_fb *fb)
681 fb->panel = versatile_clcd_panel();
683 fb->fb.screen_base = dma_alloc_writecombine(&fb->dev->dev, framesize,
685 if (!fb->fb.screen_base) {
686 printk(KERN_ERR "CLCD: unable to map framebuffer\n");
690 fb->fb.fix.smem_start = dma;
691 fb->fb.fix.smem_len = framesize;
696 static int versatile_clcd_mmap(struct clcd_fb *fb, struct vm_area_struct *vma)
698 return dma_mmap_writecombine(&fb->dev->dev, vma,
700 fb->fb.fix.smem_start,
701 fb->fb.fix.smem_len);
704 static void versatile_clcd_remove(struct clcd_fb *fb)
706 dma_free_writecombine(&fb->dev->dev, fb->fb.fix.smem_len,
707 fb->fb.screen_base, fb->fb.fix.smem_start);
710 static struct clcd_board clcd_plat_data = {
712 .check = clcdfb_check,
713 .decode = clcdfb_decode,
714 .disable = versatile_clcd_disable,
715 .enable = versatile_clcd_enable,
716 .setup = versatile_clcd_setup,
717 .mmap = versatile_clcd_mmap,
718 .remove = versatile_clcd_remove,
721 static struct pl061_platform_data gpio0_plat_data = {
723 .irq_base = IRQ_GPIO0_START,
726 static struct pl061_platform_data gpio1_plat_data = {
728 .irq_base = IRQ_GPIO1_START,
731 static struct pl022_ssp_controller ssp0_plat_data = {
737 #define AACI_IRQ { IRQ_AACI, NO_IRQ }
738 #define AACI_DMA { 0x80, 0x81 }
739 #define MMCI0_IRQ { IRQ_MMCI0A,IRQ_SIC_MMCI0B }
740 #define MMCI0_DMA { 0x84, 0 }
741 #define KMI0_IRQ { IRQ_SIC_KMI0, NO_IRQ }
742 #define KMI0_DMA { 0, 0 }
743 #define KMI1_IRQ { IRQ_SIC_KMI1, NO_IRQ }
744 #define KMI1_DMA { 0, 0 }
747 * These devices are connected directly to the multi-layer AHB switch
749 #define SMC_IRQ { NO_IRQ, NO_IRQ }
750 #define SMC_DMA { 0, 0 }
751 #define MPMC_IRQ { NO_IRQ, NO_IRQ }
752 #define MPMC_DMA { 0, 0 }
753 #define CLCD_IRQ { IRQ_CLCDINT, NO_IRQ }
754 #define CLCD_DMA { 0, 0 }
755 #define DMAC_IRQ { IRQ_DMAINT, NO_IRQ }
756 #define DMAC_DMA { 0, 0 }
759 * These devices are connected via the core APB bridge
761 #define SCTL_IRQ { NO_IRQ, NO_IRQ }
762 #define SCTL_DMA { 0, 0 }
763 #define WATCHDOG_IRQ { IRQ_WDOGINT, NO_IRQ }
764 #define WATCHDOG_DMA { 0, 0 }
765 #define GPIO0_IRQ { IRQ_GPIOINT0, NO_IRQ }
766 #define GPIO0_DMA { 0, 0 }
767 #define GPIO1_IRQ { IRQ_GPIOINT1, NO_IRQ }
768 #define GPIO1_DMA { 0, 0 }
769 #define RTC_IRQ { IRQ_RTCINT, NO_IRQ }
770 #define RTC_DMA { 0, 0 }
773 * These devices are connected via the DMA APB bridge
775 #define SCI_IRQ { IRQ_SCIINT, NO_IRQ }
776 #define SCI_DMA { 7, 6 }
777 #define UART0_IRQ { IRQ_UARTINT0, NO_IRQ }
778 #define UART0_DMA { 15, 14 }
779 #define UART1_IRQ { IRQ_UARTINT1, NO_IRQ }
780 #define UART1_DMA { 13, 12 }
781 #define UART2_IRQ { IRQ_UARTINT2, NO_IRQ }
782 #define UART2_DMA { 11, 10 }
783 #define SSP_IRQ { IRQ_SSPINT, NO_IRQ }
784 #define SSP_DMA { 9, 8 }
786 /* FPGA Primecells */
787 AMBA_DEVICE(aaci, "fpga:04", AACI, NULL);
788 AMBA_DEVICE(mmc0, "fpga:05", MMCI0, &mmc0_plat_data);
789 AMBA_DEVICE(kmi0, "fpga:06", KMI0, NULL);
790 AMBA_DEVICE(kmi1, "fpga:07", KMI1, NULL);
792 /* DevChip Primecells */
793 AMBA_DEVICE(smc, "dev:00", SMC, NULL);
794 AMBA_DEVICE(mpmc, "dev:10", MPMC, NULL);
795 AMBA_DEVICE(clcd, "dev:20", CLCD, &clcd_plat_data);
796 AMBA_DEVICE(dmac, "dev:30", DMAC, NULL);
797 AMBA_DEVICE(sctl, "dev:e0", SCTL, NULL);
798 AMBA_DEVICE(wdog, "dev:e1", WATCHDOG, NULL);
799 AMBA_DEVICE(gpio0, "dev:e4", GPIO0, &gpio0_plat_data);
800 AMBA_DEVICE(gpio1, "dev:e5", GPIO1, &gpio1_plat_data);
801 AMBA_DEVICE(rtc, "dev:e8", RTC, NULL);
802 AMBA_DEVICE(sci0, "dev:f0", SCI, NULL);
803 AMBA_DEVICE(uart0, "dev:f1", UART0, NULL);
804 AMBA_DEVICE(uart1, "dev:f2", UART1, NULL);
805 AMBA_DEVICE(uart2, "dev:f3", UART2, NULL);
806 AMBA_DEVICE(ssp0, "dev:f4", SSP, &ssp0_plat_data);
808 static struct amba_device *amba_devs[] __initdata = {
830 #define VA_LEDS_BASE (__io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_LED_OFFSET)
832 static void versatile_leds_event(led_event_t ledevt)
837 local_irq_save(flags);
838 val = readl(VA_LEDS_BASE);
842 val = val & ~VERSATILE_SYS_LED0;
846 val = val | VERSATILE_SYS_LED0;
850 val = val ^ VERSATILE_SYS_LED1;
861 writel(val, VA_LEDS_BASE);
862 local_irq_restore(flags);
864 #endif /* CONFIG_LEDS */
866 void __init versatile_init(void)
870 osc4_clk.vcoreg = __io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_OSCCLCD_OFFSET;
872 clkdev_add_table(lookups, ARRAY_SIZE(lookups));
874 platform_device_register(&versatile_flash_device);
875 platform_device_register(&versatile_i2c_device);
876 platform_device_register(&smc91x_device);
877 platform_device_register(&char_lcd_device);
879 for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
880 struct amba_device *d = amba_devs[i];
881 amba_device_register(d, &iomem_resource);
885 leds_event = versatile_leds_event;
890 * The sched_clock counter
892 #define REFCOUNTER (__io_address(VERSATILE_SYS_BASE) + \
893 VERSATILE_SYS_24MHz_OFFSET)
896 * Where is the timer (VA)?
898 #define TIMER0_VA_BASE __io_address(VERSATILE_TIMER0_1_BASE)
899 #define TIMER1_VA_BASE (__io_address(VERSATILE_TIMER0_1_BASE) + 0x20)
900 #define TIMER2_VA_BASE __io_address(VERSATILE_TIMER2_3_BASE)
901 #define TIMER3_VA_BASE (__io_address(VERSATILE_TIMER2_3_BASE) + 0x20)
904 * Set up timer interrupt, and return the current time in seconds.
906 static void __init versatile_timer_init(void)
910 versatile_sched_clock_init(REFCOUNTER, 24000000);
913 * set clock frequency:
914 * VERSATILE_REFCLK is 32KHz
915 * VERSATILE_TIMCLK is 1MHz
917 val = readl(__io_address(VERSATILE_SCTL_BASE));
918 writel((VERSATILE_TIMCLK << VERSATILE_TIMER1_EnSel) |
919 (VERSATILE_TIMCLK << VERSATILE_TIMER2_EnSel) |
920 (VERSATILE_TIMCLK << VERSATILE_TIMER3_EnSel) |
921 (VERSATILE_TIMCLK << VERSATILE_TIMER4_EnSel) | val,
922 __io_address(VERSATILE_SCTL_BASE));
925 * Initialise to a known state (all timers off)
927 writel(0, TIMER0_VA_BASE + TIMER_CTRL);
928 writel(0, TIMER1_VA_BASE + TIMER_CTRL);
929 writel(0, TIMER2_VA_BASE + TIMER_CTRL);
930 writel(0, TIMER3_VA_BASE + TIMER_CTRL);
932 sp804_clocksource_init(TIMER3_VA_BASE);
933 sp804_clockevents_init(TIMER0_VA_BASE, IRQ_TIMERINT0_1);
936 struct sys_timer versatile_timer = {
937 .init = versatile_timer_init,