arch/arm/mach-u300/core.c

   1 /*
   2  *
   3  * arch/arm/mach-u300/core.c
   4  *
   5  *
   6  * Copyright (C) 2007-2012 ST-Ericsson SA
   7  * License terms: GNU General Public License (GPL) version 2
   8  * Core platform support, IRQ handling and device definitions.
   9  * Author: Linus Walleij <linus.walleij@stericsson.com>
  10  */
  11 #include <linux/kernel.h>
  12 #include <linux/init.h>
  13 #include <linux/spinlock.h>
  14 #include <linux/interrupt.h>
  15 #include <linux/bitops.h>
  16 #include <linux/device.h>
  17 #include <linux/mm.h>
  18 #include <linux/termios.h>
  19 #include <linux/dmaengine.h>
  20 #include <linux/amba/bus.h>
  21 #include <linux/amba/mmci.h>
  22 #include <linux/amba/serial.h>
  23 #include <linux/platform_device.h>
  24 #include <linux/gpio.h>
  25 #include <linux/clk.h>
  26 #include <linux/err.h>
  27 #include <linux/mtd/nand.h>
  28 #include <linux/mtd/fsmc.h>
  29 #include <linux/pinctrl/machine.h>
  30 #include <linux/pinctrl/pinconf-generic.h>
  31 #include <linux/dma-mapping.h>
  32 #include <linux/platform_data/clk-u300.h>
  33 #include <linux/platform_data/pinctrl-coh901.h>
  34 #include <linux/irqchip/arm-vic.h>
  35
  36 #include <asm/types.h>
  37 #include <asm/setup.h>
  38 #include <asm/memory.h>
  39 #include <asm/mach/map.h>
  40 #include <asm/mach-types.h>
  41 #include <asm/mach/arch.h>
  42
  43 #include <mach/coh901318.h>
  44 #include <mach/hardware.h>
  45 #include <mach/syscon.h>
  46 #include <mach/irqs.h>
  47
  48 #include "timer.h"
  49 #include "spi.h"
  50 #include "i2c.h"
  51 #include "u300-gpio.h"
  52 #include "dma_channels.h"
  53
  54 /*
  55  * Static I/O mappings that are needed for booting the U300 platforms. The
  56  * only things we need are the areas where we find the timer, syscon and
  57  * intcon, since the remaining device drivers will map their own memory
  58  * physical to virtual as the need arise.
  59  */
  60 static struct map_desc u300_io_desc[] __initdata = {
  61         {
  62                 .virtual        = U300_SLOW_PER_VIRT_BASE,
  63                 .pfn            = __phys_to_pfn(U300_SLOW_PER_PHYS_BASE),
  64                 .length         = SZ_64K,
  65                 .type           = MT_DEVICE,
  66         },
  67         {
  68                 .virtual        = U300_AHB_PER_VIRT_BASE,
  69                 .pfn            = __phys_to_pfn(U300_AHB_PER_PHYS_BASE),
  70                 .length         = SZ_32K,
  71                 .type           = MT_DEVICE,
  72         },
  73         {
  74                 .virtual        = U300_FAST_PER_VIRT_BASE,
  75                 .pfn            = __phys_to_pfn(U300_FAST_PER_PHYS_BASE),
  76                 .length         = SZ_32K,
  77                 .type           = MT_DEVICE,
  78         },
  79 };
  80
  81 static void __init u300_map_io(void)
  82 {
  83         iotable_init(u300_io_desc, ARRAY_SIZE(u300_io_desc));
  84 }
  85
  86 /*
  87  * Declaration of devices found on the U300 board and
  88  * their respective memory locations.
  89  */
  90
  91 static struct amba_pl011_data uart0_plat_data = {
  92 #ifdef CONFIG_COH901318
  93         .dma_filter = coh901318_filter_id,
  94         .dma_rx_param = (void *) U300_DMA_UART0_RX,
  95         .dma_tx_param = (void *) U300_DMA_UART0_TX,
  96 #endif
  97 };
  98
  99 /* Slow device at 0x3000 offset */
 100 static AMBA_APB_DEVICE(uart0, "uart0", 0, U300_UART0_BASE,
 101         { IRQ_U300_UART0 }, &uart0_plat_data);
 102
 103 /* The U335 have an additional UART1 on the APP CPU */
 104 static struct amba_pl011_data uart1_plat_data = {
 105 #ifdef CONFIG_COH901318
 106         .dma_filter = coh901318_filter_id,
 107         .dma_rx_param = (void *) U300_DMA_UART1_RX,
 108         .dma_tx_param = (void *) U300_DMA_UART1_TX,
 109 #endif
 110 };
 111
 112 /* Fast device at 0x7000 offset */
 113 static AMBA_APB_DEVICE(uart1, "uart1", 0, U300_UART1_BASE,
 114         { IRQ_U300_UART1 }, &uart1_plat_data);
 115
 116 /* AHB device at 0x4000 offset */
 117 static AMBA_APB_DEVICE(pl172, "pl172", 0, U300_EMIF_CFG_BASE, { }, NULL);
 118
 119 /* Fast device at 0x6000 offset */
 120 static AMBA_APB_DEVICE(pl022, "pl022", 0, U300_SPI_BASE,
 121         { IRQ_U300_SPI }, NULL);
 122
 123 /* Fast device at 0x1000 offset */
 124 #define U300_MMCSD_IRQS { IRQ_U300_MMCSD_MCIINTR0, IRQ_U300_MMCSD_MCIINTR1 }
 125
 126 static struct mmci_platform_data mmcsd_platform_data = {
 127         /*
 128          * Do not set ocr_mask or voltage translation function,
 129          * we have a regulator we can control instead.
 130          */
 131         .f_max = 24000000,
 132         .gpio_wp = -1,
 133         .gpio_cd = U300_GPIO_PIN_MMC_CD,
 134         .cd_invert = true,
 135         .capabilities = MMC_CAP_MMC_HIGHSPEED |
 136         MMC_CAP_SD_HIGHSPEED | MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA,
 137 #ifdef CONFIG_COH901318
 138         .dma_filter = coh901318_filter_id,
 139         .dma_rx_param = (void *) U300_DMA_MMCSD_RX_TX,
 140         /* Don't specify a TX channel, this RX channel is bidirectional */
 141 #endif
 142 };
 143
 144 static AMBA_APB_DEVICE(mmcsd, "mmci", 0, U300_MMCSD_BASE,
 145         U300_MMCSD_IRQS, &mmcsd_platform_data);
 146
 147 /*
 148  * The order of device declaration may be important, since some devices
 149  * have dependencies on other devices being initialized first.
 150  */
 151 static struct amba_device *amba_devs[] __initdata = {
 152         &uart0_device,
 153         &uart1_device,
 154         &pl022_device,
 155         &pl172_device,
 156         &mmcsd_device,
 157 };
 158
 159 /* Here follows a list of all hw resources that the platform devices
 160  * allocate. Note, clock dependencies are not included
 161  */
 162
 163 static struct resource gpio_resources[] = {
 164         {
 165                 .start = U300_GPIO_BASE,
 166                 .end   = (U300_GPIO_BASE + SZ_4K - 1),
 167                 .flags = IORESOURCE_MEM,
 168         },
 169         {
 170                 .name  = "gpio0",
 171                 .start = IRQ_U300_GPIO_PORT0,
 172                 .end   = IRQ_U300_GPIO_PORT0,
 173                 .flags = IORESOURCE_IRQ,
 174         },
 175         {
 176                 .name  = "gpio1",
 177                 .start = IRQ_U300_GPIO_PORT1,
 178                 .end   = IRQ_U300_GPIO_PORT1,
 179                 .flags = IORESOURCE_IRQ,
 180         },
 181         {
 182                 .name  = "gpio2",
 183                 .start = IRQ_U300_GPIO_PORT2,
 184                 .end   = IRQ_U300_GPIO_PORT2,
 185                 .flags = IORESOURCE_IRQ,
 186         },
 187         {
 188                 .name  = "gpio3",
 189                 .start = IRQ_U300_GPIO_PORT3,
 190                 .end   = IRQ_U300_GPIO_PORT3,
 191                 .flags = IORESOURCE_IRQ,
 192         },
 193         {
 194                 .name  = "gpio4",
 195                 .start = IRQ_U300_GPIO_PORT4,
 196                 .end   = IRQ_U300_GPIO_PORT4,
 197                 .flags = IORESOURCE_IRQ,
 198         },
 199         {
 200                 .name  = "gpio5",
 201                 .start = IRQ_U300_GPIO_PORT5,
 202                 .end   = IRQ_U300_GPIO_PORT5,
 203                 .flags = IORESOURCE_IRQ,
 204         },
 205         {
 206                 .name  = "gpio6",
 207                 .start = IRQ_U300_GPIO_PORT6,
 208                 .end   = IRQ_U300_GPIO_PORT6,
 209                 .flags = IORESOURCE_IRQ,
 210         },
 211 };
 212
 213 static struct resource keypad_resources[] = {
 214         {
 215                 .start = U300_KEYPAD_BASE,
 216                 .end   = U300_KEYPAD_BASE + SZ_4K - 1,
 217                 .flags = IORESOURCE_MEM,
 218         },
 219         {
 220                 .name  = "coh901461-press",
 221                 .start = IRQ_U300_KEYPAD_KEYBF,
 222                 .end   = IRQ_U300_KEYPAD_KEYBF,
 223                 .flags = IORESOURCE_IRQ,
 224         },
 225         {
 226                 .name  = "coh901461-release",
 227                 .start = IRQ_U300_KEYPAD_KEYBR,
 228                 .end   = IRQ_U300_KEYPAD_KEYBR,
 229                 .flags = IORESOURCE_IRQ,
 230         },
 231 };
 232
 233 static struct resource rtc_resources[] = {
 234         {
 235                 .start = U300_RTC_BASE,
 236                 .end   = U300_RTC_BASE + SZ_4K - 1,
 237                 .flags = IORESOURCE_MEM,
 238         },
 239         {
 240                 .start = IRQ_U300_RTC,
 241                 .end   = IRQ_U300_RTC,
 242                 .flags = IORESOURCE_IRQ,
 243         },
 244 };
 245
 246 /*
 247  * Fsmc does have IRQs: #43 and #44 (NFIF and NFIF2)
 248  * but these are not yet used by the driver.
 249  */
 250 static struct resource fsmc_resources[] = {
 251         {
 252                 .name  = "nand_addr",
 253                 .start = U300_NAND_CS0_PHYS_BASE + PLAT_NAND_ALE,
 254                 .end   = U300_NAND_CS0_PHYS_BASE + PLAT_NAND_ALE + SZ_16K - 1,
 255                 .flags = IORESOURCE_MEM,
 256         },
 257         {
 258                 .name  = "nand_cmd",
 259                 .start = U300_NAND_CS0_PHYS_BASE + PLAT_NAND_CLE,
 260                 .end   = U300_NAND_CS0_PHYS_BASE + PLAT_NAND_CLE + SZ_16K - 1,
 261                 .flags = IORESOURCE_MEM,
 262         },
 263         {
 264                 .name  = "nand_data",
 265                 .start = U300_NAND_CS0_PHYS_BASE,
 266                 .end   = U300_NAND_CS0_PHYS_BASE + SZ_16K - 1,
 267                 .flags = IORESOURCE_MEM,
 268         },
 269         {
 270                 .name  = "fsmc_regs",
 271                 .start = U300_NAND_IF_PHYS_BASE,
 272                 .end   = U300_NAND_IF_PHYS_BASE + SZ_4K - 1,
 273                 .flags = IORESOURCE_MEM,
 274         },
 275 };
 276
 277 static struct resource i2c0_resources[] = {
 278         {
 279                 .start = U300_I2C0_BASE,
 280                 .end   = U300_I2C0_BASE + SZ_4K - 1,
 281                 .flags = IORESOURCE_MEM,
 282         },
 283         {
 284                 .start = IRQ_U300_I2C0,
 285                 .end   = IRQ_U300_I2C0,
 286                 .flags = IORESOURCE_IRQ,
 287         },
 288 };
 289
 290 static struct resource i2c1_resources[] = {
 291         {
 292                 .start = U300_I2C1_BASE,
 293                 .end   = U300_I2C1_BASE + SZ_4K - 1,
 294                 .flags = IORESOURCE_MEM,
 295         },
 296         {
 297                 .start = IRQ_U300_I2C1,
 298                 .end   = IRQ_U300_I2C1,
 299                 .flags = IORESOURCE_IRQ,
 300         },
 301
 302 };
 303
 304 static struct resource wdog_resources[] = {
 305         {
 306                 .start = U300_WDOG_BASE,
 307                 .end   = U300_WDOG_BASE + SZ_4K - 1,
 308                 .flags = IORESOURCE_MEM,
 309         },
 310         {
 311                 .start = IRQ_U300_WDOG,
 312                 .end   = IRQ_U300_WDOG,
 313                 .flags = IORESOURCE_IRQ,
 314         }
 315 };
 316
 317 static struct resource dma_resource[] = {
 318         {
 319                 .start = U300_DMAC_BASE,
 320                 .end = U300_DMAC_BASE + PAGE_SIZE - 1,
 321                 .flags =  IORESOURCE_MEM,
 322         },
 323         {
 324                 .start = IRQ_U300_DMA,
 325                 .end = IRQ_U300_DMA,
 326                 .flags =  IORESOURCE_IRQ,
 327         }
 328 };
 329
 330 /* points out all dma slave channels.
 331  * Syntax is [A1, B1, A2, B2, .... ,-1,-1]
 332  * Select all channels from A to B, end of list is marked with -1,-1
 333  */
 334 static int dma_slave_channels[] = {
 335         U300_DMA_MSL_TX_0, U300_DMA_SPI_RX,
 336         U300_DMA_UART1_TX, U300_DMA_UART1_RX, -1, -1};
 337
 338 /* points out all dma memcpy channels. */
 339 static int dma_memcpy_channels[] = {
 340         U300_DMA_GENERAL_PURPOSE_0, U300_DMA_GENERAL_PURPOSE_8, -1, -1};
 341
 342 /** register dma for memory access
 343  *
 344  * active  1 means dma intends to access memory
 345  *         0 means dma wont access memory
 346  */
 347 static void coh901318_access_memory_state(struct device *dev, bool active)
 348 {
 349 }
 350
 351 #define flags_memcpy_config (COH901318_CX_CFG_CH_DISABLE | \
 352                         COH901318_CX_CFG_RM_MEMORY_TO_MEMORY | \
 353                         COH901318_CX_CFG_LCR_DISABLE | \
 354                         COH901318_CX_CFG_TC_IRQ_ENABLE | \
 355                         COH901318_CX_CFG_BE_IRQ_ENABLE)
 356 #define flags_memcpy_lli_chained (COH901318_CX_CTRL_TC_ENABLE | \
 357                         COH901318_CX_CTRL_BURST_COUNT_32_BYTES | \
 358                         COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | \
 359                         COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE | \
 360                         COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | \
 361                         COH901318_CX_CTRL_DST_ADDR_INC_ENABLE | \
 362                         COH901318_CX_CTRL_MASTER_MODE_M1RW | \
 363                         COH901318_CX_CTRL_TCP_DISABLE | \
 364                         COH901318_CX_CTRL_TC_IRQ_DISABLE | \
 365                         COH901318_CX_CTRL_HSP_DISABLE | \
 366                         COH901318_CX_CTRL_HSS_DISABLE | \
 367                         COH901318_CX_CTRL_DDMA_LEGACY | \
 368                         COH901318_CX_CTRL_PRDD_SOURCE)
 369 #define flags_memcpy_lli (COH901318_CX_CTRL_TC_ENABLE | \
 370                         COH901318_CX_CTRL_BURST_COUNT_32_BYTES | \
 371                         COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | \
 372                         COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE | \
 373                         COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | \
 374                         COH901318_CX_CTRL_DST_ADDR_INC_ENABLE | \
 375                         COH901318_CX_CTRL_MASTER_MODE_M1RW | \
 376                         COH901318_CX_CTRL_TCP_DISABLE | \
 377                         COH901318_CX_CTRL_TC_IRQ_DISABLE | \
 378                         COH901318_CX_CTRL_HSP_DISABLE | \
 379                         COH901318_CX_CTRL_HSS_DISABLE | \
 380                         COH901318_CX_CTRL_DDMA_LEGACY | \
 381                         COH901318_CX_CTRL_PRDD_SOURCE)
 382 #define flags_memcpy_lli_last (COH901318_CX_CTRL_TC_ENABLE | \
 383                         COH901318_CX_CTRL_BURST_COUNT_32_BYTES | \
 384                         COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | \
 385                         COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE | \
 386                         COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | \
 387                         COH901318_CX_CTRL_DST_ADDR_INC_ENABLE | \
 388                         COH901318_CX_CTRL_MASTER_MODE_M1RW | \
 389                         COH901318_CX_CTRL_TCP_DISABLE | \
 390                         COH901318_CX_CTRL_TC_IRQ_ENABLE | \
 391                         COH901318_CX_CTRL_HSP_DISABLE | \
 392                         COH901318_CX_CTRL_HSS_DISABLE | \
 393                         COH901318_CX_CTRL_DDMA_LEGACY | \
 394                         COH901318_CX_CTRL_PRDD_SOURCE)
 395
 396 const struct coh_dma_channel chan_config[U300_DMA_CHANNELS] = {
 397         {
 398                 .number = U300_DMA_MSL_TX_0,
 399                 .name = "MSL TX 0",
 400                 .priority_high = 0,
 401                 .dev_addr = U300_MSL_BASE + 0 * 0x40 + 0x20,
 402         },
 403         {
 404                 .number = U300_DMA_MSL_TX_1,
 405                 .name = "MSL TX 1",
 406                 .priority_high = 0,
 407                 .dev_addr = U300_MSL_BASE + 1 * 0x40 + 0x20,
 408                 .param.config = COH901318_CX_CFG_CH_DISABLE |
 409                                 COH901318_CX_CFG_LCR_DISABLE |
 410                                 COH901318_CX_CFG_TC_IRQ_ENABLE |
 411                                 COH901318_CX_CFG_BE_IRQ_ENABLE,
 412                 .param.ctrl_lli_chained = 0 |
 413                                 COH901318_CX_CTRL_TC_ENABLE |
 414                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 415                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 416                                 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
 417                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 418                                 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
 419                                 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
 420                                 COH901318_CX_CTRL_TCP_DISABLE |
 421                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
 422                                 COH901318_CX_CTRL_HSP_ENABLE |
 423                                 COH901318_CX_CTRL_HSS_DISABLE |
 424                                 COH901318_CX_CTRL_DDMA_LEGACY |
 425                                 COH901318_CX_CTRL_PRDD_SOURCE,
 426                 .param.ctrl_lli = 0 |
 427                                 COH901318_CX_CTRL_TC_ENABLE |
 428                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 429                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 430                                 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
 431                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 432                                 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
 433                                 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
 434                                 COH901318_CX_CTRL_TCP_ENABLE |
 435                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
 436                                 COH901318_CX_CTRL_HSP_ENABLE |
 437                                 COH901318_CX_CTRL_HSS_DISABLE |
 438                                 COH901318_CX_CTRL_DDMA_LEGACY |
 439                                 COH901318_CX_CTRL_PRDD_SOURCE,
 440                 .param.ctrl_lli_last = 0 |
 441                                 COH901318_CX_CTRL_TC_ENABLE |
 442                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 443                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 444                                 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
 445                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 446                                 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
 447                                 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
 448                                 COH901318_CX_CTRL_TCP_ENABLE |
 449                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
 450                                 COH901318_CX_CTRL_HSP_ENABLE |
 451                                 COH901318_CX_CTRL_HSS_DISABLE |
 452                                 COH901318_CX_CTRL_DDMA_LEGACY |
 453                                 COH901318_CX_CTRL_PRDD_SOURCE,
 454         },
 455         {
 456                 .number = U300_DMA_MSL_TX_2,
 457                 .name = "MSL TX 2",
 458                 .priority_high = 0,
 459                 .dev_addr = U300_MSL_BASE + 2 * 0x40 + 0x20,
 460                 .param.config = COH901318_CX_CFG_CH_DISABLE |
 461                                 COH901318_CX_CFG_LCR_DISABLE |
 462                                 COH901318_CX_CFG_TC_IRQ_ENABLE |
 463                                 COH901318_CX_CFG_BE_IRQ_ENABLE,
 464                 .param.ctrl_lli_chained = 0 |
 465                                 COH901318_CX_CTRL_TC_ENABLE |
 466                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 467                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 468                                 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
 469                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 470                                 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
 471                                 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
 472                                 COH901318_CX_CTRL_TCP_DISABLE |
 473                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
 474                                 COH901318_CX_CTRL_HSP_ENABLE |
 475                                 COH901318_CX_CTRL_HSS_DISABLE |
 476                                 COH901318_CX_CTRL_DDMA_LEGACY |
 477                                 COH901318_CX_CTRL_PRDD_SOURCE,
 478                 .param.ctrl_lli = 0 |
 479                                 COH901318_CX_CTRL_TC_ENABLE |
 480                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 481                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 482                                 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
 483                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 484                                 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
 485                                 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
 486                                 COH901318_CX_CTRL_TCP_ENABLE |
 487                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
 488                                 COH901318_CX_CTRL_HSP_ENABLE |
 489                                 COH901318_CX_CTRL_HSS_DISABLE |
 490                                 COH901318_CX_CTRL_DDMA_LEGACY |
 491                                 COH901318_CX_CTRL_PRDD_SOURCE,
 492                 .param.ctrl_lli_last = 0 |
 493                                 COH901318_CX_CTRL_TC_ENABLE |
 494                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 495                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 496                                 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
 497                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 498                                 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
 499                                 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
 500                                 COH901318_CX_CTRL_TCP_ENABLE |
 501                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
 502                                 COH901318_CX_CTRL_HSP_ENABLE |
 503                                 COH901318_CX_CTRL_HSS_DISABLE |
 504                                 COH901318_CX_CTRL_DDMA_LEGACY |
 505                                 COH901318_CX_CTRL_PRDD_SOURCE,
 506                 .desc_nbr_max = 10,
 507         },
 508         {
 509                 .number = U300_DMA_MSL_TX_3,
 510                 .name = "MSL TX 3",
 511                 .priority_high = 0,
 512                 .dev_addr = U300_MSL_BASE + 3 * 0x40 + 0x20,
 513                 .param.config = COH901318_CX_CFG_CH_DISABLE |
 514                                 COH901318_CX_CFG_LCR_DISABLE |
 515                                 COH901318_CX_CFG_TC_IRQ_ENABLE |
 516                                 COH901318_CX_CFG_BE_IRQ_ENABLE,
 517                 .param.ctrl_lli_chained = 0 |
 518                                 COH901318_CX_CTRL_TC_ENABLE |
 519                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 520                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 521                                 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
 522                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 523                                 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
 524                                 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
 525                                 COH901318_CX_CTRL_TCP_DISABLE |
 526                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
 527                                 COH901318_CX_CTRL_HSP_ENABLE |
 528                                 COH901318_CX_CTRL_HSS_DISABLE |
 529                                 COH901318_CX_CTRL_DDMA_LEGACY |
 530                                 COH901318_CX_CTRL_PRDD_SOURCE,
 531                 .param.ctrl_lli = 0 |
 532                                 COH901318_CX_CTRL_TC_ENABLE |
 533                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 534                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 535                                 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
 536                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 537                                 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
 538                                 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
 539                                 COH901318_CX_CTRL_TCP_ENABLE |
 540                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
 541                                 COH901318_CX_CTRL_HSP_ENABLE |
 542                                 COH901318_CX_CTRL_HSS_DISABLE |
 543                                 COH901318_CX_CTRL_DDMA_LEGACY |
 544                                 COH901318_CX_CTRL_PRDD_SOURCE,
 545                 .param.ctrl_lli_last = 0 |
 546                                 COH901318_CX_CTRL_TC_ENABLE |
 547                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 548                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 549                                 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
 550                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 551                                 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
 552                                 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
 553                                 COH901318_CX_CTRL_TCP_ENABLE |
 554                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
 555                                 COH901318_CX_CTRL_HSP_ENABLE |
 556                                 COH901318_CX_CTRL_HSS_DISABLE |
 557                                 COH901318_CX_CTRL_DDMA_LEGACY |
 558                                 COH901318_CX_CTRL_PRDD_SOURCE,
 559         },
 560         {
 561                 .number = U300_DMA_MSL_TX_4,
 562                 .name = "MSL TX 4",
 563                 .priority_high = 0,
 564                 .dev_addr = U300_MSL_BASE + 4 * 0x40 + 0x20,
 565                 .param.config = COH901318_CX_CFG_CH_DISABLE |
 566                                 COH901318_CX_CFG_LCR_DISABLE |
 567                                 COH901318_CX_CFG_TC_IRQ_ENABLE |
 568                                 COH901318_CX_CFG_BE_IRQ_ENABLE,
 569                 .param.ctrl_lli_chained = 0 |
 570                                 COH901318_CX_CTRL_TC_ENABLE |
 571                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 572                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 573                                 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
 574                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 575                                 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
 576                                 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
 577                                 COH901318_CX_CTRL_TCP_DISABLE |
 578                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
 579                                 COH901318_CX_CTRL_HSP_ENABLE |
 580                                 COH901318_CX_CTRL_HSS_DISABLE |
 581                                 COH901318_CX_CTRL_DDMA_LEGACY |
 582                                 COH901318_CX_CTRL_PRDD_SOURCE,
 583                 .param.ctrl_lli = 0 |
 584                                 COH901318_CX_CTRL_TC_ENABLE |
 585                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 586                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 587                                 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
 588                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 589                                 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
 590                                 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
 591                                 COH901318_CX_CTRL_TCP_ENABLE |
 592                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
 593                                 COH901318_CX_CTRL_HSP_ENABLE |
 594                                 COH901318_CX_CTRL_HSS_DISABLE |
 595                                 COH901318_CX_CTRL_DDMA_LEGACY |
 596                                 COH901318_CX_CTRL_PRDD_SOURCE,
 597                 .param.ctrl_lli_last = 0 |
 598                                 COH901318_CX_CTRL_TC_ENABLE |
 599                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 600                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 601                                 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
 602                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 603                                 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
 604                                 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
 605                                 COH901318_CX_CTRL_TCP_ENABLE |
 606                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
 607                                 COH901318_CX_CTRL_HSP_ENABLE |
 608                                 COH901318_CX_CTRL_HSS_DISABLE |
 609                                 COH901318_CX_CTRL_DDMA_LEGACY |
 610                                 COH901318_CX_CTRL_PRDD_SOURCE,
 611         },
 612         {
 613                 .number = U300_DMA_MSL_TX_5,
 614                 .name = "MSL TX 5",
 615                 .priority_high = 0,
 616                 .dev_addr = U300_MSL_BASE + 5 * 0x40 + 0x20,
 617         },
 618         {
 619                 .number = U300_DMA_MSL_TX_6,
 620                 .name = "MSL TX 6",
 621                 .priority_high = 0,
 622                 .dev_addr = U300_MSL_BASE + 6 * 0x40 + 0x20,
 623         },
 624         {
 625                 .number = U300_DMA_MSL_RX_0,
 626                 .name = "MSL RX 0",
 627                 .priority_high = 0,
 628                 .dev_addr = U300_MSL_BASE + 0 * 0x40 + 0x220,
 629         },
 630         {
 631                 .number = U300_DMA_MSL_RX_1,
 632                 .name = "MSL RX 1",
 633                 .priority_high = 0,
 634                 .dev_addr = U300_MSL_BASE + 1 * 0x40 + 0x220,
 635                 .param.config = COH901318_CX_CFG_CH_DISABLE |
 636                                 COH901318_CX_CFG_LCR_DISABLE |
 637                                 COH901318_CX_CFG_TC_IRQ_ENABLE |
 638                                 COH901318_CX_CFG_BE_IRQ_ENABLE,
 639                 .param.ctrl_lli_chained = 0 |
 640                                 COH901318_CX_CTRL_TC_ENABLE |
 641                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 642                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 643                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
 644                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 645                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
 646                                 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
 647                                 COH901318_CX_CTRL_TCP_DISABLE |
 648                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
 649                                 COH901318_CX_CTRL_HSP_ENABLE |
 650                                 COH901318_CX_CTRL_HSS_DISABLE |
 651                                 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
 652                                 COH901318_CX_CTRL_PRDD_DEST,
 653                 .param.ctrl_lli = 0,
 654                 .param.ctrl_lli_last = 0 |
 655                                 COH901318_CX_CTRL_TC_ENABLE |
 656                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 657                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 658                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
 659                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 660                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
 661                                 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
 662                                 COH901318_CX_CTRL_TCP_DISABLE |
 663                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
 664                                 COH901318_CX_CTRL_HSP_ENABLE |
 665                                 COH901318_CX_CTRL_HSS_DISABLE |
 666                                 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
 667                                 COH901318_CX_CTRL_PRDD_DEST,
 668         },
 669         {
 670                 .number = U300_DMA_MSL_RX_2,
 671                 .name = "MSL RX 2",
 672                 .priority_high = 0,
 673                 .dev_addr = U300_MSL_BASE + 2 * 0x40 + 0x220,
 674                 .param.config = COH901318_CX_CFG_CH_DISABLE |
 675                                 COH901318_CX_CFG_LCR_DISABLE |
 676                                 COH901318_CX_CFG_TC_IRQ_ENABLE |
 677                                 COH901318_CX_CFG_BE_IRQ_ENABLE,
 678                 .param.ctrl_lli_chained = 0 |
 679                                 COH901318_CX_CTRL_TC_ENABLE |
 680                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 681                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 682                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
 683                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 684                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
 685                                 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
 686                                 COH901318_CX_CTRL_TCP_DISABLE |
 687                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
 688                                 COH901318_CX_CTRL_HSP_ENABLE |
 689                                 COH901318_CX_CTRL_HSS_DISABLE |
 690                                 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
 691                                 COH901318_CX_CTRL_PRDD_DEST,
 692                 .param.ctrl_lli = 0 |
 693                                 COH901318_CX_CTRL_TC_ENABLE |
 694                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 695                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 696                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
 697                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 698                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
 699                                 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
 700                                 COH901318_CX_CTRL_TCP_DISABLE |
 701                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
 702                                 COH901318_CX_CTRL_HSP_ENABLE |
 703                                 COH901318_CX_CTRL_HSS_DISABLE |
 704                                 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
 705                                 COH901318_CX_CTRL_PRDD_DEST,
 706                 .param.ctrl_lli_last = 0 |
 707                                 COH901318_CX_CTRL_TC_ENABLE |
 708                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 709                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 710                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
 711                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 712                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
 713                                 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
 714                                 COH901318_CX_CTRL_TCP_DISABLE |
 715                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
 716                                 COH901318_CX_CTRL_HSP_ENABLE |
 717                                 COH901318_CX_CTRL_HSS_DISABLE |
 718                                 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
 719                                 COH901318_CX_CTRL_PRDD_DEST,
 720         },
 721         {
 722                 .number = U300_DMA_MSL_RX_3,
 723                 .name = "MSL RX 3",
 724                 .priority_high = 0,
 725                 .dev_addr = U300_MSL_BASE + 3 * 0x40 + 0x220,
 726                 .param.config = COH901318_CX_CFG_CH_DISABLE |
 727                                 COH901318_CX_CFG_LCR_DISABLE |
 728                                 COH901318_CX_CFG_TC_IRQ_ENABLE |
 729                                 COH901318_CX_CFG_BE_IRQ_ENABLE,
 730                 .param.ctrl_lli_chained = 0 |
 731                                 COH901318_CX_CTRL_TC_ENABLE |
 732                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 733                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 734                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
 735                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 736                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
 737                                 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
 738                                 COH901318_CX_CTRL_TCP_DISABLE |
 739                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
 740                                 COH901318_CX_CTRL_HSP_ENABLE |
 741                                 COH901318_CX_CTRL_HSS_DISABLE |
 742                                 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
 743                                 COH901318_CX_CTRL_PRDD_DEST,
 744                 .param.ctrl_lli = 0 |
 745                                 COH901318_CX_CTRL_TC_ENABLE |
 746                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 747                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 748                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
 749                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 750                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
 751                                 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
 752                                 COH901318_CX_CTRL_TCP_DISABLE |
 753                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
 754                                 COH901318_CX_CTRL_HSP_ENABLE |
 755                                 COH901318_CX_CTRL_HSS_DISABLE |
 756                                 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
 757                                 COH901318_CX_CTRL_PRDD_DEST,
 758                 .param.ctrl_lli_last = 0 |
 759                                 COH901318_CX_CTRL_TC_ENABLE |
 760                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 761                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 762                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
 763                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 764                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
 765                                 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
 766                                 COH901318_CX_CTRL_TCP_DISABLE |
 767                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
 768                                 COH901318_CX_CTRL_HSP_ENABLE |
 769                                 COH901318_CX_CTRL_HSS_DISABLE |
 770                                 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
 771                                 COH901318_CX_CTRL_PRDD_DEST,
 772         },
 773         {
 774                 .number = U300_DMA_MSL_RX_4,
 775                 .name = "MSL RX 4",
 776                 .priority_high = 0,
 777                 .dev_addr = U300_MSL_BASE + 4 * 0x40 + 0x220,
 778                 .param.config = COH901318_CX_CFG_CH_DISABLE |
 779                                 COH901318_CX_CFG_LCR_DISABLE |
 780                                 COH901318_CX_CFG_TC_IRQ_ENABLE |
 781                                 COH901318_CX_CFG_BE_IRQ_ENABLE,
 782                 .param.ctrl_lli_chained = 0 |
 783                                 COH901318_CX_CTRL_TC_ENABLE |
 784                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 785                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 786                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
 787                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 788                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
 789                                 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
 790                                 COH901318_CX_CTRL_TCP_DISABLE |
 791                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
 792                                 COH901318_CX_CTRL_HSP_ENABLE |
 793                                 COH901318_CX_CTRL_HSS_DISABLE |
 794                                 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
 795                                 COH901318_CX_CTRL_PRDD_DEST,
 796                 .param.ctrl_lli = 0 |
 797                                 COH901318_CX_CTRL_TC_ENABLE |
 798                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 799                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 800                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
 801                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 802                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
 803                                 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
 804                                 COH901318_CX_CTRL_TCP_DISABLE |
 805                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
 806                                 COH901318_CX_CTRL_HSP_ENABLE |
 807                                 COH901318_CX_CTRL_HSS_DISABLE |
 808                                 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
 809                                 COH901318_CX_CTRL_PRDD_DEST,
 810                 .param.ctrl_lli_last = 0 |
 811                                 COH901318_CX_CTRL_TC_ENABLE |
 812                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 813                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 814                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
 815                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 816                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
 817                                 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
 818                                 COH901318_CX_CTRL_TCP_DISABLE |
 819                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
 820                                 COH901318_CX_CTRL_HSP_ENABLE |
 821                                 COH901318_CX_CTRL_HSS_DISABLE |
 822                                 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
 823                                 COH901318_CX_CTRL_PRDD_DEST,
 824         },
 825         {
 826                 .number = U300_DMA_MSL_RX_5,
 827                 .name = "MSL RX 5",
 828                 .priority_high = 0,
 829                 .dev_addr = U300_MSL_BASE + 5 * 0x40 + 0x220,
 830                 .param.config = COH901318_CX_CFG_CH_DISABLE |
 831                                 COH901318_CX_CFG_LCR_DISABLE |
 832                                 COH901318_CX_CFG_TC_IRQ_ENABLE |
 833                                 COH901318_CX_CFG_BE_IRQ_ENABLE,
 834                 .param.ctrl_lli_chained = 0 |
 835                                 COH901318_CX_CTRL_TC_ENABLE |
 836                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 837                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 838                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
 839                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 840                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
 841                                 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
 842                                 COH901318_CX_CTRL_TCP_DISABLE |
 843                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
 844                                 COH901318_CX_CTRL_HSP_ENABLE |
 845                                 COH901318_CX_CTRL_HSS_DISABLE |
 846                                 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
 847                                 COH901318_CX_CTRL_PRDD_DEST,
 848                 .param.ctrl_lli = 0 |
 849                                 COH901318_CX_CTRL_TC_ENABLE |
 850                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 851                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 852                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
 853                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 854                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
 855                                 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
 856                                 COH901318_CX_CTRL_TCP_DISABLE |
 857                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
 858                                 COH901318_CX_CTRL_HSP_ENABLE |
 859                                 COH901318_CX_CTRL_HSS_DISABLE |
 860                                 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
 861                                 COH901318_CX_CTRL_PRDD_DEST,
 862                 .param.ctrl_lli_last = 0 |
 863                                 COH901318_CX_CTRL_TC_ENABLE |
 864                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 865                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 866                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
 867                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 868                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
 869                                 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
 870                                 COH901318_CX_CTRL_TCP_DISABLE |
 871                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
 872                                 COH901318_CX_CTRL_HSP_ENABLE |
 873                                 COH901318_CX_CTRL_HSS_DISABLE |
 874                                 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
 875                                 COH901318_CX_CTRL_PRDD_DEST,
 876         },
 877         {
 878                 .number = U300_DMA_MSL_RX_6,
 879                 .name = "MSL RX 6",
 880                 .priority_high = 0,
 881                 .dev_addr = U300_MSL_BASE + 6 * 0x40 + 0x220,
 882         },
 883         /*
 884          * Don't set up device address, burst count or size of src
 885          * or dst bus for this peripheral - handled by PrimeCell
 886          * DMA extension.
 887          */
 888         {
 889                 .number = U300_DMA_MMCSD_RX_TX,
 890                 .name = "MMCSD RX TX",
 891                 .priority_high = 0,
 892                 .param.config = COH901318_CX_CFG_CH_DISABLE |
 893                                 COH901318_CX_CFG_LCR_DISABLE |
 894                                 COH901318_CX_CFG_TC_IRQ_ENABLE |
 895                                 COH901318_CX_CFG_BE_IRQ_ENABLE,
 896                 .param.ctrl_lli_chained = 0 |
 897                                 COH901318_CX_CTRL_TC_ENABLE |
 898                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
 899                                 COH901318_CX_CTRL_TCP_ENABLE |
 900                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
 901                                 COH901318_CX_CTRL_HSP_ENABLE |
 902                                 COH901318_CX_CTRL_HSS_DISABLE |
 903                                 COH901318_CX_CTRL_DDMA_LEGACY,
 904                 .param.ctrl_lli = 0 |
 905                                 COH901318_CX_CTRL_TC_ENABLE |
 906                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
 907                                 COH901318_CX_CTRL_TCP_ENABLE |
 908                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
 909                                 COH901318_CX_CTRL_HSP_ENABLE |
 910                                 COH901318_CX_CTRL_HSS_DISABLE |
 911                                 COH901318_CX_CTRL_DDMA_LEGACY,
 912                 .param.ctrl_lli_last = 0 |
 913                                 COH901318_CX_CTRL_TC_ENABLE |
 914                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
 915                                 COH901318_CX_CTRL_TCP_DISABLE |
 916                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
 917                                 COH901318_CX_CTRL_HSP_ENABLE |
 918                                 COH901318_CX_CTRL_HSS_DISABLE |
 919                                 COH901318_CX_CTRL_DDMA_LEGACY,
 920
 921         },
 922         {
 923                 .number = U300_DMA_MSPRO_TX,
 924                 .name = "MSPRO TX",
 925                 .priority_high = 0,
 926         },
 927         {
 928                 .number = U300_DMA_MSPRO_RX,
 929                 .name = "MSPRO RX",
 930                 .priority_high = 0,
 931         },
 932         /*
 933          * Don't set up device address, burst count or size of src
 934          * or dst bus for this peripheral - handled by PrimeCell
 935          * DMA extension.
 936          */
 937         {
 938                 .number = U300_DMA_UART0_TX,
 939                 .name = "UART0 TX",
 940                 .priority_high = 0,
 941                 .param.config = COH901318_CX_CFG_CH_DISABLE |
 942                                 COH901318_CX_CFG_LCR_DISABLE |
 943                                 COH901318_CX_CFG_TC_IRQ_ENABLE |
 944                                 COH901318_CX_CFG_BE_IRQ_ENABLE,
 945                 .param.ctrl_lli_chained = 0 |
 946                                 COH901318_CX_CTRL_TC_ENABLE |
 947                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
 948                                 COH901318_CX_CTRL_TCP_ENABLE |
 949                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
 950                                 COH901318_CX_CTRL_HSP_ENABLE |
 951                                 COH901318_CX_CTRL_HSS_DISABLE |
 952                                 COH901318_CX_CTRL_DDMA_LEGACY,
 953                 .param.ctrl_lli = 0 |
 954                                 COH901318_CX_CTRL_TC_ENABLE |
 955                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
 956                                 COH901318_CX_CTRL_TCP_ENABLE |
 957                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
 958                                 COH901318_CX_CTRL_HSP_ENABLE |
 959                                 COH901318_CX_CTRL_HSS_DISABLE |
 960                                 COH901318_CX_CTRL_DDMA_LEGACY,
 961                 .param.ctrl_lli_last = 0 |
 962                                 COH901318_CX_CTRL_TC_ENABLE |
 963                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
 964                                 COH901318_CX_CTRL_TCP_ENABLE |
 965                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
 966                                 COH901318_CX_CTRL_HSP_ENABLE |
 967                                 COH901318_CX_CTRL_HSS_DISABLE |
 968                                 COH901318_CX_CTRL_DDMA_LEGACY,
 969         },
 970         {
 971                 .number = U300_DMA_UART0_RX,
 972                 .name = "UART0 RX",
 973                 .priority_high = 0,
 974                 .param.config = COH901318_CX_CFG_CH_DISABLE |
 975                                 COH901318_CX_CFG_LCR_DISABLE |
 976                                 COH901318_CX_CFG_TC_IRQ_ENABLE |
 977                                 COH901318_CX_CFG_BE_IRQ_ENABLE,
 978                 .param.ctrl_lli_chained = 0 |
 979                                 COH901318_CX_CTRL_TC_ENABLE |
 980                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
 981                                 COH901318_CX_CTRL_TCP_ENABLE |
 982                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
 983                                 COH901318_CX_CTRL_HSP_ENABLE |
 984                                 COH901318_CX_CTRL_HSS_DISABLE |
 985                                 COH901318_CX_CTRL_DDMA_LEGACY,
 986                 .param.ctrl_lli = 0 |
 987                                 COH901318_CX_CTRL_TC_ENABLE |
 988                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
 989                                 COH901318_CX_CTRL_TCP_ENABLE |
 990                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
 991                                 COH901318_CX_CTRL_HSP_ENABLE |
 992                                 COH901318_CX_CTRL_HSS_DISABLE |
 993                                 COH901318_CX_CTRL_DDMA_LEGACY,
 994                 .param.ctrl_lli_last = 0 |
 995                                 COH901318_CX_CTRL_TC_ENABLE |
 996                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
 997                                 COH901318_CX_CTRL_TCP_ENABLE |
 998                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
 999                                 COH901318_CX_CTRL_HSP_ENABLE |
1000                                 COH901318_CX_CTRL_HSS_DISABLE |
1001                                 COH901318_CX_CTRL_DDMA_LEGACY,
1002         },
1003         {
1004                 .number = U300_DMA_APEX_TX,
1005                 .name = "APEX TX",
1006                 .priority_high = 0,
1007         },
1008         {
1009                 .number = U300_DMA_APEX_RX,
1010                 .name = "APEX RX",
1011                 .priority_high = 0,
1012         },
1013         {
1014                 .number = U300_DMA_PCM_I2S0_TX,
1015                 .name = "PCM I2S0 TX",
1016                 .priority_high = 1,
1017                 .dev_addr = U300_PCM_I2S0_BASE + 0x14,
1018                 .param.config = COH901318_CX_CFG_CH_DISABLE |
1019                                 COH901318_CX_CFG_LCR_DISABLE |
1020                                 COH901318_CX_CFG_TC_IRQ_ENABLE |
1021                                 COH901318_CX_CFG_BE_IRQ_ENABLE,
1022                 .param.ctrl_lli_chained = 0 |
1023                                 COH901318_CX_CTRL_TC_ENABLE |
1024                                 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1025                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1026                                 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
1027                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1028                                 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
1029                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1030                                 COH901318_CX_CTRL_TCP_DISABLE |
1031                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1032                                 COH901318_CX_CTRL_HSP_ENABLE |
1033                                 COH901318_CX_CTRL_HSS_DISABLE |
1034                                 COH901318_CX_CTRL_DDMA_LEGACY |
1035                                 COH901318_CX_CTRL_PRDD_SOURCE,
1036                 .param.ctrl_lli = 0 |
1037                                 COH901318_CX_CTRL_TC_ENABLE |
1038                                 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1039                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1040                                 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
1041                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1042                                 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
1043                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1044                                 COH901318_CX_CTRL_TCP_ENABLE |
1045                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1046                                 COH901318_CX_CTRL_HSP_ENABLE |
1047                                 COH901318_CX_CTRL_HSS_DISABLE |
1048                                 COH901318_CX_CTRL_DDMA_LEGACY |
1049                                 COH901318_CX_CTRL_PRDD_SOURCE,
1050                 .param.ctrl_lli_last = 0 |
1051                                 COH901318_CX_CTRL_TC_ENABLE |
1052                                 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1053                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1054                                 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
1055                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1056                                 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
1057                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1058                                 COH901318_CX_CTRL_TCP_ENABLE |
1059                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1060                                 COH901318_CX_CTRL_HSP_ENABLE |
1061                                 COH901318_CX_CTRL_HSS_DISABLE |
1062                                 COH901318_CX_CTRL_DDMA_LEGACY |
1063                                 COH901318_CX_CTRL_PRDD_SOURCE,
1064         },
1065         {
1066                 .number = U300_DMA_PCM_I2S0_RX,
1067                 .name = "PCM I2S0 RX",
1068                 .priority_high = 1,
1069                 .dev_addr = U300_PCM_I2S0_BASE + 0x10,
1070                 .param.config = COH901318_CX_CFG_CH_DISABLE |
1071                                 COH901318_CX_CFG_LCR_DISABLE |
1072                                 COH901318_CX_CFG_TC_IRQ_ENABLE |
1073                                 COH901318_CX_CFG_BE_IRQ_ENABLE,
1074                 .param.ctrl_lli_chained = 0 |
1075                                 COH901318_CX_CTRL_TC_ENABLE |
1076                                 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1077                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1078                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
1079                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1080                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
1081                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1082                                 COH901318_CX_CTRL_TCP_DISABLE |
1083                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1084                                 COH901318_CX_CTRL_HSP_ENABLE |
1085                                 COH901318_CX_CTRL_HSS_DISABLE |
1086                                 COH901318_CX_CTRL_DDMA_LEGACY |
1087                                 COH901318_CX_CTRL_PRDD_DEST,
1088                 .param.ctrl_lli = 0 |
1089                                 COH901318_CX_CTRL_TC_ENABLE |
1090                                 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1091                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1092                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
1093                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1094                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
1095                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1096                                 COH901318_CX_CTRL_TCP_ENABLE |
1097                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1098                                 COH901318_CX_CTRL_HSP_ENABLE |
1099                                 COH901318_CX_CTRL_HSS_DISABLE |
1100                                 COH901318_CX_CTRL_DDMA_LEGACY |
1101                                 COH901318_CX_CTRL_PRDD_DEST,
1102                 .param.ctrl_lli_last = 0 |
1103                                 COH901318_CX_CTRL_TC_ENABLE |
1104                                 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1105                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1106                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
1107                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1108                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
1109                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1110                                 COH901318_CX_CTRL_TCP_ENABLE |
1111                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
1112                                 COH901318_CX_CTRL_HSP_ENABLE |
1113                                 COH901318_CX_CTRL_HSS_DISABLE |
1114                                 COH901318_CX_CTRL_DDMA_LEGACY |
1115                                 COH901318_CX_CTRL_PRDD_DEST,
1116         },
1117         {
1118                 .number = U300_DMA_PCM_I2S1_TX,
1119                 .name = "PCM I2S1 TX",
1120                 .priority_high = 1,
1121                 .dev_addr =  U300_PCM_I2S1_BASE + 0x14,
1122                 .param.config = COH901318_CX_CFG_CH_DISABLE |
1123                                 COH901318_CX_CFG_LCR_DISABLE |
1124                                 COH901318_CX_CFG_TC_IRQ_ENABLE |
1125                                 COH901318_CX_CFG_BE_IRQ_ENABLE,
1126                 .param.ctrl_lli_chained = 0 |
1127                                 COH901318_CX_CTRL_TC_ENABLE |
1128                                 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1129                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1130                                 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
1131                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1132                                 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
1133                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1134                                 COH901318_CX_CTRL_TCP_DISABLE |
1135                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1136                                 COH901318_CX_CTRL_HSP_ENABLE |
1137                                 COH901318_CX_CTRL_HSS_DISABLE |
1138                                 COH901318_CX_CTRL_DDMA_LEGACY |
1139                                 COH901318_CX_CTRL_PRDD_SOURCE,
1140                 .param.ctrl_lli = 0 |
1141                                 COH901318_CX_CTRL_TC_ENABLE |
1142                                 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1143                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1144                                 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
1145                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1146                                 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
1147                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1148                                 COH901318_CX_CTRL_TCP_ENABLE |
1149                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1150                                 COH901318_CX_CTRL_HSP_ENABLE |
1151                                 COH901318_CX_CTRL_HSS_DISABLE |
1152                                 COH901318_CX_CTRL_DDMA_LEGACY |
1153                                 COH901318_CX_CTRL_PRDD_SOURCE,
1154                 .param.ctrl_lli_last = 0 |
1155                                 COH901318_CX_CTRL_TC_ENABLE |
1156                                 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1157                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1158                                 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
1159                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1160                                 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
1161                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1162                                 COH901318_CX_CTRL_TCP_ENABLE |
1163                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
1164                                 COH901318_CX_CTRL_HSP_ENABLE |
1165                                 COH901318_CX_CTRL_HSS_DISABLE |
1166                                 COH901318_CX_CTRL_DDMA_LEGACY |
1167                                 COH901318_CX_CTRL_PRDD_SOURCE,
1168         },
1169         {
1170                 .number = U300_DMA_PCM_I2S1_RX,
1171                 .name = "PCM I2S1 RX",
1172                 .priority_high = 1,
1173                 .dev_addr = U300_PCM_I2S1_BASE + 0x10,
1174                 .param.config = COH901318_CX_CFG_CH_DISABLE |
1175                                 COH901318_CX_CFG_LCR_DISABLE |
1176                                 COH901318_CX_CFG_TC_IRQ_ENABLE |
1177                                 COH901318_CX_CFG_BE_IRQ_ENABLE,
1178                 .param.ctrl_lli_chained = 0 |
1179                                 COH901318_CX_CTRL_TC_ENABLE |
1180                                 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1181                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1182                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
1183                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1184                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
1185                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1186                                 COH901318_CX_CTRL_TCP_DISABLE |
1187                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1188                                 COH901318_CX_CTRL_HSP_ENABLE |
1189                                 COH901318_CX_CTRL_HSS_DISABLE |
1190                                 COH901318_CX_CTRL_DDMA_LEGACY |
1191                                 COH901318_CX_CTRL_PRDD_DEST,
1192                 .param.ctrl_lli = 0 |
1193                                 COH901318_CX_CTRL_TC_ENABLE |
1194                                 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1195                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1196                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
1197                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1198                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
1199                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1200                                 COH901318_CX_CTRL_TCP_ENABLE |
1201                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1202                                 COH901318_CX_CTRL_HSP_ENABLE |
1203                                 COH901318_CX_CTRL_HSS_DISABLE |
1204                                 COH901318_CX_CTRL_DDMA_LEGACY |
1205                                 COH901318_CX_CTRL_PRDD_DEST,
1206                 .param.ctrl_lli_last = 0 |
1207                                 COH901318_CX_CTRL_TC_ENABLE |
1208                                 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1209                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1210                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
1211                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1212                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
1213                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1214                                 COH901318_CX_CTRL_TCP_ENABLE |
1215                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
1216                                 COH901318_CX_CTRL_HSP_ENABLE |
1217                                 COH901318_CX_CTRL_HSS_DISABLE |
1218                                 COH901318_CX_CTRL_DDMA_LEGACY |
1219                                 COH901318_CX_CTRL_PRDD_DEST,
1220         },
1221         {
1222                 .number = U300_DMA_XGAM_CDI,
1223                 .name = "XGAM CDI",
1224                 .priority_high = 0,
1225         },
1226         {
1227                 .number = U300_DMA_XGAM_PDI,
1228                 .name = "XGAM PDI",
1229                 .priority_high = 0,
1230         },
1231         /*
1232          * Don't set up device address, burst count or size of src
1233          * or dst bus for this peripheral - handled by PrimeCell
1234          * DMA extension.
1235          */
1236         {
1237                 .number = U300_DMA_SPI_TX,
1238                 .name = "SPI TX",
1239                 .priority_high = 0,
1240                 .param.config = COH901318_CX_CFG_CH_DISABLE |
1241                                 COH901318_CX_CFG_LCR_DISABLE |
1242                                 COH901318_CX_CFG_TC_IRQ_ENABLE |
1243                                 COH901318_CX_CFG_BE_IRQ_ENABLE,
1244                 .param.ctrl_lli_chained = 0 |
1245                                 COH901318_CX_CTRL_TC_ENABLE |
1246                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1247                                 COH901318_CX_CTRL_TCP_DISABLE |
1248                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1249                                 COH901318_CX_CTRL_HSP_ENABLE |
1250                                 COH901318_CX_CTRL_HSS_DISABLE |
1251                                 COH901318_CX_CTRL_DDMA_LEGACY,
1252                 .param.ctrl_lli = 0 |
1253                                 COH901318_CX_CTRL_TC_ENABLE |
1254                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1255                                 COH901318_CX_CTRL_TCP_DISABLE |
1256                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
1257                                 COH901318_CX_CTRL_HSP_ENABLE |
1258                                 COH901318_CX_CTRL_HSS_DISABLE |
1259                                 COH901318_CX_CTRL_DDMA_LEGACY,
1260                 .param.ctrl_lli_last = 0 |
1261                                 COH901318_CX_CTRL_TC_ENABLE |
1262                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1263                                 COH901318_CX_CTRL_TCP_DISABLE |
1264                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
1265                                 COH901318_CX_CTRL_HSP_ENABLE |
1266                                 COH901318_CX_CTRL_HSS_DISABLE |
1267                                 COH901318_CX_CTRL_DDMA_LEGACY,
1268         },
1269         {
1270                 .number = U300_DMA_SPI_RX,
1271                 .name = "SPI RX",
1272                 .priority_high = 0,
1273                 .param.config = COH901318_CX_CFG_CH_DISABLE |
1274                                 COH901318_CX_CFG_LCR_DISABLE |
1275                                 COH901318_CX_CFG_TC_IRQ_ENABLE |
1276                                 COH901318_CX_CFG_BE_IRQ_ENABLE,
1277                 .param.ctrl_lli_chained = 0 |
1278                                 COH901318_CX_CTRL_TC_ENABLE |
1279                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1280                                 COH901318_CX_CTRL_TCP_DISABLE |
1281                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1282                                 COH901318_CX_CTRL_HSP_ENABLE |
1283                                 COH901318_CX_CTRL_HSS_DISABLE |
1284                                 COH901318_CX_CTRL_DDMA_LEGACY,
1285                 .param.ctrl_lli = 0 |
1286                                 COH901318_CX_CTRL_TC_ENABLE |
1287                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1288                                 COH901318_CX_CTRL_TCP_DISABLE |
1289                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
1290                                 COH901318_CX_CTRL_HSP_ENABLE |
1291                                 COH901318_CX_CTRL_HSS_DISABLE |
1292                                 COH901318_CX_CTRL_DDMA_LEGACY,
1293                 .param.ctrl_lli_last = 0 |
1294                                 COH901318_CX_CTRL_TC_ENABLE |
1295                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1296                                 COH901318_CX_CTRL_TCP_DISABLE |
1297                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
1298                                 COH901318_CX_CTRL_HSP_ENABLE |
1299                                 COH901318_CX_CTRL_HSS_DISABLE |
1300                                 COH901318_CX_CTRL_DDMA_LEGACY,
1301
1302         },
1303         {
1304                 .number = U300_DMA_GENERAL_PURPOSE_0,
1305                 .name = "GENERAL 00",
1306                 .priority_high = 0,
1307
1308                 .param.config = flags_memcpy_config,
1309                 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1310                 .param.ctrl_lli = flags_memcpy_lli,
1311                 .param.ctrl_lli_last = flags_memcpy_lli_last,
1312         },
1313         {
1314                 .number = U300_DMA_GENERAL_PURPOSE_1,
1315                 .name = "GENERAL 01",
1316                 .priority_high = 0,
1317
1318                 .param.config = flags_memcpy_config,
1319                 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1320                 .param.ctrl_lli = flags_memcpy_lli,
1321                 .param.ctrl_lli_last = flags_memcpy_lli_last,
1322         },
1323         {
1324                 .number = U300_DMA_GENERAL_PURPOSE_2,
1325                 .name = "GENERAL 02",
1326                 .priority_high = 0,
1327
1328                 .param.config = flags_memcpy_config,
1329                 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1330                 .param.ctrl_lli = flags_memcpy_lli,
1331                 .param.ctrl_lli_last = flags_memcpy_lli_last,
1332         },
1333         {
1334                 .number = U300_DMA_GENERAL_PURPOSE_3,
1335                 .name = "GENERAL 03",
1336                 .priority_high = 0,
1337
1338                 .param.config = flags_memcpy_config,
1339                 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1340                 .param.ctrl_lli = flags_memcpy_lli,
1341                 .param.ctrl_lli_last = flags_memcpy_lli_last,
1342         },
1343         {
1344                 .number = U300_DMA_GENERAL_PURPOSE_4,
1345                 .name = "GENERAL 04",
1346                 .priority_high = 0,
1347
1348                 .param.config = flags_memcpy_config,
1349                 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1350                 .param.ctrl_lli = flags_memcpy_lli,
1351                 .param.ctrl_lli_last = flags_memcpy_lli_last,
1352         },
1353         {
1354                 .number = U300_DMA_GENERAL_PURPOSE_5,
1355                 .name = "GENERAL 05",
1356                 .priority_high = 0,
1357
1358                 .param.config = flags_memcpy_config,
1359                 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1360                 .param.ctrl_lli = flags_memcpy_lli,
1361                 .param.ctrl_lli_last = flags_memcpy_lli_last,
1362         },
1363         {
1364                 .number = U300_DMA_GENERAL_PURPOSE_6,
1365                 .name = "GENERAL 06",
1366                 .priority_high = 0,
1367
1368                 .param.config = flags_memcpy_config,
1369                 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1370                 .param.ctrl_lli = flags_memcpy_lli,
1371                 .param.ctrl_lli_last = flags_memcpy_lli_last,
1372         },
1373         {
1374                 .number = U300_DMA_GENERAL_PURPOSE_7,
1375                 .name = "GENERAL 07",
1376                 .priority_high = 0,
1377
1378                 .param.config = flags_memcpy_config,
1379                 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1380                 .param.ctrl_lli = flags_memcpy_lli,
1381                 .param.ctrl_lli_last = flags_memcpy_lli_last,
1382         },
1383         {
1384                 .number = U300_DMA_GENERAL_PURPOSE_8,
1385                 .name = "GENERAL 08",
1386                 .priority_high = 0,
1387
1388                 .param.config = flags_memcpy_config,
1389                 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1390                 .param.ctrl_lli = flags_memcpy_lli,
1391                 .param.ctrl_lli_last = flags_memcpy_lli_last,
1392         },
1393         {
1394                 .number = U300_DMA_UART1_TX,
1395                 .name = "UART1 TX",
1396                 .priority_high = 0,
1397         },
1398         {
1399                 .number = U300_DMA_UART1_RX,
1400                 .name = "UART1 RX",
1401                 .priority_high = 0,
1402         }
1403 };
1404
1405
1406 static struct coh901318_platform coh901318_platform = {
1407         .chans_slave = dma_slave_channels,
1408         .chans_memcpy = dma_memcpy_channels,
1409         .access_memory_state = coh901318_access_memory_state,
1410         .chan_conf = chan_config,
1411         .max_channels = U300_DMA_CHANNELS,
1412 };
1413
1414 static struct resource pinctrl_resources[] = {
1415         {
1416                 .start = U300_SYSCON_BASE,
1417                 .end   = U300_SYSCON_BASE + SZ_4K - 1,
1418                 .flags = IORESOURCE_MEM,
1419         },
1420 };
1421
1422 static struct platform_device wdog_device = {
1423         .name = "coh901327_wdog",
1424         .id = -1,
1425         .num_resources = ARRAY_SIZE(wdog_resources),
1426         .resource = wdog_resources,
1427 };
1428
1429 static struct platform_device i2c0_device = {
1430         .name = "stu300",
1431         .id = 0,
1432         .num_resources = ARRAY_SIZE(i2c0_resources),
1433         .resource = i2c0_resources,
1434 };
1435
1436 static struct platform_device i2c1_device = {
1437         .name = "stu300",
1438         .id = 1,
1439         .num_resources = ARRAY_SIZE(i2c1_resources),
1440         .resource = i2c1_resources,
1441 };
1442
1443 static struct platform_device pinctrl_device = {
1444         .name = "pinctrl-u300",
1445         .id = -1,
1446         .num_resources = ARRAY_SIZE(pinctrl_resources),
1447         .resource = pinctrl_resources,
1448 };
1449
1450 /*
1451  * The different variants have a few different versions of the
1452  * GPIO block, with different number of ports.
1453  */
1454 static struct u300_gpio_platform u300_gpio_plat = {
1455         .ports = 7,
1456         .gpio_base = 0,
1457 };
1458
1459 static struct platform_device gpio_device = {
1460         .name = "u300-gpio",
1461         .id = -1,
1462         .num_resources = ARRAY_SIZE(gpio_resources),
1463         .resource = gpio_resources,
1464         .dev = {
1465                 .platform_data = &u300_gpio_plat,
1466         },
1467 };
1468
1469 static struct platform_device keypad_device = {
1470         .name = "keypad",
1471         .id = -1,
1472         .num_resources = ARRAY_SIZE(keypad_resources),
1473         .resource = keypad_resources,
1474 };
1475
1476 static struct platform_device rtc_device = {
1477         .name = "rtc-coh901331",
1478         .id = -1,
1479         .num_resources = ARRAY_SIZE(rtc_resources),
1480         .resource = rtc_resources,
1481 };
1482
1483 static struct mtd_partition u300_partitions[] = {
1484         {
1485                 .name = "bootrecords",
1486                 .offset = 0,
1487                 .size = SZ_128K,
1488         },
1489         {
1490                 .name = "free",
1491                 .offset = SZ_128K,
1492                 .size = 8064 * SZ_1K,
1493         },
1494         {
1495                 .name = "platform",
1496                 .offset = 8192 * SZ_1K,
1497                 .size = 253952 * SZ_1K,
1498         },
1499 };
1500
1501 static struct fsmc_nand_platform_data nand_platform_data = {
1502         .partitions = u300_partitions,
1503         .nr_partitions = ARRAY_SIZE(u300_partitions),
1504         .options = NAND_SKIP_BBTSCAN,
1505         .width = FSMC_NAND_BW8,
1506 };
1507
1508 static struct platform_device nand_device = {
1509         .name = "fsmc-nand",
1510         .id = -1,
1511         .resource = fsmc_resources,
1512         .num_resources = ARRAY_SIZE(fsmc_resources),
1513         .dev = {
1514                 .platform_data = &nand_platform_data,
1515         },
1516 };
1517
1518 static struct platform_device dma_device = {
1519         .name           = "coh901318",
1520         .id             = -1,
1521         .resource       = dma_resource,
1522         .num_resources  = ARRAY_SIZE(dma_resource),
1523         .dev = {
1524                 .platform_data = &coh901318_platform,
1525                 .coherent_dma_mask = ~0,
1526         },
1527 };
1528
1529 static unsigned long pin_pullup_conf[] = {
1530         PIN_CONF_PACKED(PIN_CONFIG_BIAS_PULL_UP, 1),
1531 };
1532
1533 static unsigned long pin_highz_conf[] = {
1534         PIN_CONF_PACKED(PIN_CONFIG_BIAS_HIGH_IMPEDANCE, 0),
1535 };
1536
1537 /* Pin control settings */
1538 static struct pinctrl_map __initdata u300_pinmux_map[] = {
1539         /* anonymous maps for chip power and EMIFs */
1540         PIN_MAP_MUX_GROUP_HOG_DEFAULT("pinctrl-u300", NULL, "power"),
1541         PIN_MAP_MUX_GROUP_HOG_DEFAULT("pinctrl-u300", NULL, "emif0"),
1542         PIN_MAP_MUX_GROUP_HOG_DEFAULT("pinctrl-u300", NULL, "emif1"),
1543         /* per-device maps for MMC/SD, SPI and UART */
1544         PIN_MAP_MUX_GROUP_DEFAULT("mmci",  "pinctrl-u300", NULL, "mmc0"),
1545         PIN_MAP_MUX_GROUP_DEFAULT("pl022", "pinctrl-u300", NULL, "spi0"),
1546         PIN_MAP_MUX_GROUP_DEFAULT("uart0", "pinctrl-u300", NULL, "uart0"),
1547         /* This pin is used for clock return rather than GPIO */
1548         PIN_MAP_CONFIGS_PIN_DEFAULT("mmci", "pinctrl-u300", "PIO APP GPIO 11",
1549                                     pin_pullup_conf),
1550         /* This pin is used for card detect */
1551         PIN_MAP_CONFIGS_PIN_DEFAULT("mmci", "pinctrl-u300", "PIO MS INS",
1552                                     pin_highz_conf),
1553 };
1554
1555 /*
1556  * Notice that AMBA devices are initialized before platform devices.
1557  *
1558  */
1559 static struct platform_device *platform_devs[] __initdata = {
1560         &dma_device,
1561         &i2c0_device,
1562         &i2c1_device,
1563         &keypad_device,
1564         &rtc_device,
1565         &pinctrl_device,
1566         &gpio_device,
1567         &nand_device,
1568         &wdog_device,
1569 };
1570
1571 /*
1572  * Interrupts: the U300 platforms have two pl190 ARM PrimeCells connected
1573  * together so some interrupts are connected to the first one and some
1574  * to the second one.
1575  */
1576 static void __init u300_init_irq(void)
1577 {
1578         u32 mask[2] = {0, 0};
1579         struct clk *clk;
1580         int i;
1581
1582         /* initialize clocking early, we want to clock the INTCON */
1583         u300_clk_init(U300_SYSCON_VBASE);
1584
1585         /* Bootstrap EMIF and SEMI clocks */
1586         clk = clk_get_sys("pl172", NULL);
1587         BUG_ON(IS_ERR(clk));
1588         clk_prepare_enable(clk);
1589         clk = clk_get_sys("semi", NULL);
1590         BUG_ON(IS_ERR(clk));
1591         clk_prepare_enable(clk);
1592
1593         /* Clock the interrupt controller */
1594         clk = clk_get_sys("intcon", NULL);
1595         BUG_ON(IS_ERR(clk));
1596         clk_prepare_enable(clk);
1597
1598         for (i = 0; i < U300_VIC_IRQS_END; i++)
1599                 set_bit(i, (unsigned long *) &mask[0]);
1600         vic_init((void __iomem *) U300_INTCON0_VBASE, IRQ_U300_INTCON0_START,
1601                  mask[0], mask[0]);
1602         vic_init((void __iomem *) U300_INTCON1_VBASE, IRQ_U300_INTCON1_START,
1603                  mask[1], mask[1]);
1604 }
1605
1606
1607 /*
1608  * U300 platforms peripheral handling
1609  */
1610 struct db_chip {
1611         u16 chipid;
1612         const char *name;
1613 };
1614
1615 /*
1616  * This is a list of the Digital Baseband chips used in the U300 platform.
1617  */
1618 static struct db_chip db_chips[] __initdata = {
1619         {
1620                 .chipid = 0xb800,
1621                 .name = "DB3000",
1622         },
1623         {
1624                 .chipid = 0xc000,
1625                 .name = "DB3100",
1626         },
1627         {
1628                 .chipid = 0xc800,
1629                 .name = "DB3150",
1630         },
1631         {
1632                 .chipid = 0xd800,
1633                 .name = "DB3200",
1634         },
1635         {
1636                 .chipid = 0xe000,
1637                 .name = "DB3250",
1638         },
1639         {
1640                 .chipid = 0xe800,
1641                 .name = "DB3210",
1642         },
1643         {
1644                 .chipid = 0xf000,
1645                 .name = "DB3350 P1x",
1646         },
1647         {
1648                 .chipid = 0xf100,
1649                 .name = "DB3350 P2x",
1650         },
1651         {
1652                 .chipid = 0x0000, /* List terminator */
1653                 .name = NULL,
1654         }
1655 };
1656
1657 static void __init u300_init_check_chip(void)
1658 {
1659
1660         u16 val;
1661         struct db_chip *chip;
1662         const char *chipname;
1663         const char unknown[] = "UNKNOWN";
1664
1665         /* Read out and print chip ID */
1666         val = readw(U300_SYSCON_VBASE + U300_SYSCON_CIDR);
1667         /* This is in funky bigendian order... */
1668         val = (val & 0xFFU) << 8 | (val >> 8);
1669         chip = db_chips;
1670         chipname = unknown;
1671
1672         for ( ; chip->chipid; chip++) {
1673                 if (chip->chipid == (val & 0xFF00U)) {
1674                         chipname = chip->name;
1675                         break;
1676                 }
1677         }
1678         printk(KERN_INFO "Initializing U300 system on %s baseband chip " \
1679                "(chip ID 0x%04x)\n", chipname, val);
1680
1681         if ((val & 0xFF00U) != 0xf000 && (val & 0xFF00U) != 0xf100) {
1682                 printk(KERN_ERR "Platform configured for BS335 " \
1683                        " with DB3350 but %s detected, expect problems!",
1684                        chipname);
1685         }
1686 }
1687
1688 /*
1689  * Some devices and their resources require reserved physical memory from
1690  * the end of the available RAM. This function traverses the list of devices
1691  * and assigns actual addresses to these.
1692  */
1693 static void __init u300_assign_physmem(void)
1694 {
1695         unsigned long curr_start = __pa(high_memory);
1696         int i, j;
1697
1698         for (i = 0; i < ARRAY_SIZE(platform_devs); i++) {
1699                 for (j = 0; j < platform_devs[i]->num_resources; j++) {
1700                         struct resource *const res =
1701                           &platform_devs[i]->resource[j];
1702
1703                         if (IORESOURCE_MEM == res->flags &&
1704                                      0 == res->start) {
1705                                 res->start  = curr_start;
1706                                 res->end   += curr_start;
1707                                 curr_start += resource_size(res);
1708
1709                                 printk(KERN_INFO "core.c: Mapping RAM " \
1710                                        "%#x-%#x to device %s:%s\n",
1711                                         res->start, res->end,
1712                                        platform_devs[i]->name, res->name);
1713                         }
1714                 }
1715         }
1716 }
1717
1718 static void __init u300_init_machine(void)
1719 {
1720         int i;
1721         u16 val;
1722
1723         /* Check what platform we run and print some status information */
1724         u300_init_check_chip();
1725
1726         /* Initialize SPI device with some board specifics */
1727         u300_spi_init(&pl022_device);
1728
1729         /* Register the AMBA devices in the AMBA bus abstraction layer */
1730         for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
1731                 struct amba_device *d = amba_devs[i];
1732                 amba_device_register(d, &iomem_resource);
1733         }
1734
1735         u300_assign_physmem();
1736
1737         /* Initialize pinmuxing */
1738         pinctrl_register_mappings(u300_pinmux_map,
1739                                   ARRAY_SIZE(u300_pinmux_map));
1740
1741         /* Register subdevices on the I2C buses */
1742         u300_i2c_register_board_devices();
1743
1744         /* Register the platform devices */
1745         platform_add_devices(platform_devs, ARRAY_SIZE(platform_devs));
1746
1747         /* Register subdevices on the SPI bus */
1748         u300_spi_register_board_devices();
1749
1750         /* Enable SEMI self refresh */
1751         val = readw(U300_SYSCON_VBASE + U300_SYSCON_SMCR) |
1752                 U300_SYSCON_SMCR_SEMI_SREFREQ_ENABLE;
1753         writew(val, U300_SYSCON_VBASE + U300_SYSCON_SMCR);
1754 }
1755
1756 /* Forward declare this function from the watchdog */
1757 void coh901327_watchdog_reset(void);
1758
1759 static void u300_restart(char mode, const char *cmd)
1760 {
1761         switch (mode) {
1762         case 's':
1763         case 'h':
1764 #ifdef CONFIG_COH901327_WATCHDOG
1765                 coh901327_watchdog_reset();
1766 #endif
1767                 break;
1768         default:
1769                 /* Do nothing */
1770                 break;
1771         }
1772         /* Wait for system do die/reset. */
1773         while (1);
1774 }
1775
1776 MACHINE_START(U300, "Ericsson AB U335 S335/B335 Prototype Board")
1777         /* Maintainer: Linus Walleij <linus.walleij@stericsson.com> */
1778         .atag_offset    = 0x100,
1779         .map_io         = u300_map_io,
1780         .nr_irqs        = 0,
1781         .init_irq       = u300_init_irq,
1782         .init_time      = u300_timer_init,
1783         .init_machine   = u300_init_machine,
1784         .restart        = u300_restart,
1785 MACHINE_END