3 * arch/arm/mach-u300/core.c
6 * Copyright (C) 2007-2012 ST-Ericsson SA
7 * License terms: GNU General Public License (GPL) version 2
8 * Core platform support, IRQ handling and device definitions.
9 * Author: Linus Walleij <linus.walleij@stericsson.com>
11 #include <linux/kernel.h>
12 #include <linux/init.h>
13 #include <linux/spinlock.h>
14 #include <linux/interrupt.h>
15 #include <linux/bitops.h>
16 #include <linux/device.h>
18 #include <linux/termios.h>
19 #include <linux/dmaengine.h>
20 #include <linux/amba/bus.h>
21 #include <linux/amba/mmci.h>
22 #include <linux/amba/serial.h>
23 #include <linux/platform_device.h>
24 #include <linux/gpio.h>
25 #include <linux/clk.h>
26 #include <linux/err.h>
27 #include <linux/mtd/nand.h>
28 #include <linux/mtd/fsmc.h>
29 #include <linux/pinctrl/machine.h>
30 #include <linux/pinctrl/consumer.h>
31 #include <linux/pinctrl/pinconf-generic.h>
32 #include <linux/dma-mapping.h>
33 #include <linux/platform_data/clk-u300.h>
34 #include <linux/platform_data/pinctrl-coh901.h>
36 #include <asm/types.h>
37 #include <asm/setup.h>
38 #include <asm/memory.h>
39 #include <asm/hardware/vic.h>
40 #include <asm/mach/map.h>
41 #include <asm/mach-types.h>
42 #include <asm/mach/arch.h>
44 #include <mach/coh901318.h>
45 #include <mach/hardware.h>
46 #include <mach/syscon.h>
47 #include <mach/irqs.h>
52 #include "u300-gpio.h"
53 #include "dma_channels.h"
56 * Static I/O mappings that are needed for booting the U300 platforms. The
57 * only things we need are the areas where we find the timer, syscon and
58 * intcon, since the remaining device drivers will map their own memory
59 * physical to virtual as the need arise.
61 static struct map_desc u300_io_desc[] __initdata = {
63 .virtual = U300_SLOW_PER_VIRT_BASE,
64 .pfn = __phys_to_pfn(U300_SLOW_PER_PHYS_BASE),
69 .virtual = U300_AHB_PER_VIRT_BASE,
70 .pfn = __phys_to_pfn(U300_AHB_PER_PHYS_BASE),
75 .virtual = U300_FAST_PER_VIRT_BASE,
76 .pfn = __phys_to_pfn(U300_FAST_PER_PHYS_BASE),
82 static void __init u300_map_io(void)
84 iotable_init(u300_io_desc, ARRAY_SIZE(u300_io_desc));
88 * Declaration of devices found on the U300 board and
89 * their respective memory locations.
92 static struct amba_pl011_data uart0_plat_data = {
93 #ifdef CONFIG_COH901318
94 .dma_filter = coh901318_filter_id,
95 .dma_rx_param = (void *) U300_DMA_UART0_RX,
96 .dma_tx_param = (void *) U300_DMA_UART0_TX,
100 /* Slow device at 0x3000 offset */
101 static AMBA_APB_DEVICE(uart0, "uart0", 0, U300_UART0_BASE,
102 { IRQ_U300_UART0 }, &uart0_plat_data);
104 /* The U335 have an additional UART1 on the APP CPU */
105 static struct amba_pl011_data uart1_plat_data = {
106 #ifdef CONFIG_COH901318
107 .dma_filter = coh901318_filter_id,
108 .dma_rx_param = (void *) U300_DMA_UART1_RX,
109 .dma_tx_param = (void *) U300_DMA_UART1_TX,
113 /* Fast device at 0x7000 offset */
114 static AMBA_APB_DEVICE(uart1, "uart1", 0, U300_UART1_BASE,
115 { IRQ_U300_UART1 }, &uart1_plat_data);
117 /* AHB device at 0x4000 offset */
118 static AMBA_APB_DEVICE(pl172, "pl172", 0, U300_EMIF_CFG_BASE, { }, NULL);
120 /* Fast device at 0x6000 offset */
121 static AMBA_APB_DEVICE(pl022, "pl022", 0, U300_SPI_BASE,
122 { IRQ_U300_SPI }, NULL);
124 /* Fast device at 0x1000 offset */
125 #define U300_MMCSD_IRQS { IRQ_U300_MMCSD_MCIINTR0, IRQ_U300_MMCSD_MCIINTR1 }
127 static struct mmci_platform_data mmcsd_platform_data = {
129 * Do not set ocr_mask or voltage translation function,
130 * we have a regulator we can control instead.
134 .gpio_cd = U300_GPIO_PIN_MMC_CD,
136 .capabilities = MMC_CAP_MMC_HIGHSPEED |
137 MMC_CAP_SD_HIGHSPEED | MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA,
138 #ifdef CONFIG_COH901318
139 .dma_filter = coh901318_filter_id,
140 .dma_rx_param = (void *) U300_DMA_MMCSD_RX_TX,
141 /* Don't specify a TX channel, this RX channel is bidirectional */
145 static AMBA_APB_DEVICE(mmcsd, "mmci", 0, U300_MMCSD_BASE,
146 U300_MMCSD_IRQS, &mmcsd_platform_data);
149 * The order of device declaration may be important, since some devices
150 * have dependencies on other devices being initialized first.
152 static struct amba_device *amba_devs[] __initdata = {
160 /* Here follows a list of all hw resources that the platform devices
161 * allocate. Note, clock dependencies are not included
164 static struct resource gpio_resources[] = {
166 .start = U300_GPIO_BASE,
167 .end = (U300_GPIO_BASE + SZ_4K - 1),
168 .flags = IORESOURCE_MEM,
172 .start = IRQ_U300_GPIO_PORT0,
173 .end = IRQ_U300_GPIO_PORT0,
174 .flags = IORESOURCE_IRQ,
178 .start = IRQ_U300_GPIO_PORT1,
179 .end = IRQ_U300_GPIO_PORT1,
180 .flags = IORESOURCE_IRQ,
184 .start = IRQ_U300_GPIO_PORT2,
185 .end = IRQ_U300_GPIO_PORT2,
186 .flags = IORESOURCE_IRQ,
190 .start = IRQ_U300_GPIO_PORT3,
191 .end = IRQ_U300_GPIO_PORT3,
192 .flags = IORESOURCE_IRQ,
196 .start = IRQ_U300_GPIO_PORT4,
197 .end = IRQ_U300_GPIO_PORT4,
198 .flags = IORESOURCE_IRQ,
202 .start = IRQ_U300_GPIO_PORT5,
203 .end = IRQ_U300_GPIO_PORT5,
204 .flags = IORESOURCE_IRQ,
208 .start = IRQ_U300_GPIO_PORT6,
209 .end = IRQ_U300_GPIO_PORT6,
210 .flags = IORESOURCE_IRQ,
214 static struct resource keypad_resources[] = {
216 .start = U300_KEYPAD_BASE,
217 .end = U300_KEYPAD_BASE + SZ_4K - 1,
218 .flags = IORESOURCE_MEM,
221 .name = "coh901461-press",
222 .start = IRQ_U300_KEYPAD_KEYBF,
223 .end = IRQ_U300_KEYPAD_KEYBF,
224 .flags = IORESOURCE_IRQ,
227 .name = "coh901461-release",
228 .start = IRQ_U300_KEYPAD_KEYBR,
229 .end = IRQ_U300_KEYPAD_KEYBR,
230 .flags = IORESOURCE_IRQ,
234 static struct resource rtc_resources[] = {
236 .start = U300_RTC_BASE,
237 .end = U300_RTC_BASE + SZ_4K - 1,
238 .flags = IORESOURCE_MEM,
241 .start = IRQ_U300_RTC,
243 .flags = IORESOURCE_IRQ,
248 * Fsmc does have IRQs: #43 and #44 (NFIF and NFIF2)
249 * but these are not yet used by the driver.
251 static struct resource fsmc_resources[] = {
254 .start = U300_NAND_CS0_PHYS_BASE,
255 .end = U300_NAND_CS0_PHYS_BASE + SZ_16K - 1,
256 .flags = IORESOURCE_MEM,
260 .start = U300_NAND_IF_PHYS_BASE,
261 .end = U300_NAND_IF_PHYS_BASE + SZ_4K - 1,
262 .flags = IORESOURCE_MEM,
266 static struct resource i2c0_resources[] = {
268 .start = U300_I2C0_BASE,
269 .end = U300_I2C0_BASE + SZ_4K - 1,
270 .flags = IORESOURCE_MEM,
273 .start = IRQ_U300_I2C0,
274 .end = IRQ_U300_I2C0,
275 .flags = IORESOURCE_IRQ,
279 static struct resource i2c1_resources[] = {
281 .start = U300_I2C1_BASE,
282 .end = U300_I2C1_BASE + SZ_4K - 1,
283 .flags = IORESOURCE_MEM,
286 .start = IRQ_U300_I2C1,
287 .end = IRQ_U300_I2C1,
288 .flags = IORESOURCE_IRQ,
293 static struct resource wdog_resources[] = {
295 .start = U300_WDOG_BASE,
296 .end = U300_WDOG_BASE + SZ_4K - 1,
297 .flags = IORESOURCE_MEM,
300 .start = IRQ_U300_WDOG,
301 .end = IRQ_U300_WDOG,
302 .flags = IORESOURCE_IRQ,
306 static struct resource dma_resource[] = {
308 .start = U300_DMAC_BASE,
309 .end = U300_DMAC_BASE + PAGE_SIZE - 1,
310 .flags = IORESOURCE_MEM,
313 .start = IRQ_U300_DMA,
315 .flags = IORESOURCE_IRQ,
319 /* points out all dma slave channels.
320 * Syntax is [A1, B1, A2, B2, .... ,-1,-1]
321 * Select all channels from A to B, end of list is marked with -1,-1
323 static int dma_slave_channels[] = {
324 U300_DMA_MSL_TX_0, U300_DMA_SPI_RX,
325 U300_DMA_UART1_TX, U300_DMA_UART1_RX, -1, -1};
327 /* points out all dma memcpy channels. */
328 static int dma_memcpy_channels[] = {
329 U300_DMA_GENERAL_PURPOSE_0, U300_DMA_GENERAL_PURPOSE_8, -1, -1};
331 /** register dma for memory access
333 * active 1 means dma intends to access memory
334 * 0 means dma wont access memory
336 static void coh901318_access_memory_state(struct device *dev, bool active)
340 #define flags_memcpy_config (COH901318_CX_CFG_CH_DISABLE | \
341 COH901318_CX_CFG_RM_MEMORY_TO_MEMORY | \
342 COH901318_CX_CFG_LCR_DISABLE | \
343 COH901318_CX_CFG_TC_IRQ_ENABLE | \
344 COH901318_CX_CFG_BE_IRQ_ENABLE)
345 #define flags_memcpy_lli_chained (COH901318_CX_CTRL_TC_ENABLE | \
346 COH901318_CX_CTRL_BURST_COUNT_32_BYTES | \
347 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | \
348 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE | \
349 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | \
350 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE | \
351 COH901318_CX_CTRL_MASTER_MODE_M1RW | \
352 COH901318_CX_CTRL_TCP_DISABLE | \
353 COH901318_CX_CTRL_TC_IRQ_DISABLE | \
354 COH901318_CX_CTRL_HSP_DISABLE | \
355 COH901318_CX_CTRL_HSS_DISABLE | \
356 COH901318_CX_CTRL_DDMA_LEGACY | \
357 COH901318_CX_CTRL_PRDD_SOURCE)
358 #define flags_memcpy_lli (COH901318_CX_CTRL_TC_ENABLE | \
359 COH901318_CX_CTRL_BURST_COUNT_32_BYTES | \
360 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | \
361 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE | \
362 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | \
363 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE | \
364 COH901318_CX_CTRL_MASTER_MODE_M1RW | \
365 COH901318_CX_CTRL_TCP_DISABLE | \
366 COH901318_CX_CTRL_TC_IRQ_DISABLE | \
367 COH901318_CX_CTRL_HSP_DISABLE | \
368 COH901318_CX_CTRL_HSS_DISABLE | \
369 COH901318_CX_CTRL_DDMA_LEGACY | \
370 COH901318_CX_CTRL_PRDD_SOURCE)
371 #define flags_memcpy_lli_last (COH901318_CX_CTRL_TC_ENABLE | \
372 COH901318_CX_CTRL_BURST_COUNT_32_BYTES | \
373 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | \
374 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE | \
375 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | \
376 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE | \
377 COH901318_CX_CTRL_MASTER_MODE_M1RW | \
378 COH901318_CX_CTRL_TCP_DISABLE | \
379 COH901318_CX_CTRL_TC_IRQ_ENABLE | \
380 COH901318_CX_CTRL_HSP_DISABLE | \
381 COH901318_CX_CTRL_HSS_DISABLE | \
382 COH901318_CX_CTRL_DDMA_LEGACY | \
383 COH901318_CX_CTRL_PRDD_SOURCE)
385 const struct coh_dma_channel chan_config[U300_DMA_CHANNELS] = {
387 .number = U300_DMA_MSL_TX_0,
390 .dev_addr = U300_MSL_BASE + 0 * 0x40 + 0x20,
393 .number = U300_DMA_MSL_TX_1,
396 .dev_addr = U300_MSL_BASE + 1 * 0x40 + 0x20,
397 .param.config = COH901318_CX_CFG_CH_DISABLE |
398 COH901318_CX_CFG_LCR_DISABLE |
399 COH901318_CX_CFG_TC_IRQ_ENABLE |
400 COH901318_CX_CFG_BE_IRQ_ENABLE,
401 .param.ctrl_lli_chained = 0 |
402 COH901318_CX_CTRL_TC_ENABLE |
403 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
404 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
405 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
406 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
407 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
408 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
409 COH901318_CX_CTRL_TCP_DISABLE |
410 COH901318_CX_CTRL_TC_IRQ_DISABLE |
411 COH901318_CX_CTRL_HSP_ENABLE |
412 COH901318_CX_CTRL_HSS_DISABLE |
413 COH901318_CX_CTRL_DDMA_LEGACY |
414 COH901318_CX_CTRL_PRDD_SOURCE,
415 .param.ctrl_lli = 0 |
416 COH901318_CX_CTRL_TC_ENABLE |
417 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
418 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
419 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
420 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
421 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
422 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
423 COH901318_CX_CTRL_TCP_ENABLE |
424 COH901318_CX_CTRL_TC_IRQ_DISABLE |
425 COH901318_CX_CTRL_HSP_ENABLE |
426 COH901318_CX_CTRL_HSS_DISABLE |
427 COH901318_CX_CTRL_DDMA_LEGACY |
428 COH901318_CX_CTRL_PRDD_SOURCE,
429 .param.ctrl_lli_last = 0 |
430 COH901318_CX_CTRL_TC_ENABLE |
431 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
432 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
433 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
434 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
435 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
436 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
437 COH901318_CX_CTRL_TCP_ENABLE |
438 COH901318_CX_CTRL_TC_IRQ_ENABLE |
439 COH901318_CX_CTRL_HSP_ENABLE |
440 COH901318_CX_CTRL_HSS_DISABLE |
441 COH901318_CX_CTRL_DDMA_LEGACY |
442 COH901318_CX_CTRL_PRDD_SOURCE,
445 .number = U300_DMA_MSL_TX_2,
448 .dev_addr = U300_MSL_BASE + 2 * 0x40 + 0x20,
449 .param.config = COH901318_CX_CFG_CH_DISABLE |
450 COH901318_CX_CFG_LCR_DISABLE |
451 COH901318_CX_CFG_TC_IRQ_ENABLE |
452 COH901318_CX_CFG_BE_IRQ_ENABLE,
453 .param.ctrl_lli_chained = 0 |
454 COH901318_CX_CTRL_TC_ENABLE |
455 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
456 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
457 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
458 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
459 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
460 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
461 COH901318_CX_CTRL_TCP_DISABLE |
462 COH901318_CX_CTRL_TC_IRQ_DISABLE |
463 COH901318_CX_CTRL_HSP_ENABLE |
464 COH901318_CX_CTRL_HSS_DISABLE |
465 COH901318_CX_CTRL_DDMA_LEGACY |
466 COH901318_CX_CTRL_PRDD_SOURCE,
467 .param.ctrl_lli = 0 |
468 COH901318_CX_CTRL_TC_ENABLE |
469 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
470 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
471 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
472 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
473 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
474 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
475 COH901318_CX_CTRL_TCP_ENABLE |
476 COH901318_CX_CTRL_TC_IRQ_DISABLE |
477 COH901318_CX_CTRL_HSP_ENABLE |
478 COH901318_CX_CTRL_HSS_DISABLE |
479 COH901318_CX_CTRL_DDMA_LEGACY |
480 COH901318_CX_CTRL_PRDD_SOURCE,
481 .param.ctrl_lli_last = 0 |
482 COH901318_CX_CTRL_TC_ENABLE |
483 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
484 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
485 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
486 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
487 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
488 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
489 COH901318_CX_CTRL_TCP_ENABLE |
490 COH901318_CX_CTRL_TC_IRQ_ENABLE |
491 COH901318_CX_CTRL_HSP_ENABLE |
492 COH901318_CX_CTRL_HSS_DISABLE |
493 COH901318_CX_CTRL_DDMA_LEGACY |
494 COH901318_CX_CTRL_PRDD_SOURCE,
498 .number = U300_DMA_MSL_TX_3,
501 .dev_addr = U300_MSL_BASE + 3 * 0x40 + 0x20,
502 .param.config = COH901318_CX_CFG_CH_DISABLE |
503 COH901318_CX_CFG_LCR_DISABLE |
504 COH901318_CX_CFG_TC_IRQ_ENABLE |
505 COH901318_CX_CFG_BE_IRQ_ENABLE,
506 .param.ctrl_lli_chained = 0 |
507 COH901318_CX_CTRL_TC_ENABLE |
508 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
509 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
510 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
511 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
512 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
513 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
514 COH901318_CX_CTRL_TCP_DISABLE |
515 COH901318_CX_CTRL_TC_IRQ_DISABLE |
516 COH901318_CX_CTRL_HSP_ENABLE |
517 COH901318_CX_CTRL_HSS_DISABLE |
518 COH901318_CX_CTRL_DDMA_LEGACY |
519 COH901318_CX_CTRL_PRDD_SOURCE,
520 .param.ctrl_lli = 0 |
521 COH901318_CX_CTRL_TC_ENABLE |
522 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
523 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
524 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
525 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
526 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
527 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
528 COH901318_CX_CTRL_TCP_ENABLE |
529 COH901318_CX_CTRL_TC_IRQ_DISABLE |
530 COH901318_CX_CTRL_HSP_ENABLE |
531 COH901318_CX_CTRL_HSS_DISABLE |
532 COH901318_CX_CTRL_DDMA_LEGACY |
533 COH901318_CX_CTRL_PRDD_SOURCE,
534 .param.ctrl_lli_last = 0 |
535 COH901318_CX_CTRL_TC_ENABLE |
536 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
537 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
538 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
539 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
540 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
541 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
542 COH901318_CX_CTRL_TCP_ENABLE |
543 COH901318_CX_CTRL_TC_IRQ_ENABLE |
544 COH901318_CX_CTRL_HSP_ENABLE |
545 COH901318_CX_CTRL_HSS_DISABLE |
546 COH901318_CX_CTRL_DDMA_LEGACY |
547 COH901318_CX_CTRL_PRDD_SOURCE,
550 .number = U300_DMA_MSL_TX_4,
553 .dev_addr = U300_MSL_BASE + 4 * 0x40 + 0x20,
554 .param.config = COH901318_CX_CFG_CH_DISABLE |
555 COH901318_CX_CFG_LCR_DISABLE |
556 COH901318_CX_CFG_TC_IRQ_ENABLE |
557 COH901318_CX_CFG_BE_IRQ_ENABLE,
558 .param.ctrl_lli_chained = 0 |
559 COH901318_CX_CTRL_TC_ENABLE |
560 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
561 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
562 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
563 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
564 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
565 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
566 COH901318_CX_CTRL_TCP_DISABLE |
567 COH901318_CX_CTRL_TC_IRQ_DISABLE |
568 COH901318_CX_CTRL_HSP_ENABLE |
569 COH901318_CX_CTRL_HSS_DISABLE |
570 COH901318_CX_CTRL_DDMA_LEGACY |
571 COH901318_CX_CTRL_PRDD_SOURCE,
572 .param.ctrl_lli = 0 |
573 COH901318_CX_CTRL_TC_ENABLE |
574 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
575 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
576 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
577 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
578 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
579 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
580 COH901318_CX_CTRL_TCP_ENABLE |
581 COH901318_CX_CTRL_TC_IRQ_DISABLE |
582 COH901318_CX_CTRL_HSP_ENABLE |
583 COH901318_CX_CTRL_HSS_DISABLE |
584 COH901318_CX_CTRL_DDMA_LEGACY |
585 COH901318_CX_CTRL_PRDD_SOURCE,
586 .param.ctrl_lli_last = 0 |
587 COH901318_CX_CTRL_TC_ENABLE |
588 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
589 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
590 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
591 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
592 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
593 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
594 COH901318_CX_CTRL_TCP_ENABLE |
595 COH901318_CX_CTRL_TC_IRQ_ENABLE |
596 COH901318_CX_CTRL_HSP_ENABLE |
597 COH901318_CX_CTRL_HSS_DISABLE |
598 COH901318_CX_CTRL_DDMA_LEGACY |
599 COH901318_CX_CTRL_PRDD_SOURCE,
602 .number = U300_DMA_MSL_TX_5,
605 .dev_addr = U300_MSL_BASE + 5 * 0x40 + 0x20,
608 .number = U300_DMA_MSL_TX_6,
611 .dev_addr = U300_MSL_BASE + 6 * 0x40 + 0x20,
614 .number = U300_DMA_MSL_RX_0,
617 .dev_addr = U300_MSL_BASE + 0 * 0x40 + 0x220,
620 .number = U300_DMA_MSL_RX_1,
623 .dev_addr = U300_MSL_BASE + 1 * 0x40 + 0x220,
624 .param.config = COH901318_CX_CFG_CH_DISABLE |
625 COH901318_CX_CFG_LCR_DISABLE |
626 COH901318_CX_CFG_TC_IRQ_ENABLE |
627 COH901318_CX_CFG_BE_IRQ_ENABLE,
628 .param.ctrl_lli_chained = 0 |
629 COH901318_CX_CTRL_TC_ENABLE |
630 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
631 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
632 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
633 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
634 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
635 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
636 COH901318_CX_CTRL_TCP_DISABLE |
637 COH901318_CX_CTRL_TC_IRQ_DISABLE |
638 COH901318_CX_CTRL_HSP_ENABLE |
639 COH901318_CX_CTRL_HSS_DISABLE |
640 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
641 COH901318_CX_CTRL_PRDD_DEST,
643 .param.ctrl_lli_last = 0 |
644 COH901318_CX_CTRL_TC_ENABLE |
645 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
646 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
647 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
648 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
649 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
650 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
651 COH901318_CX_CTRL_TCP_DISABLE |
652 COH901318_CX_CTRL_TC_IRQ_ENABLE |
653 COH901318_CX_CTRL_HSP_ENABLE |
654 COH901318_CX_CTRL_HSS_DISABLE |
655 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
656 COH901318_CX_CTRL_PRDD_DEST,
659 .number = U300_DMA_MSL_RX_2,
662 .dev_addr = U300_MSL_BASE + 2 * 0x40 + 0x220,
663 .param.config = COH901318_CX_CFG_CH_DISABLE |
664 COH901318_CX_CFG_LCR_DISABLE |
665 COH901318_CX_CFG_TC_IRQ_ENABLE |
666 COH901318_CX_CFG_BE_IRQ_ENABLE,
667 .param.ctrl_lli_chained = 0 |
668 COH901318_CX_CTRL_TC_ENABLE |
669 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
670 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
671 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
672 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
673 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
674 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
675 COH901318_CX_CTRL_TCP_DISABLE |
676 COH901318_CX_CTRL_TC_IRQ_DISABLE |
677 COH901318_CX_CTRL_HSP_ENABLE |
678 COH901318_CX_CTRL_HSS_DISABLE |
679 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
680 COH901318_CX_CTRL_PRDD_DEST,
681 .param.ctrl_lli = 0 |
682 COH901318_CX_CTRL_TC_ENABLE |
683 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
684 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
685 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
686 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
687 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
688 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
689 COH901318_CX_CTRL_TCP_DISABLE |
690 COH901318_CX_CTRL_TC_IRQ_ENABLE |
691 COH901318_CX_CTRL_HSP_ENABLE |
692 COH901318_CX_CTRL_HSS_DISABLE |
693 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
694 COH901318_CX_CTRL_PRDD_DEST,
695 .param.ctrl_lli_last = 0 |
696 COH901318_CX_CTRL_TC_ENABLE |
697 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
698 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
699 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
700 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
701 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
702 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
703 COH901318_CX_CTRL_TCP_DISABLE |
704 COH901318_CX_CTRL_TC_IRQ_ENABLE |
705 COH901318_CX_CTRL_HSP_ENABLE |
706 COH901318_CX_CTRL_HSS_DISABLE |
707 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
708 COH901318_CX_CTRL_PRDD_DEST,
711 .number = U300_DMA_MSL_RX_3,
714 .dev_addr = U300_MSL_BASE + 3 * 0x40 + 0x220,
715 .param.config = COH901318_CX_CFG_CH_DISABLE |
716 COH901318_CX_CFG_LCR_DISABLE |
717 COH901318_CX_CFG_TC_IRQ_ENABLE |
718 COH901318_CX_CFG_BE_IRQ_ENABLE,
719 .param.ctrl_lli_chained = 0 |
720 COH901318_CX_CTRL_TC_ENABLE |
721 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
722 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
723 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
724 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
725 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
726 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
727 COH901318_CX_CTRL_TCP_DISABLE |
728 COH901318_CX_CTRL_TC_IRQ_DISABLE |
729 COH901318_CX_CTRL_HSP_ENABLE |
730 COH901318_CX_CTRL_HSS_DISABLE |
731 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
732 COH901318_CX_CTRL_PRDD_DEST,
733 .param.ctrl_lli = 0 |
734 COH901318_CX_CTRL_TC_ENABLE |
735 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
736 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
737 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
738 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
739 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
740 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
741 COH901318_CX_CTRL_TCP_DISABLE |
742 COH901318_CX_CTRL_TC_IRQ_ENABLE |
743 COH901318_CX_CTRL_HSP_ENABLE |
744 COH901318_CX_CTRL_HSS_DISABLE |
745 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
746 COH901318_CX_CTRL_PRDD_DEST,
747 .param.ctrl_lli_last = 0 |
748 COH901318_CX_CTRL_TC_ENABLE |
749 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
750 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
751 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
752 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
753 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
754 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
755 COH901318_CX_CTRL_TCP_DISABLE |
756 COH901318_CX_CTRL_TC_IRQ_ENABLE |
757 COH901318_CX_CTRL_HSP_ENABLE |
758 COH901318_CX_CTRL_HSS_DISABLE |
759 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
760 COH901318_CX_CTRL_PRDD_DEST,
763 .number = U300_DMA_MSL_RX_4,
766 .dev_addr = U300_MSL_BASE + 4 * 0x40 + 0x220,
767 .param.config = COH901318_CX_CFG_CH_DISABLE |
768 COH901318_CX_CFG_LCR_DISABLE |
769 COH901318_CX_CFG_TC_IRQ_ENABLE |
770 COH901318_CX_CFG_BE_IRQ_ENABLE,
771 .param.ctrl_lli_chained = 0 |
772 COH901318_CX_CTRL_TC_ENABLE |
773 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
774 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
775 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
776 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
777 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
778 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
779 COH901318_CX_CTRL_TCP_DISABLE |
780 COH901318_CX_CTRL_TC_IRQ_DISABLE |
781 COH901318_CX_CTRL_HSP_ENABLE |
782 COH901318_CX_CTRL_HSS_DISABLE |
783 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
784 COH901318_CX_CTRL_PRDD_DEST,
785 .param.ctrl_lli = 0 |
786 COH901318_CX_CTRL_TC_ENABLE |
787 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
788 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
789 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
790 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
791 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
792 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
793 COH901318_CX_CTRL_TCP_DISABLE |
794 COH901318_CX_CTRL_TC_IRQ_ENABLE |
795 COH901318_CX_CTRL_HSP_ENABLE |
796 COH901318_CX_CTRL_HSS_DISABLE |
797 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
798 COH901318_CX_CTRL_PRDD_DEST,
799 .param.ctrl_lli_last = 0 |
800 COH901318_CX_CTRL_TC_ENABLE |
801 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
802 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
803 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
804 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
805 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
806 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
807 COH901318_CX_CTRL_TCP_DISABLE |
808 COH901318_CX_CTRL_TC_IRQ_ENABLE |
809 COH901318_CX_CTRL_HSP_ENABLE |
810 COH901318_CX_CTRL_HSS_DISABLE |
811 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
812 COH901318_CX_CTRL_PRDD_DEST,
815 .number = U300_DMA_MSL_RX_5,
818 .dev_addr = U300_MSL_BASE + 5 * 0x40 + 0x220,
819 .param.config = COH901318_CX_CFG_CH_DISABLE |
820 COH901318_CX_CFG_LCR_DISABLE |
821 COH901318_CX_CFG_TC_IRQ_ENABLE |
822 COH901318_CX_CFG_BE_IRQ_ENABLE,
823 .param.ctrl_lli_chained = 0 |
824 COH901318_CX_CTRL_TC_ENABLE |
825 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
826 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
827 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
828 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
829 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
830 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
831 COH901318_CX_CTRL_TCP_DISABLE |
832 COH901318_CX_CTRL_TC_IRQ_DISABLE |
833 COH901318_CX_CTRL_HSP_ENABLE |
834 COH901318_CX_CTRL_HSS_DISABLE |
835 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
836 COH901318_CX_CTRL_PRDD_DEST,
837 .param.ctrl_lli = 0 |
838 COH901318_CX_CTRL_TC_ENABLE |
839 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
840 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
841 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
842 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
843 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
844 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
845 COH901318_CX_CTRL_TCP_DISABLE |
846 COH901318_CX_CTRL_TC_IRQ_ENABLE |
847 COH901318_CX_CTRL_HSP_ENABLE |
848 COH901318_CX_CTRL_HSS_DISABLE |
849 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
850 COH901318_CX_CTRL_PRDD_DEST,
851 .param.ctrl_lli_last = 0 |
852 COH901318_CX_CTRL_TC_ENABLE |
853 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
854 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
855 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
856 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
857 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
858 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
859 COH901318_CX_CTRL_TCP_DISABLE |
860 COH901318_CX_CTRL_TC_IRQ_ENABLE |
861 COH901318_CX_CTRL_HSP_ENABLE |
862 COH901318_CX_CTRL_HSS_DISABLE |
863 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
864 COH901318_CX_CTRL_PRDD_DEST,
867 .number = U300_DMA_MSL_RX_6,
870 .dev_addr = U300_MSL_BASE + 6 * 0x40 + 0x220,
873 * Don't set up device address, burst count or size of src
874 * or dst bus for this peripheral - handled by PrimeCell
878 .number = U300_DMA_MMCSD_RX_TX,
879 .name = "MMCSD RX TX",
881 .param.config = COH901318_CX_CFG_CH_DISABLE |
882 COH901318_CX_CFG_LCR_DISABLE |
883 COH901318_CX_CFG_TC_IRQ_ENABLE |
884 COH901318_CX_CFG_BE_IRQ_ENABLE,
885 .param.ctrl_lli_chained = 0 |
886 COH901318_CX_CTRL_TC_ENABLE |
887 COH901318_CX_CTRL_MASTER_MODE_M1RW |
888 COH901318_CX_CTRL_TCP_ENABLE |
889 COH901318_CX_CTRL_TC_IRQ_DISABLE |
890 COH901318_CX_CTRL_HSP_ENABLE |
891 COH901318_CX_CTRL_HSS_DISABLE |
892 COH901318_CX_CTRL_DDMA_LEGACY,
893 .param.ctrl_lli = 0 |
894 COH901318_CX_CTRL_TC_ENABLE |
895 COH901318_CX_CTRL_MASTER_MODE_M1RW |
896 COH901318_CX_CTRL_TCP_ENABLE |
897 COH901318_CX_CTRL_TC_IRQ_DISABLE |
898 COH901318_CX_CTRL_HSP_ENABLE |
899 COH901318_CX_CTRL_HSS_DISABLE |
900 COH901318_CX_CTRL_DDMA_LEGACY,
901 .param.ctrl_lli_last = 0 |
902 COH901318_CX_CTRL_TC_ENABLE |
903 COH901318_CX_CTRL_MASTER_MODE_M1RW |
904 COH901318_CX_CTRL_TCP_DISABLE |
905 COH901318_CX_CTRL_TC_IRQ_ENABLE |
906 COH901318_CX_CTRL_HSP_ENABLE |
907 COH901318_CX_CTRL_HSS_DISABLE |
908 COH901318_CX_CTRL_DDMA_LEGACY,
912 .number = U300_DMA_MSPRO_TX,
917 .number = U300_DMA_MSPRO_RX,
922 * Don't set up device address, burst count or size of src
923 * or dst bus for this peripheral - handled by PrimeCell
927 .number = U300_DMA_UART0_TX,
930 .param.config = COH901318_CX_CFG_CH_DISABLE |
931 COH901318_CX_CFG_LCR_DISABLE |
932 COH901318_CX_CFG_TC_IRQ_ENABLE |
933 COH901318_CX_CFG_BE_IRQ_ENABLE,
934 .param.ctrl_lli_chained = 0 |
935 COH901318_CX_CTRL_TC_ENABLE |
936 COH901318_CX_CTRL_MASTER_MODE_M1RW |
937 COH901318_CX_CTRL_TCP_ENABLE |
938 COH901318_CX_CTRL_TC_IRQ_DISABLE |
939 COH901318_CX_CTRL_HSP_ENABLE |
940 COH901318_CX_CTRL_HSS_DISABLE |
941 COH901318_CX_CTRL_DDMA_LEGACY,
942 .param.ctrl_lli = 0 |
943 COH901318_CX_CTRL_TC_ENABLE |
944 COH901318_CX_CTRL_MASTER_MODE_M1RW |
945 COH901318_CX_CTRL_TCP_ENABLE |
946 COH901318_CX_CTRL_TC_IRQ_ENABLE |
947 COH901318_CX_CTRL_HSP_ENABLE |
948 COH901318_CX_CTRL_HSS_DISABLE |
949 COH901318_CX_CTRL_DDMA_LEGACY,
950 .param.ctrl_lli_last = 0 |
951 COH901318_CX_CTRL_TC_ENABLE |
952 COH901318_CX_CTRL_MASTER_MODE_M1RW |
953 COH901318_CX_CTRL_TCP_ENABLE |
954 COH901318_CX_CTRL_TC_IRQ_ENABLE |
955 COH901318_CX_CTRL_HSP_ENABLE |
956 COH901318_CX_CTRL_HSS_DISABLE |
957 COH901318_CX_CTRL_DDMA_LEGACY,
960 .number = U300_DMA_UART0_RX,
963 .param.config = COH901318_CX_CFG_CH_DISABLE |
964 COH901318_CX_CFG_LCR_DISABLE |
965 COH901318_CX_CFG_TC_IRQ_ENABLE |
966 COH901318_CX_CFG_BE_IRQ_ENABLE,
967 .param.ctrl_lli_chained = 0 |
968 COH901318_CX_CTRL_TC_ENABLE |
969 COH901318_CX_CTRL_MASTER_MODE_M1RW |
970 COH901318_CX_CTRL_TCP_ENABLE |
971 COH901318_CX_CTRL_TC_IRQ_DISABLE |
972 COH901318_CX_CTRL_HSP_ENABLE |
973 COH901318_CX_CTRL_HSS_DISABLE |
974 COH901318_CX_CTRL_DDMA_LEGACY,
975 .param.ctrl_lli = 0 |
976 COH901318_CX_CTRL_TC_ENABLE |
977 COH901318_CX_CTRL_MASTER_MODE_M1RW |
978 COH901318_CX_CTRL_TCP_ENABLE |
979 COH901318_CX_CTRL_TC_IRQ_ENABLE |
980 COH901318_CX_CTRL_HSP_ENABLE |
981 COH901318_CX_CTRL_HSS_DISABLE |
982 COH901318_CX_CTRL_DDMA_LEGACY,
983 .param.ctrl_lli_last = 0 |
984 COH901318_CX_CTRL_TC_ENABLE |
985 COH901318_CX_CTRL_MASTER_MODE_M1RW |
986 COH901318_CX_CTRL_TCP_ENABLE |
987 COH901318_CX_CTRL_TC_IRQ_ENABLE |
988 COH901318_CX_CTRL_HSP_ENABLE |
989 COH901318_CX_CTRL_HSS_DISABLE |
990 COH901318_CX_CTRL_DDMA_LEGACY,
993 .number = U300_DMA_APEX_TX,
998 .number = U300_DMA_APEX_RX,
1003 .number = U300_DMA_PCM_I2S0_TX,
1004 .name = "PCM I2S0 TX",
1006 .dev_addr = U300_PCM_I2S0_BASE + 0x14,
1007 .param.config = COH901318_CX_CFG_CH_DISABLE |
1008 COH901318_CX_CFG_LCR_DISABLE |
1009 COH901318_CX_CFG_TC_IRQ_ENABLE |
1010 COH901318_CX_CFG_BE_IRQ_ENABLE,
1011 .param.ctrl_lli_chained = 0 |
1012 COH901318_CX_CTRL_TC_ENABLE |
1013 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1014 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1015 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
1016 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1017 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
1018 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1019 COH901318_CX_CTRL_TCP_DISABLE |
1020 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1021 COH901318_CX_CTRL_HSP_ENABLE |
1022 COH901318_CX_CTRL_HSS_DISABLE |
1023 COH901318_CX_CTRL_DDMA_LEGACY |
1024 COH901318_CX_CTRL_PRDD_SOURCE,
1025 .param.ctrl_lli = 0 |
1026 COH901318_CX_CTRL_TC_ENABLE |
1027 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1028 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1029 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
1030 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1031 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
1032 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1033 COH901318_CX_CTRL_TCP_ENABLE |
1034 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1035 COH901318_CX_CTRL_HSP_ENABLE |
1036 COH901318_CX_CTRL_HSS_DISABLE |
1037 COH901318_CX_CTRL_DDMA_LEGACY |
1038 COH901318_CX_CTRL_PRDD_SOURCE,
1039 .param.ctrl_lli_last = 0 |
1040 COH901318_CX_CTRL_TC_ENABLE |
1041 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1042 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1043 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
1044 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1045 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
1046 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1047 COH901318_CX_CTRL_TCP_ENABLE |
1048 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1049 COH901318_CX_CTRL_HSP_ENABLE |
1050 COH901318_CX_CTRL_HSS_DISABLE |
1051 COH901318_CX_CTRL_DDMA_LEGACY |
1052 COH901318_CX_CTRL_PRDD_SOURCE,
1055 .number = U300_DMA_PCM_I2S0_RX,
1056 .name = "PCM I2S0 RX",
1058 .dev_addr = U300_PCM_I2S0_BASE + 0x10,
1059 .param.config = COH901318_CX_CFG_CH_DISABLE |
1060 COH901318_CX_CFG_LCR_DISABLE |
1061 COH901318_CX_CFG_TC_IRQ_ENABLE |
1062 COH901318_CX_CFG_BE_IRQ_ENABLE,
1063 .param.ctrl_lli_chained = 0 |
1064 COH901318_CX_CTRL_TC_ENABLE |
1065 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1066 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1067 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
1068 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1069 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
1070 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1071 COH901318_CX_CTRL_TCP_DISABLE |
1072 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1073 COH901318_CX_CTRL_HSP_ENABLE |
1074 COH901318_CX_CTRL_HSS_DISABLE |
1075 COH901318_CX_CTRL_DDMA_LEGACY |
1076 COH901318_CX_CTRL_PRDD_DEST,
1077 .param.ctrl_lli = 0 |
1078 COH901318_CX_CTRL_TC_ENABLE |
1079 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1080 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1081 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
1082 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1083 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
1084 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1085 COH901318_CX_CTRL_TCP_ENABLE |
1086 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1087 COH901318_CX_CTRL_HSP_ENABLE |
1088 COH901318_CX_CTRL_HSS_DISABLE |
1089 COH901318_CX_CTRL_DDMA_LEGACY |
1090 COH901318_CX_CTRL_PRDD_DEST,
1091 .param.ctrl_lli_last = 0 |
1092 COH901318_CX_CTRL_TC_ENABLE |
1093 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1094 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1095 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
1096 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1097 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
1098 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1099 COH901318_CX_CTRL_TCP_ENABLE |
1100 COH901318_CX_CTRL_TC_IRQ_ENABLE |
1101 COH901318_CX_CTRL_HSP_ENABLE |
1102 COH901318_CX_CTRL_HSS_DISABLE |
1103 COH901318_CX_CTRL_DDMA_LEGACY |
1104 COH901318_CX_CTRL_PRDD_DEST,
1107 .number = U300_DMA_PCM_I2S1_TX,
1108 .name = "PCM I2S1 TX",
1110 .dev_addr = U300_PCM_I2S1_BASE + 0x14,
1111 .param.config = COH901318_CX_CFG_CH_DISABLE |
1112 COH901318_CX_CFG_LCR_DISABLE |
1113 COH901318_CX_CFG_TC_IRQ_ENABLE |
1114 COH901318_CX_CFG_BE_IRQ_ENABLE,
1115 .param.ctrl_lli_chained = 0 |
1116 COH901318_CX_CTRL_TC_ENABLE |
1117 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1118 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1119 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
1120 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1121 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
1122 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1123 COH901318_CX_CTRL_TCP_DISABLE |
1124 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1125 COH901318_CX_CTRL_HSP_ENABLE |
1126 COH901318_CX_CTRL_HSS_DISABLE |
1127 COH901318_CX_CTRL_DDMA_LEGACY |
1128 COH901318_CX_CTRL_PRDD_SOURCE,
1129 .param.ctrl_lli = 0 |
1130 COH901318_CX_CTRL_TC_ENABLE |
1131 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1132 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1133 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
1134 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1135 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
1136 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1137 COH901318_CX_CTRL_TCP_ENABLE |
1138 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1139 COH901318_CX_CTRL_HSP_ENABLE |
1140 COH901318_CX_CTRL_HSS_DISABLE |
1141 COH901318_CX_CTRL_DDMA_LEGACY |
1142 COH901318_CX_CTRL_PRDD_SOURCE,
1143 .param.ctrl_lli_last = 0 |
1144 COH901318_CX_CTRL_TC_ENABLE |
1145 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1146 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1147 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
1148 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1149 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
1150 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1151 COH901318_CX_CTRL_TCP_ENABLE |
1152 COH901318_CX_CTRL_TC_IRQ_ENABLE |
1153 COH901318_CX_CTRL_HSP_ENABLE |
1154 COH901318_CX_CTRL_HSS_DISABLE |
1155 COH901318_CX_CTRL_DDMA_LEGACY |
1156 COH901318_CX_CTRL_PRDD_SOURCE,
1159 .number = U300_DMA_PCM_I2S1_RX,
1160 .name = "PCM I2S1 RX",
1162 .dev_addr = U300_PCM_I2S1_BASE + 0x10,
1163 .param.config = COH901318_CX_CFG_CH_DISABLE |
1164 COH901318_CX_CFG_LCR_DISABLE |
1165 COH901318_CX_CFG_TC_IRQ_ENABLE |
1166 COH901318_CX_CFG_BE_IRQ_ENABLE,
1167 .param.ctrl_lli_chained = 0 |
1168 COH901318_CX_CTRL_TC_ENABLE |
1169 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1170 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1171 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
1172 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1173 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
1174 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1175 COH901318_CX_CTRL_TCP_DISABLE |
1176 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1177 COH901318_CX_CTRL_HSP_ENABLE |
1178 COH901318_CX_CTRL_HSS_DISABLE |
1179 COH901318_CX_CTRL_DDMA_LEGACY |
1180 COH901318_CX_CTRL_PRDD_DEST,
1181 .param.ctrl_lli = 0 |
1182 COH901318_CX_CTRL_TC_ENABLE |
1183 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1184 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1185 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
1186 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1187 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
1188 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1189 COH901318_CX_CTRL_TCP_ENABLE |
1190 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1191 COH901318_CX_CTRL_HSP_ENABLE |
1192 COH901318_CX_CTRL_HSS_DISABLE |
1193 COH901318_CX_CTRL_DDMA_LEGACY |
1194 COH901318_CX_CTRL_PRDD_DEST,
1195 .param.ctrl_lli_last = 0 |
1196 COH901318_CX_CTRL_TC_ENABLE |
1197 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1198 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1199 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
1200 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1201 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
1202 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1203 COH901318_CX_CTRL_TCP_ENABLE |
1204 COH901318_CX_CTRL_TC_IRQ_ENABLE |
1205 COH901318_CX_CTRL_HSP_ENABLE |
1206 COH901318_CX_CTRL_HSS_DISABLE |
1207 COH901318_CX_CTRL_DDMA_LEGACY |
1208 COH901318_CX_CTRL_PRDD_DEST,
1211 .number = U300_DMA_XGAM_CDI,
1216 .number = U300_DMA_XGAM_PDI,
1221 * Don't set up device address, burst count or size of src
1222 * or dst bus for this peripheral - handled by PrimeCell
1226 .number = U300_DMA_SPI_TX,
1229 .param.config = COH901318_CX_CFG_CH_DISABLE |
1230 COH901318_CX_CFG_LCR_DISABLE |
1231 COH901318_CX_CFG_TC_IRQ_ENABLE |
1232 COH901318_CX_CFG_BE_IRQ_ENABLE,
1233 .param.ctrl_lli_chained = 0 |
1234 COH901318_CX_CTRL_TC_ENABLE |
1235 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1236 COH901318_CX_CTRL_TCP_DISABLE |
1237 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1238 COH901318_CX_CTRL_HSP_ENABLE |
1239 COH901318_CX_CTRL_HSS_DISABLE |
1240 COH901318_CX_CTRL_DDMA_LEGACY,
1241 .param.ctrl_lli = 0 |
1242 COH901318_CX_CTRL_TC_ENABLE |
1243 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1244 COH901318_CX_CTRL_TCP_DISABLE |
1245 COH901318_CX_CTRL_TC_IRQ_ENABLE |
1246 COH901318_CX_CTRL_HSP_ENABLE |
1247 COH901318_CX_CTRL_HSS_DISABLE |
1248 COH901318_CX_CTRL_DDMA_LEGACY,
1249 .param.ctrl_lli_last = 0 |
1250 COH901318_CX_CTRL_TC_ENABLE |
1251 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1252 COH901318_CX_CTRL_TCP_DISABLE |
1253 COH901318_CX_CTRL_TC_IRQ_ENABLE |
1254 COH901318_CX_CTRL_HSP_ENABLE |
1255 COH901318_CX_CTRL_HSS_DISABLE |
1256 COH901318_CX_CTRL_DDMA_LEGACY,
1259 .number = U300_DMA_SPI_RX,
1262 .param.config = COH901318_CX_CFG_CH_DISABLE |
1263 COH901318_CX_CFG_LCR_DISABLE |
1264 COH901318_CX_CFG_TC_IRQ_ENABLE |
1265 COH901318_CX_CFG_BE_IRQ_ENABLE,
1266 .param.ctrl_lli_chained = 0 |
1267 COH901318_CX_CTRL_TC_ENABLE |
1268 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1269 COH901318_CX_CTRL_TCP_DISABLE |
1270 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1271 COH901318_CX_CTRL_HSP_ENABLE |
1272 COH901318_CX_CTRL_HSS_DISABLE |
1273 COH901318_CX_CTRL_DDMA_LEGACY,
1274 .param.ctrl_lli = 0 |
1275 COH901318_CX_CTRL_TC_ENABLE |
1276 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1277 COH901318_CX_CTRL_TCP_DISABLE |
1278 COH901318_CX_CTRL_TC_IRQ_ENABLE |
1279 COH901318_CX_CTRL_HSP_ENABLE |
1280 COH901318_CX_CTRL_HSS_DISABLE |
1281 COH901318_CX_CTRL_DDMA_LEGACY,
1282 .param.ctrl_lli_last = 0 |
1283 COH901318_CX_CTRL_TC_ENABLE |
1284 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1285 COH901318_CX_CTRL_TCP_DISABLE |
1286 COH901318_CX_CTRL_TC_IRQ_ENABLE |
1287 COH901318_CX_CTRL_HSP_ENABLE |
1288 COH901318_CX_CTRL_HSS_DISABLE |
1289 COH901318_CX_CTRL_DDMA_LEGACY,
1293 .number = U300_DMA_GENERAL_PURPOSE_0,
1294 .name = "GENERAL 00",
1297 .param.config = flags_memcpy_config,
1298 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1299 .param.ctrl_lli = flags_memcpy_lli,
1300 .param.ctrl_lli_last = flags_memcpy_lli_last,
1303 .number = U300_DMA_GENERAL_PURPOSE_1,
1304 .name = "GENERAL 01",
1307 .param.config = flags_memcpy_config,
1308 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1309 .param.ctrl_lli = flags_memcpy_lli,
1310 .param.ctrl_lli_last = flags_memcpy_lli_last,
1313 .number = U300_DMA_GENERAL_PURPOSE_2,
1314 .name = "GENERAL 02",
1317 .param.config = flags_memcpy_config,
1318 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1319 .param.ctrl_lli = flags_memcpy_lli,
1320 .param.ctrl_lli_last = flags_memcpy_lli_last,
1323 .number = U300_DMA_GENERAL_PURPOSE_3,
1324 .name = "GENERAL 03",
1327 .param.config = flags_memcpy_config,
1328 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1329 .param.ctrl_lli = flags_memcpy_lli,
1330 .param.ctrl_lli_last = flags_memcpy_lli_last,
1333 .number = U300_DMA_GENERAL_PURPOSE_4,
1334 .name = "GENERAL 04",
1337 .param.config = flags_memcpy_config,
1338 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1339 .param.ctrl_lli = flags_memcpy_lli,
1340 .param.ctrl_lli_last = flags_memcpy_lli_last,
1343 .number = U300_DMA_GENERAL_PURPOSE_5,
1344 .name = "GENERAL 05",
1347 .param.config = flags_memcpy_config,
1348 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1349 .param.ctrl_lli = flags_memcpy_lli,
1350 .param.ctrl_lli_last = flags_memcpy_lli_last,
1353 .number = U300_DMA_GENERAL_PURPOSE_6,
1354 .name = "GENERAL 06",
1357 .param.config = flags_memcpy_config,
1358 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1359 .param.ctrl_lli = flags_memcpy_lli,
1360 .param.ctrl_lli_last = flags_memcpy_lli_last,
1363 .number = U300_DMA_GENERAL_PURPOSE_7,
1364 .name = "GENERAL 07",
1367 .param.config = flags_memcpy_config,
1368 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1369 .param.ctrl_lli = flags_memcpy_lli,
1370 .param.ctrl_lli_last = flags_memcpy_lli_last,
1373 .number = U300_DMA_GENERAL_PURPOSE_8,
1374 .name = "GENERAL 08",
1377 .param.config = flags_memcpy_config,
1378 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1379 .param.ctrl_lli = flags_memcpy_lli,
1380 .param.ctrl_lli_last = flags_memcpy_lli_last,
1383 .number = U300_DMA_UART1_TX,
1388 .number = U300_DMA_UART1_RX,
1395 static struct coh901318_platform coh901318_platform = {
1396 .chans_slave = dma_slave_channels,
1397 .chans_memcpy = dma_memcpy_channels,
1398 .access_memory_state = coh901318_access_memory_state,
1399 .chan_conf = chan_config,
1400 .max_channels = U300_DMA_CHANNELS,
1403 static struct resource pinctrl_resources[] = {
1405 .start = U300_SYSCON_BASE,
1406 .end = U300_SYSCON_BASE + SZ_4K - 1,
1407 .flags = IORESOURCE_MEM,
1411 static struct platform_device wdog_device = {
1412 .name = "coh901327_wdog",
1414 .num_resources = ARRAY_SIZE(wdog_resources),
1415 .resource = wdog_resources,
1418 static struct platform_device i2c0_device = {
1421 .num_resources = ARRAY_SIZE(i2c0_resources),
1422 .resource = i2c0_resources,
1425 static struct platform_device i2c1_device = {
1428 .num_resources = ARRAY_SIZE(i2c1_resources),
1429 .resource = i2c1_resources,
1432 static struct platform_device pinctrl_device = {
1433 .name = "pinctrl-u300",
1435 .num_resources = ARRAY_SIZE(pinctrl_resources),
1436 .resource = pinctrl_resources,
1440 * The different variants have a few different versions of the
1441 * GPIO block, with different number of ports.
1443 static struct u300_gpio_platform u300_gpio_plat = {
1448 static struct platform_device gpio_device = {
1449 .name = "u300-gpio",
1451 .num_resources = ARRAY_SIZE(gpio_resources),
1452 .resource = gpio_resources,
1454 .platform_data = &u300_gpio_plat,
1458 static struct platform_device keypad_device = {
1461 .num_resources = ARRAY_SIZE(keypad_resources),
1462 .resource = keypad_resources,
1465 static struct platform_device rtc_device = {
1466 .name = "rtc-coh901331",
1468 .num_resources = ARRAY_SIZE(rtc_resources),
1469 .resource = rtc_resources,
1472 static struct mtd_partition u300_partitions[] = {
1474 .name = "bootrecords",
1481 .size = 8064 * SZ_1K,
1485 .offset = 8192 * SZ_1K,
1486 .size = 253952 * SZ_1K,
1490 static struct fsmc_nand_platform_data nand_platform_data = {
1491 .partitions = u300_partitions,
1492 .nr_partitions = ARRAY_SIZE(u300_partitions),
1493 .options = NAND_SKIP_BBTSCAN,
1494 .width = FSMC_NAND_BW8,
1495 .ale_off = PLAT_NAND_ALE,
1496 .cle_off = PLAT_NAND_CLE,
1499 static struct platform_device nand_device = {
1500 .name = "fsmc-nand",
1502 .resource = fsmc_resources,
1503 .num_resources = ARRAY_SIZE(fsmc_resources),
1505 .platform_data = &nand_platform_data,
1509 static struct platform_device dma_device = {
1510 .name = "coh901318",
1512 .resource = dma_resource,
1513 .num_resources = ARRAY_SIZE(dma_resource),
1515 .platform_data = &coh901318_platform,
1516 .coherent_dma_mask = ~0,
1520 static unsigned long pin_pullup_conf[] = {
1521 PIN_CONF_PACKED(PIN_CONFIG_BIAS_PULL_UP, 1),
1524 static unsigned long pin_highz_conf[] = {
1525 PIN_CONF_PACKED(PIN_CONFIG_BIAS_HIGH_IMPEDANCE, 0),
1528 /* Pin control settings */
1529 static struct pinctrl_map __initdata u300_pinmux_map[] = {
1530 /* anonymous maps for chip power and EMIFs */
1531 PIN_MAP_MUX_GROUP_HOG_DEFAULT("pinctrl-u300", NULL, "power"),
1532 PIN_MAP_MUX_GROUP_HOG_DEFAULT("pinctrl-u300", NULL, "emif0"),
1533 PIN_MAP_MUX_GROUP_HOG_DEFAULT("pinctrl-u300", NULL, "emif1"),
1534 /* per-device maps for MMC/SD, SPI and UART */
1535 PIN_MAP_MUX_GROUP_DEFAULT("mmci", "pinctrl-u300", NULL, "mmc0"),
1536 PIN_MAP_MUX_GROUP_DEFAULT("pl022", "pinctrl-u300", NULL, "spi0"),
1537 PIN_MAP_MUX_GROUP_DEFAULT("uart0", "pinctrl-u300", NULL, "uart0"),
1538 /* This pin is used for clock return rather than GPIO */
1539 PIN_MAP_CONFIGS_PIN_DEFAULT("mmci", "pinctrl-u300", "PIO APP GPIO 11",
1541 /* This pin is used for card detect */
1542 PIN_MAP_CONFIGS_PIN_DEFAULT("mmci", "pinctrl-u300", "PIO MS INS",
1546 struct u300_mux_hog {
1551 static struct u300_mux_hog u300_mux_hogs[] = {
1553 .dev = &uart0_device.dev,
1556 .dev = &mmcsd_device.dev,
1560 static int __init u300_pinctrl_fetch(void)
1564 for (i = 0; i < ARRAY_SIZE(u300_mux_hogs); i++) {
1567 p = pinctrl_get_select_default(u300_mux_hogs[i].dev);
1569 pr_err("u300: could not get pinmux hog for dev %s\n",
1570 dev_name(u300_mux_hogs[i].dev));
1573 u300_mux_hogs[i].p = p;
1577 subsys_initcall(u300_pinctrl_fetch);
1580 * Notice that AMBA devices are initialized before platform devices.
1583 static struct platform_device *platform_devs[] __initdata = {
1596 * Interrupts: the U300 platforms have two pl190 ARM PrimeCells connected
1597 * together so some interrupts are connected to the first one and some
1598 * to the second one.
1600 static void __init u300_init_irq(void)
1602 u32 mask[2] = {0, 0};
1606 /* initialize clocking early, we want to clock the INTCON */
1607 u300_clk_init(U300_SYSCON_VBASE);
1609 /* Bootstrap EMIF and SEMI clocks */
1610 clk = clk_get_sys("pl172", NULL);
1611 BUG_ON(IS_ERR(clk));
1612 clk_prepare_enable(clk);
1613 clk = clk_get_sys("semi", NULL);
1614 BUG_ON(IS_ERR(clk));
1615 clk_prepare_enable(clk);
1617 /* Clock the interrupt controller */
1618 clk = clk_get_sys("intcon", NULL);
1619 BUG_ON(IS_ERR(clk));
1620 clk_prepare_enable(clk);
1622 for (i = 0; i < U300_VIC_IRQS_END; i++)
1623 set_bit(i, (unsigned long *) &mask[0]);
1624 vic_init((void __iomem *) U300_INTCON0_VBASE, IRQ_U300_INTCON0_START,
1626 vic_init((void __iomem *) U300_INTCON1_VBASE, IRQ_U300_INTCON1_START,
1632 * U300 platforms peripheral handling
1640 * This is a list of the Digital Baseband chips used in the U300 platform.
1642 static struct db_chip db_chips[] __initdata = {
1669 .name = "DB3350 P1x",
1673 .name = "DB3350 P2x",
1676 .chipid = 0x0000, /* List terminator */
1681 static void __init u300_init_check_chip(void)
1685 struct db_chip *chip;
1686 const char *chipname;
1687 const char unknown[] = "UNKNOWN";
1689 /* Read out and print chip ID */
1690 val = readw(U300_SYSCON_VBASE + U300_SYSCON_CIDR);
1691 /* This is in funky bigendian order... */
1692 val = (val & 0xFFU) << 8 | (val >> 8);
1696 for ( ; chip->chipid; chip++) {
1697 if (chip->chipid == (val & 0xFF00U)) {
1698 chipname = chip->name;
1702 printk(KERN_INFO "Initializing U300 system on %s baseband chip " \
1703 "(chip ID 0x%04x)\n", chipname, val);
1705 if ((val & 0xFF00U) != 0xf000 && (val & 0xFF00U) != 0xf100) {
1706 printk(KERN_ERR "Platform configured for BS335 " \
1707 " with DB3350 but %s detected, expect problems!",
1713 * Some devices and their resources require reserved physical memory from
1714 * the end of the available RAM. This function traverses the list of devices
1715 * and assigns actual addresses to these.
1717 static void __init u300_assign_physmem(void)
1719 unsigned long curr_start = __pa(high_memory);
1722 for (i = 0; i < ARRAY_SIZE(platform_devs); i++) {
1723 for (j = 0; j < platform_devs[i]->num_resources; j++) {
1724 struct resource *const res =
1725 &platform_devs[i]->resource[j];
1727 if (IORESOURCE_MEM == res->flags &&
1729 res->start = curr_start;
1730 res->end += curr_start;
1731 curr_start += resource_size(res);
1733 printk(KERN_INFO "core.c: Mapping RAM " \
1734 "%#x-%#x to device %s:%s\n",
1735 res->start, res->end,
1736 platform_devs[i]->name, res->name);
1742 static void __init u300_init_machine(void)
1747 /* Check what platform we run and print some status information */
1748 u300_init_check_chip();
1750 /* Initialize SPI device with some board specifics */
1751 u300_spi_init(&pl022_device);
1753 /* Register the AMBA devices in the AMBA bus abstraction layer */
1754 for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
1755 struct amba_device *d = amba_devs[i];
1756 amba_device_register(d, &iomem_resource);
1759 u300_assign_physmem();
1761 /* Initialize pinmuxing */
1762 pinctrl_register_mappings(u300_pinmux_map,
1763 ARRAY_SIZE(u300_pinmux_map));
1765 /* Register subdevices on the I2C buses */
1766 u300_i2c_register_board_devices();
1768 /* Register the platform devices */
1769 platform_add_devices(platform_devs, ARRAY_SIZE(platform_devs));
1771 /* Register subdevices on the SPI bus */
1772 u300_spi_register_board_devices();
1774 /* Enable SEMI self refresh */
1775 val = readw(U300_SYSCON_VBASE + U300_SYSCON_SMCR) |
1776 U300_SYSCON_SMCR_SEMI_SREFREQ_ENABLE;
1777 writew(val, U300_SYSCON_VBASE + U300_SYSCON_SMCR);
1780 /* Forward declare this function from the watchdog */
1781 void coh901327_watchdog_reset(void);
1783 static void u300_restart(char mode, const char *cmd)
1788 #ifdef CONFIG_COH901327_WATCHDOG
1789 coh901327_watchdog_reset();
1796 /* Wait for system do die/reset. */
1800 MACHINE_START(U300, "Ericsson AB U335 S335/B335 Prototype Board")
1801 /* Maintainer: Linus Walleij <linus.walleij@stericsson.com> */
1802 .atag_offset = 0x100,
1803 .map_io = u300_map_io,
1805 .init_irq = u300_init_irq,
1806 .handle_irq = vic_handle_irq,
1807 .timer = &u300_timer,
1808 .init_machine = u300_init_machine,
1809 .restart = u300_restart,