3 * arch/arm/mach-u300/core.c
6 * Copyright (C) 2007-2010 ST-Ericsson SA
7 * License terms: GNU General Public License (GPL) version 2
8 * Core platform support, IRQ handling and device definitions.
9 * Author: Linus Walleij <linus.walleij@stericsson.com>
11 #include <linux/kernel.h>
12 #include <linux/init.h>
13 #include <linux/spinlock.h>
14 #include <linux/interrupt.h>
15 #include <linux/bitops.h>
16 #include <linux/device.h>
18 #include <linux/termios.h>
19 #include <linux/dmaengine.h>
20 #include <linux/amba/bus.h>
21 #include <linux/amba/serial.h>
22 #include <linux/platform_device.h>
23 #include <linux/gpio.h>
24 #include <linux/clk.h>
25 #include <linux/err.h>
26 #include <linux/mtd/nand.h>
27 #include <linux/mtd/fsmc.h>
28 #include <linux/pinctrl/machine.h>
29 #include <linux/pinctrl/pinmux.h>
30 #include <linux/dma-mapping.h>
32 #include <asm/types.h>
33 #include <asm/setup.h>
34 #include <asm/memory.h>
35 #include <asm/hardware/vic.h>
36 #include <asm/mach/map.h>
37 #include <asm/mach/irq.h>
39 #include <mach/coh901318.h>
40 #include <mach/hardware.h>
41 #include <mach/syscon.h>
42 #include <mach/dma_channels.h>
43 #include <mach/gpio-u300.h>
51 * Static I/O mappings that are needed for booting the U300 platforms. The
52 * only things we need are the areas where we find the timer, syscon and
53 * intcon, since the remaining device drivers will map their own memory
54 * physical to virtual as the need arise.
56 static struct map_desc u300_io_desc[] __initdata = {
58 .virtual = U300_SLOW_PER_VIRT_BASE,
59 .pfn = __phys_to_pfn(U300_SLOW_PER_PHYS_BASE),
64 .virtual = U300_AHB_PER_VIRT_BASE,
65 .pfn = __phys_to_pfn(U300_AHB_PER_PHYS_BASE),
70 .virtual = U300_FAST_PER_VIRT_BASE,
71 .pfn = __phys_to_pfn(U300_FAST_PER_PHYS_BASE),
76 .virtual = 0xffff2000, /* TCM memory */
77 .pfn = __phys_to_pfn(0xffff2000),
83 * This overlaps with the IRQ vectors etc at 0xffff0000, so these
84 * may have to be moved to 0x00000000 in order to use the ROM.
88 .virtual = U300_BOOTROM_VIRT_BASE,
89 .pfn = __phys_to_pfn(U300_BOOTROM_PHYS_BASE),
96 void __init u300_map_io(void)
98 iotable_init(u300_io_desc, ARRAY_SIZE(u300_io_desc));
99 /* We enable a real big DMA buffer if need be. */
100 init_consistent_dma_size(SZ_4M);
104 * Declaration of devices found on the U300 board and
105 * their respective memory locations.
108 static struct amba_pl011_data uart0_plat_data = {
109 #ifdef CONFIG_COH901318
110 .dma_filter = coh901318_filter_id,
111 .dma_rx_param = (void *) U300_DMA_UART0_RX,
112 .dma_tx_param = (void *) U300_DMA_UART0_TX,
116 static struct amba_device uart0_device = {
118 .coherent_dma_mask = ~0,
119 .init_name = "uart0", /* Slow device at 0x3000 offset */
120 .platform_data = &uart0_plat_data,
123 .start = U300_UART0_BASE,
124 .end = U300_UART0_BASE + SZ_4K - 1,
125 .flags = IORESOURCE_MEM,
127 .irq = { IRQ_U300_UART0, NO_IRQ },
130 /* The U335 have an additional UART1 on the APP CPU */
131 #ifdef CONFIG_MACH_U300_BS335
132 static struct amba_pl011_data uart1_plat_data = {
133 #ifdef CONFIG_COH901318
134 .dma_filter = coh901318_filter_id,
135 .dma_rx_param = (void *) U300_DMA_UART1_RX,
136 .dma_tx_param = (void *) U300_DMA_UART1_TX,
140 static struct amba_device uart1_device = {
142 .coherent_dma_mask = ~0,
143 .init_name = "uart1", /* Fast device at 0x7000 offset */
144 .platform_data = &uart1_plat_data,
147 .start = U300_UART1_BASE,
148 .end = U300_UART1_BASE + SZ_4K - 1,
149 .flags = IORESOURCE_MEM,
151 .irq = { IRQ_U300_UART1, NO_IRQ },
155 static struct amba_device pl172_device = {
157 .init_name = "pl172", /* AHB device at 0x4000 offset */
158 .platform_data = NULL,
161 .start = U300_EMIF_CFG_BASE,
162 .end = U300_EMIF_CFG_BASE + SZ_4K - 1,
163 .flags = IORESOURCE_MEM,
169 * Everything within this next ifdef deals with external devices connected to
172 static struct amba_device pl022_device = {
174 .coherent_dma_mask = ~0,
175 .init_name = "pl022", /* Fast device at 0x6000 offset */
178 .start = U300_SPI_BASE,
179 .end = U300_SPI_BASE + SZ_4K - 1,
180 .flags = IORESOURCE_MEM,
182 .irq = {IRQ_U300_SPI, NO_IRQ },
184 * This device has a DMA channel but the Linux driver does not use
189 static struct amba_device mmcsd_device = {
191 .init_name = "mmci", /* Fast device at 0x1000 offset */
192 .platform_data = NULL, /* Added later */
195 .start = U300_MMCSD_BASE,
196 .end = U300_MMCSD_BASE + SZ_4K - 1,
197 .flags = IORESOURCE_MEM,
199 .irq = {IRQ_U300_MMCSD_MCIINTR0, IRQ_U300_MMCSD_MCIINTR1 },
201 * This device has a DMA channel but the Linux driver does not use
207 * The order of device declaration may be important, since some devices
208 * have dependencies on other devices being initialized first.
210 static struct amba_device *amba_devs[] __initdata = {
212 #ifdef CONFIG_MACH_U300_BS335
220 /* Here follows a list of all hw resources that the platform devices
221 * allocate. Note, clock dependencies are not included
224 static struct resource gpio_resources[] = {
226 .start = U300_GPIO_BASE,
227 .end = (U300_GPIO_BASE + SZ_4K - 1),
228 .flags = IORESOURCE_MEM,
232 .start = IRQ_U300_GPIO_PORT0,
233 .end = IRQ_U300_GPIO_PORT0,
234 .flags = IORESOURCE_IRQ,
238 .start = IRQ_U300_GPIO_PORT1,
239 .end = IRQ_U300_GPIO_PORT1,
240 .flags = IORESOURCE_IRQ,
244 .start = IRQ_U300_GPIO_PORT2,
245 .end = IRQ_U300_GPIO_PORT2,
246 .flags = IORESOURCE_IRQ,
248 #if defined(CONFIG_MACH_U300_BS365) || defined(CONFIG_MACH_U300_BS335)
251 .start = IRQ_U300_GPIO_PORT3,
252 .end = IRQ_U300_GPIO_PORT3,
253 .flags = IORESOURCE_IRQ,
257 .start = IRQ_U300_GPIO_PORT4,
258 .end = IRQ_U300_GPIO_PORT4,
259 .flags = IORESOURCE_IRQ,
262 #ifdef CONFIG_MACH_U300_BS335
265 .start = IRQ_U300_GPIO_PORT5,
266 .end = IRQ_U300_GPIO_PORT5,
267 .flags = IORESOURCE_IRQ,
271 .start = IRQ_U300_GPIO_PORT6,
272 .end = IRQ_U300_GPIO_PORT6,
273 .flags = IORESOURCE_IRQ,
275 #endif /* CONFIG_MACH_U300_BS335 */
278 static struct resource keypad_resources[] = {
280 .start = U300_KEYPAD_BASE,
281 .end = U300_KEYPAD_BASE + SZ_4K - 1,
282 .flags = IORESOURCE_MEM,
285 .name = "coh901461-press",
286 .start = IRQ_U300_KEYPAD_KEYBF,
287 .end = IRQ_U300_KEYPAD_KEYBF,
288 .flags = IORESOURCE_IRQ,
291 .name = "coh901461-release",
292 .start = IRQ_U300_KEYPAD_KEYBR,
293 .end = IRQ_U300_KEYPAD_KEYBR,
294 .flags = IORESOURCE_IRQ,
298 static struct resource rtc_resources[] = {
300 .start = U300_RTC_BASE,
301 .end = U300_RTC_BASE + SZ_4K - 1,
302 .flags = IORESOURCE_MEM,
305 .start = IRQ_U300_RTC,
307 .flags = IORESOURCE_IRQ,
312 * Fsmc does have IRQs: #43 and #44 (NFIF and NFIF2)
313 * but these are not yet used by the driver.
315 static struct resource fsmc_resources[] = {
318 .start = U300_NAND_CS0_PHYS_BASE,
319 .end = U300_NAND_CS0_PHYS_BASE + SZ_16K - 1,
320 .flags = IORESOURCE_MEM,
324 .start = U300_NAND_IF_PHYS_BASE,
325 .end = U300_NAND_IF_PHYS_BASE + SZ_4K - 1,
326 .flags = IORESOURCE_MEM,
330 static struct resource i2c0_resources[] = {
332 .start = U300_I2C0_BASE,
333 .end = U300_I2C0_BASE + SZ_4K - 1,
334 .flags = IORESOURCE_MEM,
337 .start = IRQ_U300_I2C0,
338 .end = IRQ_U300_I2C0,
339 .flags = IORESOURCE_IRQ,
343 static struct resource i2c1_resources[] = {
345 .start = U300_I2C1_BASE,
346 .end = U300_I2C1_BASE + SZ_4K - 1,
347 .flags = IORESOURCE_MEM,
350 .start = IRQ_U300_I2C1,
351 .end = IRQ_U300_I2C1,
352 .flags = IORESOURCE_IRQ,
357 static struct resource wdog_resources[] = {
359 .start = U300_WDOG_BASE,
360 .end = U300_WDOG_BASE + SZ_4K - 1,
361 .flags = IORESOURCE_MEM,
364 .start = IRQ_U300_WDOG,
365 .end = IRQ_U300_WDOG,
366 .flags = IORESOURCE_IRQ,
370 /* TODO: These should be protected by suitable #ifdef's */
371 static struct resource ave_resources[] = {
373 .name = "AVE3e I/O Area",
374 .start = U300_VIDEOENC_BASE,
375 .end = U300_VIDEOENC_BASE + SZ_512K - 1,
376 .flags = IORESOURCE_MEM,
379 .name = "AVE3e IRQ0",
380 .start = IRQ_U300_VIDEO_ENC_0,
381 .end = IRQ_U300_VIDEO_ENC_0,
382 .flags = IORESOURCE_IRQ,
385 .name = "AVE3e IRQ1",
386 .start = IRQ_U300_VIDEO_ENC_1,
387 .end = IRQ_U300_VIDEO_ENC_1,
388 .flags = IORESOURCE_IRQ,
391 .name = "AVE3e Physmem Area",
392 .start = 0, /* 0 will be remapped to reserved memory */
394 .flags = IORESOURCE_MEM,
397 * The AVE3e requires two regions of 256MB that it considers
398 * "invisible". The hardware will not be able to access these
399 * addresses, so they should never point to system RAM.
402 .name = "AVE3e Reserved 0",
404 .end = 0xd0000000 + SZ_256M - 1,
405 .flags = IORESOURCE_MEM,
408 .name = "AVE3e Reserved 1",
410 .end = 0xe0000000 + SZ_256M - 1,
411 .flags = IORESOURCE_MEM,
415 static struct resource dma_resource[] = {
417 .start = U300_DMAC_BASE,
418 .end = U300_DMAC_BASE + PAGE_SIZE - 1,
419 .flags = IORESOURCE_MEM,
422 .start = IRQ_U300_DMA,
424 .flags = IORESOURCE_IRQ,
428 #ifdef CONFIG_MACH_U300_BS335
429 /* points out all dma slave channels.
430 * Syntax is [A1, B1, A2, B2, .... ,-1,-1]
431 * Select all channels from A to B, end of list is marked with -1,-1
433 static int dma_slave_channels[] = {
434 U300_DMA_MSL_TX_0, U300_DMA_SPI_RX,
435 U300_DMA_UART1_TX, U300_DMA_UART1_RX, -1, -1};
437 /* points out all dma memcpy channels. */
438 static int dma_memcpy_channels[] = {
439 U300_DMA_GENERAL_PURPOSE_0, U300_DMA_GENERAL_PURPOSE_8, -1, -1};
441 #else /* CONFIG_MACH_U300_BS335 */
443 static int dma_slave_channels[] = {U300_DMA_MSL_TX_0, U300_DMA_SPI_RX, -1, -1};
444 static int dma_memcpy_channels[] = {
445 U300_DMA_GENERAL_PURPOSE_0, U300_DMA_GENERAL_PURPOSE_10, -1, -1};
449 /** register dma for memory access
451 * active 1 means dma intends to access memory
452 * 0 means dma wont access memory
454 static void coh901318_access_memory_state(struct device *dev, bool active)
458 #define flags_memcpy_config (COH901318_CX_CFG_CH_DISABLE | \
459 COH901318_CX_CFG_RM_MEMORY_TO_MEMORY | \
460 COH901318_CX_CFG_LCR_DISABLE | \
461 COH901318_CX_CFG_TC_IRQ_ENABLE | \
462 COH901318_CX_CFG_BE_IRQ_ENABLE)
463 #define flags_memcpy_lli_chained (COH901318_CX_CTRL_TC_ENABLE | \
464 COH901318_CX_CTRL_BURST_COUNT_32_BYTES | \
465 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | \
466 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE | \
467 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | \
468 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE | \
469 COH901318_CX_CTRL_MASTER_MODE_M1RW | \
470 COH901318_CX_CTRL_TCP_DISABLE | \
471 COH901318_CX_CTRL_TC_IRQ_DISABLE | \
472 COH901318_CX_CTRL_HSP_DISABLE | \
473 COH901318_CX_CTRL_HSS_DISABLE | \
474 COH901318_CX_CTRL_DDMA_LEGACY | \
475 COH901318_CX_CTRL_PRDD_SOURCE)
476 #define flags_memcpy_lli (COH901318_CX_CTRL_TC_ENABLE | \
477 COH901318_CX_CTRL_BURST_COUNT_32_BYTES | \
478 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | \
479 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE | \
480 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | \
481 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE | \
482 COH901318_CX_CTRL_MASTER_MODE_M1RW | \
483 COH901318_CX_CTRL_TCP_DISABLE | \
484 COH901318_CX_CTRL_TC_IRQ_DISABLE | \
485 COH901318_CX_CTRL_HSP_DISABLE | \
486 COH901318_CX_CTRL_HSS_DISABLE | \
487 COH901318_CX_CTRL_DDMA_LEGACY | \
488 COH901318_CX_CTRL_PRDD_SOURCE)
489 #define flags_memcpy_lli_last (COH901318_CX_CTRL_TC_ENABLE | \
490 COH901318_CX_CTRL_BURST_COUNT_32_BYTES | \
491 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | \
492 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE | \
493 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | \
494 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE | \
495 COH901318_CX_CTRL_MASTER_MODE_M1RW | \
496 COH901318_CX_CTRL_TCP_DISABLE | \
497 COH901318_CX_CTRL_TC_IRQ_ENABLE | \
498 COH901318_CX_CTRL_HSP_DISABLE | \
499 COH901318_CX_CTRL_HSS_DISABLE | \
500 COH901318_CX_CTRL_DDMA_LEGACY | \
501 COH901318_CX_CTRL_PRDD_SOURCE)
503 const struct coh_dma_channel chan_config[U300_DMA_CHANNELS] = {
505 .number = U300_DMA_MSL_TX_0,
508 .dev_addr = U300_MSL_BASE + 0 * 0x40 + 0x20,
511 .number = U300_DMA_MSL_TX_1,
514 .dev_addr = U300_MSL_BASE + 1 * 0x40 + 0x20,
515 .param.config = COH901318_CX_CFG_CH_DISABLE |
516 COH901318_CX_CFG_LCR_DISABLE |
517 COH901318_CX_CFG_TC_IRQ_ENABLE |
518 COH901318_CX_CFG_BE_IRQ_ENABLE,
519 .param.ctrl_lli_chained = 0 |
520 COH901318_CX_CTRL_TC_ENABLE |
521 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
522 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
523 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
524 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
525 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
526 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
527 COH901318_CX_CTRL_TCP_DISABLE |
528 COH901318_CX_CTRL_TC_IRQ_DISABLE |
529 COH901318_CX_CTRL_HSP_ENABLE |
530 COH901318_CX_CTRL_HSS_DISABLE |
531 COH901318_CX_CTRL_DDMA_LEGACY |
532 COH901318_CX_CTRL_PRDD_SOURCE,
533 .param.ctrl_lli = 0 |
534 COH901318_CX_CTRL_TC_ENABLE |
535 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
536 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
537 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
538 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
539 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
540 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
541 COH901318_CX_CTRL_TCP_ENABLE |
542 COH901318_CX_CTRL_TC_IRQ_DISABLE |
543 COH901318_CX_CTRL_HSP_ENABLE |
544 COH901318_CX_CTRL_HSS_DISABLE |
545 COH901318_CX_CTRL_DDMA_LEGACY |
546 COH901318_CX_CTRL_PRDD_SOURCE,
547 .param.ctrl_lli_last = 0 |
548 COH901318_CX_CTRL_TC_ENABLE |
549 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
550 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
551 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
552 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
553 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
554 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
555 COH901318_CX_CTRL_TCP_ENABLE |
556 COH901318_CX_CTRL_TC_IRQ_ENABLE |
557 COH901318_CX_CTRL_HSP_ENABLE |
558 COH901318_CX_CTRL_HSS_DISABLE |
559 COH901318_CX_CTRL_DDMA_LEGACY |
560 COH901318_CX_CTRL_PRDD_SOURCE,
563 .number = U300_DMA_MSL_TX_2,
566 .dev_addr = U300_MSL_BASE + 2 * 0x40 + 0x20,
567 .param.config = COH901318_CX_CFG_CH_DISABLE |
568 COH901318_CX_CFG_LCR_DISABLE |
569 COH901318_CX_CFG_TC_IRQ_ENABLE |
570 COH901318_CX_CFG_BE_IRQ_ENABLE,
571 .param.ctrl_lli_chained = 0 |
572 COH901318_CX_CTRL_TC_ENABLE |
573 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
574 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
575 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
576 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
577 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
578 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
579 COH901318_CX_CTRL_TCP_DISABLE |
580 COH901318_CX_CTRL_TC_IRQ_DISABLE |
581 COH901318_CX_CTRL_HSP_ENABLE |
582 COH901318_CX_CTRL_HSS_DISABLE |
583 COH901318_CX_CTRL_DDMA_LEGACY |
584 COH901318_CX_CTRL_PRDD_SOURCE,
585 .param.ctrl_lli = 0 |
586 COH901318_CX_CTRL_TC_ENABLE |
587 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
588 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
589 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
590 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
591 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
592 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
593 COH901318_CX_CTRL_TCP_ENABLE |
594 COH901318_CX_CTRL_TC_IRQ_DISABLE |
595 COH901318_CX_CTRL_HSP_ENABLE |
596 COH901318_CX_CTRL_HSS_DISABLE |
597 COH901318_CX_CTRL_DDMA_LEGACY |
598 COH901318_CX_CTRL_PRDD_SOURCE,
599 .param.ctrl_lli_last = 0 |
600 COH901318_CX_CTRL_TC_ENABLE |
601 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
602 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
603 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
604 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
605 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
606 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
607 COH901318_CX_CTRL_TCP_ENABLE |
608 COH901318_CX_CTRL_TC_IRQ_ENABLE |
609 COH901318_CX_CTRL_HSP_ENABLE |
610 COH901318_CX_CTRL_HSS_DISABLE |
611 COH901318_CX_CTRL_DDMA_LEGACY |
612 COH901318_CX_CTRL_PRDD_SOURCE,
616 .number = U300_DMA_MSL_TX_3,
619 .dev_addr = U300_MSL_BASE + 3 * 0x40 + 0x20,
620 .param.config = COH901318_CX_CFG_CH_DISABLE |
621 COH901318_CX_CFG_LCR_DISABLE |
622 COH901318_CX_CFG_TC_IRQ_ENABLE |
623 COH901318_CX_CFG_BE_IRQ_ENABLE,
624 .param.ctrl_lli_chained = 0 |
625 COH901318_CX_CTRL_TC_ENABLE |
626 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
627 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
628 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
629 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
630 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
631 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
632 COH901318_CX_CTRL_TCP_DISABLE |
633 COH901318_CX_CTRL_TC_IRQ_DISABLE |
634 COH901318_CX_CTRL_HSP_ENABLE |
635 COH901318_CX_CTRL_HSS_DISABLE |
636 COH901318_CX_CTRL_DDMA_LEGACY |
637 COH901318_CX_CTRL_PRDD_SOURCE,
638 .param.ctrl_lli = 0 |
639 COH901318_CX_CTRL_TC_ENABLE |
640 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
641 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
642 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
643 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
644 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
645 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
646 COH901318_CX_CTRL_TCP_ENABLE |
647 COH901318_CX_CTRL_TC_IRQ_DISABLE |
648 COH901318_CX_CTRL_HSP_ENABLE |
649 COH901318_CX_CTRL_HSS_DISABLE |
650 COH901318_CX_CTRL_DDMA_LEGACY |
651 COH901318_CX_CTRL_PRDD_SOURCE,
652 .param.ctrl_lli_last = 0 |
653 COH901318_CX_CTRL_TC_ENABLE |
654 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
655 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
656 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
657 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
658 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
659 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
660 COH901318_CX_CTRL_TCP_ENABLE |
661 COH901318_CX_CTRL_TC_IRQ_ENABLE |
662 COH901318_CX_CTRL_HSP_ENABLE |
663 COH901318_CX_CTRL_HSS_DISABLE |
664 COH901318_CX_CTRL_DDMA_LEGACY |
665 COH901318_CX_CTRL_PRDD_SOURCE,
668 .number = U300_DMA_MSL_TX_4,
671 .dev_addr = U300_MSL_BASE + 4 * 0x40 + 0x20,
672 .param.config = COH901318_CX_CFG_CH_DISABLE |
673 COH901318_CX_CFG_LCR_DISABLE |
674 COH901318_CX_CFG_TC_IRQ_ENABLE |
675 COH901318_CX_CFG_BE_IRQ_ENABLE,
676 .param.ctrl_lli_chained = 0 |
677 COH901318_CX_CTRL_TC_ENABLE |
678 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
679 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
680 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
681 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
682 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
683 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
684 COH901318_CX_CTRL_TCP_DISABLE |
685 COH901318_CX_CTRL_TC_IRQ_DISABLE |
686 COH901318_CX_CTRL_HSP_ENABLE |
687 COH901318_CX_CTRL_HSS_DISABLE |
688 COH901318_CX_CTRL_DDMA_LEGACY |
689 COH901318_CX_CTRL_PRDD_SOURCE,
690 .param.ctrl_lli = 0 |
691 COH901318_CX_CTRL_TC_ENABLE |
692 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
693 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
694 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
695 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
696 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
697 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
698 COH901318_CX_CTRL_TCP_ENABLE |
699 COH901318_CX_CTRL_TC_IRQ_DISABLE |
700 COH901318_CX_CTRL_HSP_ENABLE |
701 COH901318_CX_CTRL_HSS_DISABLE |
702 COH901318_CX_CTRL_DDMA_LEGACY |
703 COH901318_CX_CTRL_PRDD_SOURCE,
704 .param.ctrl_lli_last = 0 |
705 COH901318_CX_CTRL_TC_ENABLE |
706 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
707 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
708 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
709 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
710 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
711 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
712 COH901318_CX_CTRL_TCP_ENABLE |
713 COH901318_CX_CTRL_TC_IRQ_ENABLE |
714 COH901318_CX_CTRL_HSP_ENABLE |
715 COH901318_CX_CTRL_HSS_DISABLE |
716 COH901318_CX_CTRL_DDMA_LEGACY |
717 COH901318_CX_CTRL_PRDD_SOURCE,
720 .number = U300_DMA_MSL_TX_5,
723 .dev_addr = U300_MSL_BASE + 5 * 0x40 + 0x20,
726 .number = U300_DMA_MSL_TX_6,
729 .dev_addr = U300_MSL_BASE + 6 * 0x40 + 0x20,
732 .number = U300_DMA_MSL_RX_0,
735 .dev_addr = U300_MSL_BASE + 0 * 0x40 + 0x220,
738 .number = U300_DMA_MSL_RX_1,
741 .dev_addr = U300_MSL_BASE + 1 * 0x40 + 0x220,
742 .param.config = COH901318_CX_CFG_CH_DISABLE |
743 COH901318_CX_CFG_LCR_DISABLE |
744 COH901318_CX_CFG_TC_IRQ_ENABLE |
745 COH901318_CX_CFG_BE_IRQ_ENABLE,
746 .param.ctrl_lli_chained = 0 |
747 COH901318_CX_CTRL_TC_ENABLE |
748 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
749 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
750 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
751 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
752 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
753 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
754 COH901318_CX_CTRL_TCP_DISABLE |
755 COH901318_CX_CTRL_TC_IRQ_DISABLE |
756 COH901318_CX_CTRL_HSP_ENABLE |
757 COH901318_CX_CTRL_HSS_DISABLE |
758 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
759 COH901318_CX_CTRL_PRDD_DEST,
761 .param.ctrl_lli_last = 0 |
762 COH901318_CX_CTRL_TC_ENABLE |
763 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
764 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
765 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
766 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
767 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
768 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
769 COH901318_CX_CTRL_TCP_DISABLE |
770 COH901318_CX_CTRL_TC_IRQ_ENABLE |
771 COH901318_CX_CTRL_HSP_ENABLE |
772 COH901318_CX_CTRL_HSS_DISABLE |
773 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
774 COH901318_CX_CTRL_PRDD_DEST,
777 .number = U300_DMA_MSL_RX_2,
780 .dev_addr = U300_MSL_BASE + 2 * 0x40 + 0x220,
781 .param.config = COH901318_CX_CFG_CH_DISABLE |
782 COH901318_CX_CFG_LCR_DISABLE |
783 COH901318_CX_CFG_TC_IRQ_ENABLE |
784 COH901318_CX_CFG_BE_IRQ_ENABLE,
785 .param.ctrl_lli_chained = 0 |
786 COH901318_CX_CTRL_TC_ENABLE |
787 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
788 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
789 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
790 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
791 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
792 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
793 COH901318_CX_CTRL_TCP_DISABLE |
794 COH901318_CX_CTRL_TC_IRQ_DISABLE |
795 COH901318_CX_CTRL_HSP_ENABLE |
796 COH901318_CX_CTRL_HSS_DISABLE |
797 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
798 COH901318_CX_CTRL_PRDD_DEST,
799 .param.ctrl_lli = 0 |
800 COH901318_CX_CTRL_TC_ENABLE |
801 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
802 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
803 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
804 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
805 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
806 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
807 COH901318_CX_CTRL_TCP_DISABLE |
808 COH901318_CX_CTRL_TC_IRQ_ENABLE |
809 COH901318_CX_CTRL_HSP_ENABLE |
810 COH901318_CX_CTRL_HSS_DISABLE |
811 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
812 COH901318_CX_CTRL_PRDD_DEST,
813 .param.ctrl_lli_last = 0 |
814 COH901318_CX_CTRL_TC_ENABLE |
815 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
816 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
817 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
818 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
819 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
820 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
821 COH901318_CX_CTRL_TCP_DISABLE |
822 COH901318_CX_CTRL_TC_IRQ_ENABLE |
823 COH901318_CX_CTRL_HSP_ENABLE |
824 COH901318_CX_CTRL_HSS_DISABLE |
825 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
826 COH901318_CX_CTRL_PRDD_DEST,
829 .number = U300_DMA_MSL_RX_3,
832 .dev_addr = U300_MSL_BASE + 3 * 0x40 + 0x220,
833 .param.config = COH901318_CX_CFG_CH_DISABLE |
834 COH901318_CX_CFG_LCR_DISABLE |
835 COH901318_CX_CFG_TC_IRQ_ENABLE |
836 COH901318_CX_CFG_BE_IRQ_ENABLE,
837 .param.ctrl_lli_chained = 0 |
838 COH901318_CX_CTRL_TC_ENABLE |
839 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
840 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
841 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
842 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
843 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
844 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
845 COH901318_CX_CTRL_TCP_DISABLE |
846 COH901318_CX_CTRL_TC_IRQ_DISABLE |
847 COH901318_CX_CTRL_HSP_ENABLE |
848 COH901318_CX_CTRL_HSS_DISABLE |
849 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
850 COH901318_CX_CTRL_PRDD_DEST,
851 .param.ctrl_lli = 0 |
852 COH901318_CX_CTRL_TC_ENABLE |
853 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
854 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
855 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
856 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
857 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
858 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
859 COH901318_CX_CTRL_TCP_DISABLE |
860 COH901318_CX_CTRL_TC_IRQ_ENABLE |
861 COH901318_CX_CTRL_HSP_ENABLE |
862 COH901318_CX_CTRL_HSS_DISABLE |
863 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
864 COH901318_CX_CTRL_PRDD_DEST,
865 .param.ctrl_lli_last = 0 |
866 COH901318_CX_CTRL_TC_ENABLE |
867 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
868 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
869 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
870 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
871 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
872 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
873 COH901318_CX_CTRL_TCP_DISABLE |
874 COH901318_CX_CTRL_TC_IRQ_ENABLE |
875 COH901318_CX_CTRL_HSP_ENABLE |
876 COH901318_CX_CTRL_HSS_DISABLE |
877 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
878 COH901318_CX_CTRL_PRDD_DEST,
881 .number = U300_DMA_MSL_RX_4,
884 .dev_addr = U300_MSL_BASE + 4 * 0x40 + 0x220,
885 .param.config = COH901318_CX_CFG_CH_DISABLE |
886 COH901318_CX_CFG_LCR_DISABLE |
887 COH901318_CX_CFG_TC_IRQ_ENABLE |
888 COH901318_CX_CFG_BE_IRQ_ENABLE,
889 .param.ctrl_lli_chained = 0 |
890 COH901318_CX_CTRL_TC_ENABLE |
891 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
892 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
893 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
894 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
895 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
896 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
897 COH901318_CX_CTRL_TCP_DISABLE |
898 COH901318_CX_CTRL_TC_IRQ_DISABLE |
899 COH901318_CX_CTRL_HSP_ENABLE |
900 COH901318_CX_CTRL_HSS_DISABLE |
901 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
902 COH901318_CX_CTRL_PRDD_DEST,
903 .param.ctrl_lli = 0 |
904 COH901318_CX_CTRL_TC_ENABLE |
905 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
906 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
907 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
908 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
909 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
910 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
911 COH901318_CX_CTRL_TCP_DISABLE |
912 COH901318_CX_CTRL_TC_IRQ_ENABLE |
913 COH901318_CX_CTRL_HSP_ENABLE |
914 COH901318_CX_CTRL_HSS_DISABLE |
915 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
916 COH901318_CX_CTRL_PRDD_DEST,
917 .param.ctrl_lli_last = 0 |
918 COH901318_CX_CTRL_TC_ENABLE |
919 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
920 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
921 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
922 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
923 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
924 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
925 COH901318_CX_CTRL_TCP_DISABLE |
926 COH901318_CX_CTRL_TC_IRQ_ENABLE |
927 COH901318_CX_CTRL_HSP_ENABLE |
928 COH901318_CX_CTRL_HSS_DISABLE |
929 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
930 COH901318_CX_CTRL_PRDD_DEST,
933 .number = U300_DMA_MSL_RX_5,
936 .dev_addr = U300_MSL_BASE + 5 * 0x40 + 0x220,
937 .param.config = COH901318_CX_CFG_CH_DISABLE |
938 COH901318_CX_CFG_LCR_DISABLE |
939 COH901318_CX_CFG_TC_IRQ_ENABLE |
940 COH901318_CX_CFG_BE_IRQ_ENABLE,
941 .param.ctrl_lli_chained = 0 |
942 COH901318_CX_CTRL_TC_ENABLE |
943 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
944 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
945 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
946 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
947 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
948 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
949 COH901318_CX_CTRL_TCP_DISABLE |
950 COH901318_CX_CTRL_TC_IRQ_DISABLE |
951 COH901318_CX_CTRL_HSP_ENABLE |
952 COH901318_CX_CTRL_HSS_DISABLE |
953 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
954 COH901318_CX_CTRL_PRDD_DEST,
955 .param.ctrl_lli = 0 |
956 COH901318_CX_CTRL_TC_ENABLE |
957 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
958 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
959 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
960 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
961 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
962 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
963 COH901318_CX_CTRL_TCP_DISABLE |
964 COH901318_CX_CTRL_TC_IRQ_ENABLE |
965 COH901318_CX_CTRL_HSP_ENABLE |
966 COH901318_CX_CTRL_HSS_DISABLE |
967 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
968 COH901318_CX_CTRL_PRDD_DEST,
969 .param.ctrl_lli_last = 0 |
970 COH901318_CX_CTRL_TC_ENABLE |
971 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
972 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
973 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
974 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
975 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
976 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
977 COH901318_CX_CTRL_TCP_DISABLE |
978 COH901318_CX_CTRL_TC_IRQ_ENABLE |
979 COH901318_CX_CTRL_HSP_ENABLE |
980 COH901318_CX_CTRL_HSS_DISABLE |
981 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
982 COH901318_CX_CTRL_PRDD_DEST,
985 .number = U300_DMA_MSL_RX_6,
988 .dev_addr = U300_MSL_BASE + 6 * 0x40 + 0x220,
991 * Don't set up device address, burst count or size of src
992 * or dst bus for this peripheral - handled by PrimeCell
996 .number = U300_DMA_MMCSD_RX_TX,
997 .name = "MMCSD RX TX",
999 .param.config = COH901318_CX_CFG_CH_DISABLE |
1000 COH901318_CX_CFG_LCR_DISABLE |
1001 COH901318_CX_CFG_TC_IRQ_ENABLE |
1002 COH901318_CX_CFG_BE_IRQ_ENABLE,
1003 .param.ctrl_lli_chained = 0 |
1004 COH901318_CX_CTRL_TC_ENABLE |
1005 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1006 COH901318_CX_CTRL_TCP_ENABLE |
1007 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1008 COH901318_CX_CTRL_HSP_ENABLE |
1009 COH901318_CX_CTRL_HSS_DISABLE |
1010 COH901318_CX_CTRL_DDMA_LEGACY,
1011 .param.ctrl_lli = 0 |
1012 COH901318_CX_CTRL_TC_ENABLE |
1013 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1014 COH901318_CX_CTRL_TCP_ENABLE |
1015 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1016 COH901318_CX_CTRL_HSP_ENABLE |
1017 COH901318_CX_CTRL_HSS_DISABLE |
1018 COH901318_CX_CTRL_DDMA_LEGACY,
1019 .param.ctrl_lli_last = 0 |
1020 COH901318_CX_CTRL_TC_ENABLE |
1021 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1022 COH901318_CX_CTRL_TCP_DISABLE |
1023 COH901318_CX_CTRL_TC_IRQ_ENABLE |
1024 COH901318_CX_CTRL_HSP_ENABLE |
1025 COH901318_CX_CTRL_HSS_DISABLE |
1026 COH901318_CX_CTRL_DDMA_LEGACY,
1030 .number = U300_DMA_MSPRO_TX,
1035 .number = U300_DMA_MSPRO_RX,
1040 * Don't set up device address, burst count or size of src
1041 * or dst bus for this peripheral - handled by PrimeCell
1045 .number = U300_DMA_UART0_TX,
1048 .param.config = COH901318_CX_CFG_CH_DISABLE |
1049 COH901318_CX_CFG_LCR_DISABLE |
1050 COH901318_CX_CFG_TC_IRQ_ENABLE |
1051 COH901318_CX_CFG_BE_IRQ_ENABLE,
1052 .param.ctrl_lli_chained = 0 |
1053 COH901318_CX_CTRL_TC_ENABLE |
1054 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1055 COH901318_CX_CTRL_TCP_ENABLE |
1056 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1057 COH901318_CX_CTRL_HSP_ENABLE |
1058 COH901318_CX_CTRL_HSS_DISABLE |
1059 COH901318_CX_CTRL_DDMA_LEGACY,
1060 .param.ctrl_lli = 0 |
1061 COH901318_CX_CTRL_TC_ENABLE |
1062 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1063 COH901318_CX_CTRL_TCP_ENABLE |
1064 COH901318_CX_CTRL_TC_IRQ_ENABLE |
1065 COH901318_CX_CTRL_HSP_ENABLE |
1066 COH901318_CX_CTRL_HSS_DISABLE |
1067 COH901318_CX_CTRL_DDMA_LEGACY,
1068 .param.ctrl_lli_last = 0 |
1069 COH901318_CX_CTRL_TC_ENABLE |
1070 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1071 COH901318_CX_CTRL_TCP_ENABLE |
1072 COH901318_CX_CTRL_TC_IRQ_ENABLE |
1073 COH901318_CX_CTRL_HSP_ENABLE |
1074 COH901318_CX_CTRL_HSS_DISABLE |
1075 COH901318_CX_CTRL_DDMA_LEGACY,
1078 .number = U300_DMA_UART0_RX,
1081 .param.config = COH901318_CX_CFG_CH_DISABLE |
1082 COH901318_CX_CFG_LCR_DISABLE |
1083 COH901318_CX_CFG_TC_IRQ_ENABLE |
1084 COH901318_CX_CFG_BE_IRQ_ENABLE,
1085 .param.ctrl_lli_chained = 0 |
1086 COH901318_CX_CTRL_TC_ENABLE |
1087 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1088 COH901318_CX_CTRL_TCP_ENABLE |
1089 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1090 COH901318_CX_CTRL_HSP_ENABLE |
1091 COH901318_CX_CTRL_HSS_DISABLE |
1092 COH901318_CX_CTRL_DDMA_LEGACY,
1093 .param.ctrl_lli = 0 |
1094 COH901318_CX_CTRL_TC_ENABLE |
1095 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1096 COH901318_CX_CTRL_TCP_ENABLE |
1097 COH901318_CX_CTRL_TC_IRQ_ENABLE |
1098 COH901318_CX_CTRL_HSP_ENABLE |
1099 COH901318_CX_CTRL_HSS_DISABLE |
1100 COH901318_CX_CTRL_DDMA_LEGACY,
1101 .param.ctrl_lli_last = 0 |
1102 COH901318_CX_CTRL_TC_ENABLE |
1103 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1104 COH901318_CX_CTRL_TCP_ENABLE |
1105 COH901318_CX_CTRL_TC_IRQ_ENABLE |
1106 COH901318_CX_CTRL_HSP_ENABLE |
1107 COH901318_CX_CTRL_HSS_DISABLE |
1108 COH901318_CX_CTRL_DDMA_LEGACY,
1111 .number = U300_DMA_APEX_TX,
1116 .number = U300_DMA_APEX_RX,
1121 .number = U300_DMA_PCM_I2S0_TX,
1122 .name = "PCM I2S0 TX",
1124 .dev_addr = U300_PCM_I2S0_BASE + 0x14,
1125 .param.config = COH901318_CX_CFG_CH_DISABLE |
1126 COH901318_CX_CFG_LCR_DISABLE |
1127 COH901318_CX_CFG_TC_IRQ_ENABLE |
1128 COH901318_CX_CFG_BE_IRQ_ENABLE,
1129 .param.ctrl_lli_chained = 0 |
1130 COH901318_CX_CTRL_TC_ENABLE |
1131 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1132 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1133 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
1134 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1135 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
1136 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1137 COH901318_CX_CTRL_TCP_DISABLE |
1138 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1139 COH901318_CX_CTRL_HSP_ENABLE |
1140 COH901318_CX_CTRL_HSS_DISABLE |
1141 COH901318_CX_CTRL_DDMA_LEGACY |
1142 COH901318_CX_CTRL_PRDD_SOURCE,
1143 .param.ctrl_lli = 0 |
1144 COH901318_CX_CTRL_TC_ENABLE |
1145 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1146 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1147 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
1148 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1149 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
1150 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1151 COH901318_CX_CTRL_TCP_ENABLE |
1152 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1153 COH901318_CX_CTRL_HSP_ENABLE |
1154 COH901318_CX_CTRL_HSS_DISABLE |
1155 COH901318_CX_CTRL_DDMA_LEGACY |
1156 COH901318_CX_CTRL_PRDD_SOURCE,
1157 .param.ctrl_lli_last = 0 |
1158 COH901318_CX_CTRL_TC_ENABLE |
1159 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1160 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1161 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
1162 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1163 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
1164 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1165 COH901318_CX_CTRL_TCP_ENABLE |
1166 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1167 COH901318_CX_CTRL_HSP_ENABLE |
1168 COH901318_CX_CTRL_HSS_DISABLE |
1169 COH901318_CX_CTRL_DDMA_LEGACY |
1170 COH901318_CX_CTRL_PRDD_SOURCE,
1173 .number = U300_DMA_PCM_I2S0_RX,
1174 .name = "PCM I2S0 RX",
1176 .dev_addr = U300_PCM_I2S0_BASE + 0x10,
1177 .param.config = COH901318_CX_CFG_CH_DISABLE |
1178 COH901318_CX_CFG_LCR_DISABLE |
1179 COH901318_CX_CFG_TC_IRQ_ENABLE |
1180 COH901318_CX_CFG_BE_IRQ_ENABLE,
1181 .param.ctrl_lli_chained = 0 |
1182 COH901318_CX_CTRL_TC_ENABLE |
1183 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1184 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1185 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
1186 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1187 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
1188 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1189 COH901318_CX_CTRL_TCP_DISABLE |
1190 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1191 COH901318_CX_CTRL_HSP_ENABLE |
1192 COH901318_CX_CTRL_HSS_DISABLE |
1193 COH901318_CX_CTRL_DDMA_LEGACY |
1194 COH901318_CX_CTRL_PRDD_DEST,
1195 .param.ctrl_lli = 0 |
1196 COH901318_CX_CTRL_TC_ENABLE |
1197 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1198 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1199 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
1200 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1201 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
1202 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1203 COH901318_CX_CTRL_TCP_ENABLE |
1204 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1205 COH901318_CX_CTRL_HSP_ENABLE |
1206 COH901318_CX_CTRL_HSS_DISABLE |
1207 COH901318_CX_CTRL_DDMA_LEGACY |
1208 COH901318_CX_CTRL_PRDD_DEST,
1209 .param.ctrl_lli_last = 0 |
1210 COH901318_CX_CTRL_TC_ENABLE |
1211 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1212 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1213 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
1214 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1215 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
1216 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1217 COH901318_CX_CTRL_TCP_ENABLE |
1218 COH901318_CX_CTRL_TC_IRQ_ENABLE |
1219 COH901318_CX_CTRL_HSP_ENABLE |
1220 COH901318_CX_CTRL_HSS_DISABLE |
1221 COH901318_CX_CTRL_DDMA_LEGACY |
1222 COH901318_CX_CTRL_PRDD_DEST,
1225 .number = U300_DMA_PCM_I2S1_TX,
1226 .name = "PCM I2S1 TX",
1228 .dev_addr = U300_PCM_I2S1_BASE + 0x14,
1229 .param.config = COH901318_CX_CFG_CH_DISABLE |
1230 COH901318_CX_CFG_LCR_DISABLE |
1231 COH901318_CX_CFG_TC_IRQ_ENABLE |
1232 COH901318_CX_CFG_BE_IRQ_ENABLE,
1233 .param.ctrl_lli_chained = 0 |
1234 COH901318_CX_CTRL_TC_ENABLE |
1235 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1236 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1237 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
1238 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1239 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
1240 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1241 COH901318_CX_CTRL_TCP_DISABLE |
1242 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1243 COH901318_CX_CTRL_HSP_ENABLE |
1244 COH901318_CX_CTRL_HSS_DISABLE |
1245 COH901318_CX_CTRL_DDMA_LEGACY |
1246 COH901318_CX_CTRL_PRDD_SOURCE,
1247 .param.ctrl_lli = 0 |
1248 COH901318_CX_CTRL_TC_ENABLE |
1249 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1250 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1251 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
1252 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1253 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
1254 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1255 COH901318_CX_CTRL_TCP_ENABLE |
1256 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1257 COH901318_CX_CTRL_HSP_ENABLE |
1258 COH901318_CX_CTRL_HSS_DISABLE |
1259 COH901318_CX_CTRL_DDMA_LEGACY |
1260 COH901318_CX_CTRL_PRDD_SOURCE,
1261 .param.ctrl_lli_last = 0 |
1262 COH901318_CX_CTRL_TC_ENABLE |
1263 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1264 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1265 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
1266 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1267 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
1268 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1269 COH901318_CX_CTRL_TCP_ENABLE |
1270 COH901318_CX_CTRL_TC_IRQ_ENABLE |
1271 COH901318_CX_CTRL_HSP_ENABLE |
1272 COH901318_CX_CTRL_HSS_DISABLE |
1273 COH901318_CX_CTRL_DDMA_LEGACY |
1274 COH901318_CX_CTRL_PRDD_SOURCE,
1277 .number = U300_DMA_PCM_I2S1_RX,
1278 .name = "PCM I2S1 RX",
1280 .dev_addr = U300_PCM_I2S1_BASE + 0x10,
1281 .param.config = COH901318_CX_CFG_CH_DISABLE |
1282 COH901318_CX_CFG_LCR_DISABLE |
1283 COH901318_CX_CFG_TC_IRQ_ENABLE |
1284 COH901318_CX_CFG_BE_IRQ_ENABLE,
1285 .param.ctrl_lli_chained = 0 |
1286 COH901318_CX_CTRL_TC_ENABLE |
1287 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1288 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1289 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
1290 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1291 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
1292 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1293 COH901318_CX_CTRL_TCP_DISABLE |
1294 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1295 COH901318_CX_CTRL_HSP_ENABLE |
1296 COH901318_CX_CTRL_HSS_DISABLE |
1297 COH901318_CX_CTRL_DDMA_LEGACY |
1298 COH901318_CX_CTRL_PRDD_DEST,
1299 .param.ctrl_lli = 0 |
1300 COH901318_CX_CTRL_TC_ENABLE |
1301 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1302 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1303 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
1304 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1305 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
1306 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1307 COH901318_CX_CTRL_TCP_ENABLE |
1308 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1309 COH901318_CX_CTRL_HSP_ENABLE |
1310 COH901318_CX_CTRL_HSS_DISABLE |
1311 COH901318_CX_CTRL_DDMA_LEGACY |
1312 COH901318_CX_CTRL_PRDD_DEST,
1313 .param.ctrl_lli_last = 0 |
1314 COH901318_CX_CTRL_TC_ENABLE |
1315 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1316 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1317 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
1318 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1319 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
1320 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1321 COH901318_CX_CTRL_TCP_ENABLE |
1322 COH901318_CX_CTRL_TC_IRQ_ENABLE |
1323 COH901318_CX_CTRL_HSP_ENABLE |
1324 COH901318_CX_CTRL_HSS_DISABLE |
1325 COH901318_CX_CTRL_DDMA_LEGACY |
1326 COH901318_CX_CTRL_PRDD_DEST,
1329 .number = U300_DMA_XGAM_CDI,
1334 .number = U300_DMA_XGAM_PDI,
1339 * Don't set up device address, burst count or size of src
1340 * or dst bus for this peripheral - handled by PrimeCell
1344 .number = U300_DMA_SPI_TX,
1347 .param.config = COH901318_CX_CFG_CH_DISABLE |
1348 COH901318_CX_CFG_LCR_DISABLE |
1349 COH901318_CX_CFG_TC_IRQ_ENABLE |
1350 COH901318_CX_CFG_BE_IRQ_ENABLE,
1351 .param.ctrl_lli_chained = 0 |
1352 COH901318_CX_CTRL_TC_ENABLE |
1353 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1354 COH901318_CX_CTRL_TCP_DISABLE |
1355 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1356 COH901318_CX_CTRL_HSP_ENABLE |
1357 COH901318_CX_CTRL_HSS_DISABLE |
1358 COH901318_CX_CTRL_DDMA_LEGACY,
1359 .param.ctrl_lli = 0 |
1360 COH901318_CX_CTRL_TC_ENABLE |
1361 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1362 COH901318_CX_CTRL_TCP_DISABLE |
1363 COH901318_CX_CTRL_TC_IRQ_ENABLE |
1364 COH901318_CX_CTRL_HSP_ENABLE |
1365 COH901318_CX_CTRL_HSS_DISABLE |
1366 COH901318_CX_CTRL_DDMA_LEGACY,
1367 .param.ctrl_lli_last = 0 |
1368 COH901318_CX_CTRL_TC_ENABLE |
1369 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1370 COH901318_CX_CTRL_TCP_DISABLE |
1371 COH901318_CX_CTRL_TC_IRQ_ENABLE |
1372 COH901318_CX_CTRL_HSP_ENABLE |
1373 COH901318_CX_CTRL_HSS_DISABLE |
1374 COH901318_CX_CTRL_DDMA_LEGACY,
1377 .number = U300_DMA_SPI_RX,
1380 .param.config = COH901318_CX_CFG_CH_DISABLE |
1381 COH901318_CX_CFG_LCR_DISABLE |
1382 COH901318_CX_CFG_TC_IRQ_ENABLE |
1383 COH901318_CX_CFG_BE_IRQ_ENABLE,
1384 .param.ctrl_lli_chained = 0 |
1385 COH901318_CX_CTRL_TC_ENABLE |
1386 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1387 COH901318_CX_CTRL_TCP_DISABLE |
1388 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1389 COH901318_CX_CTRL_HSP_ENABLE |
1390 COH901318_CX_CTRL_HSS_DISABLE |
1391 COH901318_CX_CTRL_DDMA_LEGACY,
1392 .param.ctrl_lli = 0 |
1393 COH901318_CX_CTRL_TC_ENABLE |
1394 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1395 COH901318_CX_CTRL_TCP_DISABLE |
1396 COH901318_CX_CTRL_TC_IRQ_ENABLE |
1397 COH901318_CX_CTRL_HSP_ENABLE |
1398 COH901318_CX_CTRL_HSS_DISABLE |
1399 COH901318_CX_CTRL_DDMA_LEGACY,
1400 .param.ctrl_lli_last = 0 |
1401 COH901318_CX_CTRL_TC_ENABLE |
1402 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1403 COH901318_CX_CTRL_TCP_DISABLE |
1404 COH901318_CX_CTRL_TC_IRQ_ENABLE |
1405 COH901318_CX_CTRL_HSP_ENABLE |
1406 COH901318_CX_CTRL_HSS_DISABLE |
1407 COH901318_CX_CTRL_DDMA_LEGACY,
1411 .number = U300_DMA_GENERAL_PURPOSE_0,
1412 .name = "GENERAL 00",
1415 .param.config = flags_memcpy_config,
1416 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1417 .param.ctrl_lli = flags_memcpy_lli,
1418 .param.ctrl_lli_last = flags_memcpy_lli_last,
1421 .number = U300_DMA_GENERAL_PURPOSE_1,
1422 .name = "GENERAL 01",
1425 .param.config = flags_memcpy_config,
1426 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1427 .param.ctrl_lli = flags_memcpy_lli,
1428 .param.ctrl_lli_last = flags_memcpy_lli_last,
1431 .number = U300_DMA_GENERAL_PURPOSE_2,
1432 .name = "GENERAL 02",
1435 .param.config = flags_memcpy_config,
1436 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1437 .param.ctrl_lli = flags_memcpy_lli,
1438 .param.ctrl_lli_last = flags_memcpy_lli_last,
1441 .number = U300_DMA_GENERAL_PURPOSE_3,
1442 .name = "GENERAL 03",
1445 .param.config = flags_memcpy_config,
1446 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1447 .param.ctrl_lli = flags_memcpy_lli,
1448 .param.ctrl_lli_last = flags_memcpy_lli_last,
1451 .number = U300_DMA_GENERAL_PURPOSE_4,
1452 .name = "GENERAL 04",
1455 .param.config = flags_memcpy_config,
1456 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1457 .param.ctrl_lli = flags_memcpy_lli,
1458 .param.ctrl_lli_last = flags_memcpy_lli_last,
1461 .number = U300_DMA_GENERAL_PURPOSE_5,
1462 .name = "GENERAL 05",
1465 .param.config = flags_memcpy_config,
1466 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1467 .param.ctrl_lli = flags_memcpy_lli,
1468 .param.ctrl_lli_last = flags_memcpy_lli_last,
1471 .number = U300_DMA_GENERAL_PURPOSE_6,
1472 .name = "GENERAL 06",
1475 .param.config = flags_memcpy_config,
1476 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1477 .param.ctrl_lli = flags_memcpy_lli,
1478 .param.ctrl_lli_last = flags_memcpy_lli_last,
1481 .number = U300_DMA_GENERAL_PURPOSE_7,
1482 .name = "GENERAL 07",
1485 .param.config = flags_memcpy_config,
1486 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1487 .param.ctrl_lli = flags_memcpy_lli,
1488 .param.ctrl_lli_last = flags_memcpy_lli_last,
1491 .number = U300_DMA_GENERAL_PURPOSE_8,
1492 .name = "GENERAL 08",
1495 .param.config = flags_memcpy_config,
1496 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1497 .param.ctrl_lli = flags_memcpy_lli,
1498 .param.ctrl_lli_last = flags_memcpy_lli_last,
1500 #ifdef CONFIG_MACH_U300_BS335
1502 .number = U300_DMA_UART1_TX,
1507 .number = U300_DMA_UART1_RX,
1513 .number = U300_DMA_GENERAL_PURPOSE_9,
1514 .name = "GENERAL 09",
1517 .param.config = flags_memcpy_config,
1518 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1519 .param.ctrl_lli = flags_memcpy_lli,
1520 .param.ctrl_lli_last = flags_memcpy_lli_last,
1523 .number = U300_DMA_GENERAL_PURPOSE_10,
1524 .name = "GENERAL 10",
1527 .param.config = flags_memcpy_config,
1528 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1529 .param.ctrl_lli = flags_memcpy_lli,
1530 .param.ctrl_lli_last = flags_memcpy_lli_last,
1536 static struct coh901318_platform coh901318_platform = {
1537 .chans_slave = dma_slave_channels,
1538 .chans_memcpy = dma_memcpy_channels,
1539 .access_memory_state = coh901318_access_memory_state,
1540 .chan_conf = chan_config,
1541 .max_channels = U300_DMA_CHANNELS,
1544 static struct resource pinmux_resources[] = {
1546 .start = U300_SYSCON_BASE,
1547 .end = U300_SYSCON_BASE + SZ_4K - 1,
1548 .flags = IORESOURCE_MEM,
1552 static struct platform_device wdog_device = {
1553 .name = "coh901327_wdog",
1555 .num_resources = ARRAY_SIZE(wdog_resources),
1556 .resource = wdog_resources,
1559 static struct platform_device i2c0_device = {
1562 .num_resources = ARRAY_SIZE(i2c0_resources),
1563 .resource = i2c0_resources,
1566 static struct platform_device i2c1_device = {
1569 .num_resources = ARRAY_SIZE(i2c1_resources),
1570 .resource = i2c1_resources,
1574 * The different variants have a few different versions of the
1575 * GPIO block, with different number of ports.
1577 static struct u300_gpio_platform u300_gpio_plat = {
1578 #if defined(CONFIG_MACH_U300_BS2X) || defined(CONFIG_MACH_U300_BS330)
1579 .variant = U300_GPIO_COH901335,
1582 #ifdef CONFIG_MACH_U300_BS335
1583 .variant = U300_GPIO_COH901571_3_BS335,
1586 #ifdef CONFIG_MACH_U300_BS365
1587 .variant = U300_GPIO_COH901571_3_BS365,
1591 .gpio_irq_base = IRQ_U300_GPIO_BASE,
1594 static struct platform_device gpio_device = {
1595 .name = "u300-gpio",
1597 .num_resources = ARRAY_SIZE(gpio_resources),
1598 .resource = gpio_resources,
1600 .platform_data = &u300_gpio_plat,
1604 static struct platform_device keypad_device = {
1607 .num_resources = ARRAY_SIZE(keypad_resources),
1608 .resource = keypad_resources,
1611 static struct platform_device rtc_device = {
1612 .name = "rtc-coh901331",
1614 .num_resources = ARRAY_SIZE(rtc_resources),
1615 .resource = rtc_resources,
1618 static struct mtd_partition u300_partitions[] = {
1620 .name = "bootrecords",
1627 .size = 8064 * SZ_1K,
1631 .offset = 8192 * SZ_1K,
1632 .size = 253952 * SZ_1K,
1636 static struct fsmc_nand_platform_data nand_platform_data = {
1637 .partitions = u300_partitions,
1638 .nr_partitions = ARRAY_SIZE(u300_partitions),
1639 .options = NAND_SKIP_BBTSCAN,
1640 .width = FSMC_NAND_BW8,
1643 static struct platform_device nand_device = {
1644 .name = "fsmc-nand",
1646 .resource = fsmc_resources,
1647 .num_resources = ARRAY_SIZE(fsmc_resources),
1649 .platform_data = &nand_platform_data,
1653 static struct platform_device ave_device = {
1654 .name = "video_enc",
1656 .num_resources = ARRAY_SIZE(ave_resources),
1657 .resource = ave_resources,
1660 static struct platform_device dma_device = {
1661 .name = "coh901318",
1663 .resource = dma_resource,
1664 .num_resources = ARRAY_SIZE(dma_resource),
1666 .platform_data = &coh901318_platform,
1667 .coherent_dma_mask = ~0,
1671 static struct platform_device pinmux_device = {
1672 .name = "pinmux-u300",
1674 .num_resources = ARRAY_SIZE(pinmux_resources),
1675 .resource = pinmux_resources,
1678 /* Pinmux settings */
1679 static struct pinmux_map u300_pinmux_map[] = {
1680 /* anonymous maps for chip power and EMIFs */
1681 PINMUX_MAP_PRIMARY_SYS_HOG("POWER", "power"),
1682 PINMUX_MAP_PRIMARY_SYS_HOG("EMIF0", "emif0"),
1683 PINMUX_MAP_PRIMARY_SYS_HOG("EMIF1", "emif1"),
1684 /* per-device maps for MMC/SD, SPI and UART */
1685 PINMUX_MAP_PRIMARY("MMCSD", "mmc0", "mmci"),
1686 PINMUX_MAP_PRIMARY("SPI", "spi0", "pl022"),
1687 PINMUX_MAP_PRIMARY("UART0", "uart0", "uart0"),
1690 struct u300_mux_hog {
1696 static struct u300_mux_hog u300_mux_hogs[] = {
1699 .dev = &uart0_device.dev,
1703 .dev = &pl022_device.dev,
1707 .dev = &mmcsd_device.dev,
1711 static int __init u300_pinmux_fetch(void)
1715 for (i = 0; i < ARRAY_SIZE(u300_mux_hogs); i++) {
1719 pmx = pinmux_get(u300_mux_hogs[i].dev, NULL);
1721 pr_err("u300: could not get pinmux hog %s\n",
1722 u300_mux_hogs[i].name);
1725 ret = pinmux_enable(pmx);
1727 pr_err("u300: could enable pinmux hog %s\n",
1728 u300_mux_hogs[i].name);
1731 u300_mux_hogs[i].pmx = pmx;
1735 subsys_initcall(u300_pinmux_fetch);
1738 * Notice that AMBA devices are initialized before platform devices.
1741 static struct platform_device *platform_devs[] __initdata = {
1755 * Interrupts: the U300 platforms have two pl190 ARM PrimeCells connected
1756 * together so some interrupts are connected to the first one and some
1757 * to the second one.
1759 void __init u300_init_irq(void)
1761 u32 mask[2] = {0, 0};
1765 /* initialize clocking early, we want to clock the INTCON */
1768 /* Clock the interrupt controller */
1769 clk = clk_get_sys("intcon", NULL);
1770 BUG_ON(IS_ERR(clk));
1773 for (i = 0; i < U300_VIC_IRQS_END; i++)
1774 set_bit(i, (unsigned long *) &mask[0]);
1775 vic_init((void __iomem *) U300_INTCON0_VBASE, 0, mask[0], mask[0]);
1776 vic_init((void __iomem *) U300_INTCON1_VBASE, 32, mask[1], mask[1]);
1781 * U300 platforms peripheral handling
1789 * This is a list of the Digital Baseband chips used in the U300 platform.
1791 static struct db_chip db_chips[] __initdata = {
1818 .name = "DB3350 P1x",
1822 .name = "DB3350 P2x",
1825 .chipid = 0x0000, /* List terminator */
1830 static void __init u300_init_check_chip(void)
1834 struct db_chip *chip;
1835 const char *chipname;
1836 const char unknown[] = "UNKNOWN";
1838 /* Read out and print chip ID */
1839 val = readw(U300_SYSCON_VBASE + U300_SYSCON_CIDR);
1840 /* This is in funky bigendian order... */
1841 val = (val & 0xFFU) << 8 | (val >> 8);
1845 for ( ; chip->chipid; chip++) {
1846 if (chip->chipid == (val & 0xFF00U)) {
1847 chipname = chip->name;
1851 printk(KERN_INFO "Initializing U300 system on %s baseband chip " \
1852 "(chip ID 0x%04x)\n", chipname, val);
1854 #ifdef CONFIG_MACH_U300_BS330
1855 if ((val & 0xFF00U) != 0xd800) {
1856 printk(KERN_ERR "Platform configured for BS330 " \
1857 "with DB3200 but %s detected, expect problems!",
1861 #ifdef CONFIG_MACH_U300_BS335
1862 if ((val & 0xFF00U) != 0xf000 && (val & 0xFF00U) != 0xf100) {
1863 printk(KERN_ERR "Platform configured for BS335 " \
1864 " with DB3350 but %s detected, expect problems!",
1868 #ifdef CONFIG_MACH_U300_BS365
1869 if ((val & 0xFF00U) != 0xe800) {
1870 printk(KERN_ERR "Platform configured for BS365 " \
1871 "with DB3210 but %s detected, expect problems!",
1880 * Some devices and their resources require reserved physical memory from
1881 * the end of the available RAM. This function traverses the list of devices
1882 * and assigns actual addresses to these.
1884 static void __init u300_assign_physmem(void)
1886 unsigned long curr_start = __pa(high_memory);
1889 for (i = 0; i < ARRAY_SIZE(platform_devs); i++) {
1890 for (j = 0; j < platform_devs[i]->num_resources; j++) {
1891 struct resource *const res =
1892 &platform_devs[i]->resource[j];
1894 if (IORESOURCE_MEM == res->flags &&
1896 res->start = curr_start;
1897 res->end += curr_start;
1898 curr_start += resource_size(res);
1900 printk(KERN_INFO "core.c: Mapping RAM " \
1901 "%#x-%#x to device %s:%s\n",
1902 res->start, res->end,
1903 platform_devs[i]->name, res->name);
1909 void __init u300_init_devices(void)
1914 /* Check what platform we run and print some status information */
1915 u300_init_check_chip();
1917 /* Set system to run at PLL208, max performance, a known state. */
1918 val = readw(U300_SYSCON_VBASE + U300_SYSCON_CCR);
1919 val &= ~U300_SYSCON_CCR_CLKING_PERFORMANCE_MASK;
1920 writew(val, U300_SYSCON_VBASE + U300_SYSCON_CCR);
1921 /* Wait for the PLL208 to lock if not locked in yet */
1922 while (!(readw(U300_SYSCON_VBASE + U300_SYSCON_CSR) &
1923 U300_SYSCON_CSR_PLL208_LOCK_IND));
1924 /* Initialize SPI device with some board specifics */
1925 u300_spi_init(&pl022_device);
1927 /* Register the AMBA devices in the AMBA bus abstraction layer */
1928 for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
1929 struct amba_device *d = amba_devs[i];
1930 amba_device_register(d, &iomem_resource);
1933 u300_assign_physmem();
1935 /* Initialize pinmuxing */
1936 pinmux_register_mappings(u300_pinmux_map,
1937 ARRAY_SIZE(u300_pinmux_map));
1939 /* Register subdevices on the I2C buses */
1940 u300_i2c_register_board_devices();
1942 /* Register the platform devices */
1943 platform_add_devices(platform_devs, ARRAY_SIZE(platform_devs));
1945 /* Register subdevices on the SPI bus */
1946 u300_spi_register_board_devices();
1948 #ifndef CONFIG_MACH_U300_SEMI_IS_SHARED
1950 * Enable SEMI self refresh. Self-refresh of the SDRAM is entered when
1951 * both subsystems are requesting this mode.
1952 * If we not share the Acc SDRAM, this is never the case. Therefore
1953 * enable it here from the App side.
1955 val = readw(U300_SYSCON_VBASE + U300_SYSCON_SMCR) |
1956 U300_SYSCON_SMCR_SEMI_SREFREQ_ENABLE;
1957 writew(val, U300_SYSCON_VBASE + U300_SYSCON_SMCR);
1958 #endif /* CONFIG_MACH_U300_SEMI_IS_SHARED */
1961 static int core_module_init(void)
1964 * This needs to be initialized later: it needs the input framework
1965 * to be initialized first.
1967 return mmc_init(&mmcsd_device);
1969 module_init(core_module_init);