arch/arm/mach-u300/core.c

   1 /*
   2  *
   3  * arch/arm/mach-u300/core.c
   4  *
   5  *
   6  * Copyright (C) 2007-2012 ST-Ericsson SA
   7  * License terms: GNU General Public License (GPL) version 2
   8  * Core platform support, IRQ handling and device definitions.
   9  * Author: Linus Walleij <linus.walleij@stericsson.com>
  10  */
  11 #include <linux/kernel.h>
  12 #include <linux/pinctrl/machine.h>
  13 #include <linux/pinctrl/pinconf-generic.h>
  14 #include <linux/platform_data/clk-u300.h>
  15 #include <linux/platform_data/pinctrl-coh901.h>
  16 #include <linux/irqchip.h>
  17 #include <linux/of_address.h>
  18 #include <linux/of_platform.h>
  19 #include <linux/clocksource.h>
  20 #include <linux/clk.h>
  21
  22 #include <asm/mach/map.h>
  23 #include <asm/mach/arch.h>
  24
  25 /*
  26  * These are the large blocks of memory allocated for I/O.
  27  * the defines are used for setting up the I/O memory mapping.
  28  */
  29
  30 /* NAND Flash CS0 */
  31 #define U300_NAND_CS0_PHYS_BASE         0x80000000
  32 /* NFIF */
  33 #define U300_NAND_IF_PHYS_BASE          0x9f800000
  34 /* ALE, CLE offset for FSMC NAND */
  35 #define PLAT_NAND_CLE                   (1 << 16)
  36 #define PLAT_NAND_ALE                   (1 << 17)
  37 /* AHB Peripherals */
  38 #define U300_AHB_PER_PHYS_BASE          0xa0000000
  39 #define U300_AHB_PER_VIRT_BASE          0xff010000
  40 /* FAST Peripherals */
  41 #define U300_FAST_PER_PHYS_BASE         0xc0000000
  42 #define U300_FAST_PER_VIRT_BASE         0xff020000
  43 /* SLOW Peripherals */
  44 #define U300_SLOW_PER_PHYS_BASE         0xc0010000
  45 #define U300_SLOW_PER_VIRT_BASE         0xff000000
  46 /* Boot ROM */
  47 #define U300_BOOTROM_PHYS_BASE          0xffff0000
  48 #define U300_BOOTROM_VIRT_BASE          0xffff0000
  49 /* SEMI config base */
  50 #define U300_SEMI_CONFIG_BASE           0x2FFE0000
  51
  52 /*
  53  * AHB peripherals
  54  */
  55
  56 /* AHB Peripherals Bridge Controller */
  57 #define U300_AHB_BRIDGE_BASE            (U300_AHB_PER_PHYS_BASE+0x0000)
  58 /* Vectored Interrupt Controller 0, servicing 32 interrupts */
  59 #define U300_INTCON0_BASE               (U300_AHB_PER_PHYS_BASE+0x1000)
  60 #define U300_INTCON0_VBASE              IOMEM(U300_AHB_PER_VIRT_BASE+0x1000)
  61 /* Vectored Interrupt Controller 1, servicing 32 interrupts */
  62 #define U300_INTCON1_BASE               (U300_AHB_PER_PHYS_BASE+0x2000)
  63 #define U300_INTCON1_VBASE              IOMEM(U300_AHB_PER_VIRT_BASE+0x2000)
  64 /* Memory Stick Pro (MSPRO) controller */
  65 #define U300_MSPRO_BASE                 (U300_AHB_PER_PHYS_BASE+0x3000)
  66 /* EMIF Configuration Area */
  67 #define U300_EMIF_CFG_BASE              (U300_AHB_PER_PHYS_BASE+0x4000)
  68
  69 /*
  70  * FAST peripherals
  71  */
  72
  73 /* FAST bridge control */
  74 #define U300_FAST_BRIDGE_BASE           (U300_FAST_PER_PHYS_BASE+0x0000)
  75 /* MMC/SD controller */
  76 #define U300_MMCSD_BASE                 (U300_FAST_PER_PHYS_BASE+0x1000)
  77 /* PCM I2S0 controller */
  78 #define U300_PCM_I2S0_BASE              (U300_FAST_PER_PHYS_BASE+0x2000)
  79 /* PCM I2S1 controller */
  80 #define U300_PCM_I2S1_BASE              (U300_FAST_PER_PHYS_BASE+0x3000)
  81 /* I2C0 controller */
  82 #define U300_I2C0_BASE                  (U300_FAST_PER_PHYS_BASE+0x4000)
  83 /* I2C1 controller */
  84 #define U300_I2C1_BASE                  (U300_FAST_PER_PHYS_BASE+0x5000)
  85 /* SPI controller */
  86 #define U300_SPI_BASE                   (U300_FAST_PER_PHYS_BASE+0x6000)
  87 /* Fast UART1 on U335 only */
  88 #define U300_UART1_BASE                 (U300_FAST_PER_PHYS_BASE+0x7000)
  89
  90 /*
  91  * SLOW peripherals
  92  */
  93
  94 /* SLOW bridge control */
  95 #define U300_SLOW_BRIDGE_BASE           (U300_SLOW_PER_PHYS_BASE)
  96 /* SYSCON */
  97 #define U300_SYSCON_BASE                (U300_SLOW_PER_PHYS_BASE+0x1000)
  98 #define U300_SYSCON_VBASE               IOMEM(U300_SLOW_PER_VIRT_BASE+0x1000)
  99 /* Watchdog */
 100 #define U300_WDOG_BASE                  (U300_SLOW_PER_PHYS_BASE+0x2000)
 101 /* UART0 */
 102 #define U300_UART0_BASE                 (U300_SLOW_PER_PHYS_BASE+0x3000)
 103 /* APP side special timer */
 104 #define U300_TIMER_APP_BASE             (U300_SLOW_PER_PHYS_BASE+0x4000)
 105 #define U300_TIMER_APP_VBASE            IOMEM(U300_SLOW_PER_VIRT_BASE+0x4000)
 106 /* Keypad */
 107 #define U300_KEYPAD_BASE                (U300_SLOW_PER_PHYS_BASE+0x5000)
 108 /* GPIO */
 109 #define U300_GPIO_BASE                  (U300_SLOW_PER_PHYS_BASE+0x6000)
 110 /* RTC */
 111 #define U300_RTC_BASE                   (U300_SLOW_PER_PHYS_BASE+0x7000)
 112 /* Bus tracer */
 113 #define U300_BUSTR_BASE                 (U300_SLOW_PER_PHYS_BASE+0x8000)
 114 /* Event handler (hardware queue) */
 115 #define U300_EVHIST_BASE                (U300_SLOW_PER_PHYS_BASE+0x9000)
 116 /* Genric Timer */
 117 #define U300_TIMER_BASE                 (U300_SLOW_PER_PHYS_BASE+0xa000)
 118 /* PPM */
 119 #define U300_PPM_BASE                   (U300_SLOW_PER_PHYS_BASE+0xb000)
 120
 121 /*
 122  * REST peripherals
 123  */
 124
 125 /* ISP (image signal processor) */
 126 #define U300_ISP_BASE                   (0xA0008000)
 127 /* DMA Controller base */
 128 #define U300_DMAC_BASE                  (0xC0020000)
 129 /* MSL Base */
 130 #define U300_MSL_BASE                   (0xc0022000)
 131 /* APEX Base */
 132 #define U300_APEX_BASE                  (0xc0030000)
 133 /* Video Encoder Base */
 134 #define U300_VIDEOENC_BASE              (0xc0080000)
 135 /* XGAM Base */
 136 #define U300_XGAM_BASE                  (0xd0000000)
 137
 138 /*
 139  * SYSCON addresses applicable to the core machine.
 140  */
 141
 142 /* Chip ID register 16bit (R/-) */
 143 #define U300_SYSCON_CIDR                                        (0x400)
 144 /* SMCR */
 145 #define U300_SYSCON_SMCR                                        (0x4d0)
 146 #define U300_SYSCON_SMCR_FIELD_MASK                             (0x000e)
 147 #define U300_SYSCON_SMCR_SEMI_SREFACK_IND                       (0x0008)
 148 #define U300_SYSCON_SMCR_SEMI_SREFREQ_ENABLE                    (0x0004)
 149 #define U300_SYSCON_SMCR_SEMI_EXT_BOOT_MODE_ENABLE              (0x0002)
 150 /* CPU_SW_DBGEN Software Debug Enable 16bit (R/W) */
 151 #define U300_SYSCON_CSDR                                        (0x4f0)
 152 #define U300_SYSCON_CSDR_SW_DEBUG_ENABLE                        (0x0001)
 153 /* PRINT_CONTROL Print Control 16bit (R/-) */
 154 #define U300_SYSCON_PCR                                         (0x4f8)
 155 #define U300_SYSCON_PCR_SERV_IND                                (0x0001)
 156 /* BOOT_CONTROL 16bit (R/-) */
 157 #define U300_SYSCON_BCR                                         (0x4fc)
 158 #define U300_SYSCON_BCR_ACC_CPU_SUBSYS_VINITHI_IND              (0x0400)
 159 #define U300_SYSCON_BCR_APP_CPU_SUBSYS_VINITHI_IND              (0x0200)
 160 #define U300_SYSCON_BCR_EXTRA_BOOT_OPTION_MASK                  (0x01FC)
 161 #define U300_SYSCON_BCR_APP_BOOT_SERV_MASK                      (0x0003)
 162
 163 static void __iomem *syscon_base;
 164
 165 /*
 166  * Static I/O mappings that are needed for booting the U300 platforms. The
 167  * only things we need are the areas where we find the timer, syscon and
 168  * intcon, since the remaining device drivers will map their own memory
 169  * physical to virtual as the need arise.
 170  */
 171 static struct map_desc u300_io_desc[] __initdata = {
 172         {
 173                 .virtual        = U300_SLOW_PER_VIRT_BASE,
 174                 .pfn            = __phys_to_pfn(U300_SLOW_PER_PHYS_BASE),
 175                 .length         = SZ_64K,
 176                 .type           = MT_DEVICE,
 177         },
 178         {
 179                 .virtual        = U300_AHB_PER_VIRT_BASE,
 180                 .pfn            = __phys_to_pfn(U300_AHB_PER_PHYS_BASE),
 181                 .length         = SZ_32K,
 182                 .type           = MT_DEVICE,
 183         },
 184         {
 185                 .virtual        = U300_FAST_PER_VIRT_BASE,
 186                 .pfn            = __phys_to_pfn(U300_FAST_PER_PHYS_BASE),
 187                 .length         = SZ_32K,
 188                 .type           = MT_DEVICE,
 189         },
 190 };
 191
 192 static void __init u300_map_io(void)
 193 {
 194         iotable_init(u300_io_desc, ARRAY_SIZE(u300_io_desc));
 195 }
 196
 197 /*
 198  * The different variants have a few different versions of the
 199  * GPIO block, with different number of ports.
 200  */
 201 static struct u300_gpio_platform u300_gpio_plat = {
 202         .ports = 7,
 203         .gpio_base = 0,
 204 };
 205
 206 static unsigned long pin_pullup_conf[] = {
 207         PIN_CONF_PACKED(PIN_CONFIG_BIAS_PULL_UP, 1),
 208 };
 209
 210 static unsigned long pin_highz_conf[] = {
 211         PIN_CONF_PACKED(PIN_CONFIG_BIAS_HIGH_IMPEDANCE, 0),
 212 };
 213
 214 /* Pin control settings */
 215 static struct pinctrl_map __initdata u300_pinmux_map[] = {
 216         /* anonymous maps for chip power and EMIFs */
 217         PIN_MAP_MUX_GROUP_HOG_DEFAULT("pinctrl-u300", NULL, "power"),
 218         PIN_MAP_MUX_GROUP_HOG_DEFAULT("pinctrl-u300", NULL, "emif0"),
 219         PIN_MAP_MUX_GROUP_HOG_DEFAULT("pinctrl-u300", NULL, "emif1"),
 220         /* per-device maps for MMC/SD, SPI and UART */
 221         PIN_MAP_MUX_GROUP_DEFAULT("mmci",  "pinctrl-u300", NULL, "mmc0"),
 222         PIN_MAP_MUX_GROUP_DEFAULT("pl022", "pinctrl-u300", NULL, "spi0"),
 223         PIN_MAP_MUX_GROUP_DEFAULT("uart0", "pinctrl-u300", NULL, "uart0"),
 224         /* This pin is used for clock return rather than GPIO */
 225         PIN_MAP_CONFIGS_PIN_DEFAULT("mmci", "pinctrl-u300", "PIO APP GPIO 11",
 226                                     pin_pullup_conf),
 227         /* This pin is used for card detect */
 228         PIN_MAP_CONFIGS_PIN_DEFAULT("mmci", "pinctrl-u300", "PIO MS INS",
 229                                     pin_highz_conf),
 230 };
 231
 232 struct db_chip {
 233         u16 chipid;
 234         const char *name;
 235 };
 236
 237 /*
 238  * This is a list of the Digital Baseband chips used in the U300 platform.
 239  */
 240 static struct db_chip db_chips[] __initdata = {
 241         {
 242                 .chipid = 0xb800,
 243                 .name = "DB3000",
 244         },
 245         {
 246                 .chipid = 0xc000,
 247                 .name = "DB3100",
 248         },
 249         {
 250                 .chipid = 0xc800,
 251                 .name = "DB3150",
 252         },
 253         {
 254                 .chipid = 0xd800,
 255                 .name = "DB3200",
 256         },
 257         {
 258                 .chipid = 0xe000,
 259                 .name = "DB3250",
 260         },
 261         {
 262                 .chipid = 0xe800,
 263                 .name = "DB3210",
 264         },
 265         {
 266                 .chipid = 0xf000,
 267                 .name = "DB3350 P1x",
 268         },
 269         {
 270                 .chipid = 0xf100,
 271                 .name = "DB3350 P2x",
 272         },
 273         {
 274                 .chipid = 0x0000, /* List terminator */
 275                 .name = NULL,
 276         }
 277 };
 278
 279 static void __init u300_init_check_chip(void)
 280 {
 281
 282         u16 val;
 283         struct db_chip *chip;
 284         const char *chipname;
 285         const char unknown[] = "UNKNOWN";
 286
 287         /* Read out and print chip ID */
 288         val = readw(syscon_base + U300_SYSCON_CIDR);
 289         /* This is in funky bigendian order... */
 290         val = (val & 0xFFU) << 8 | (val >> 8);
 291         chip = db_chips;
 292         chipname = unknown;
 293
 294         for ( ; chip->chipid; chip++) {
 295                 if (chip->chipid == (val & 0xFF00U)) {
 296                         chipname = chip->name;
 297                         break;
 298                 }
 299         }
 300         printk(KERN_INFO "Initializing U300 system on %s baseband chip " \
 301                "(chip ID 0x%04x)\n", chipname, val);
 302
 303         if ((val & 0xFF00U) != 0xf000 && (val & 0xFF00U) != 0xf100) {
 304                 printk(KERN_ERR "Platform configured for BS335 " \
 305                        " with DB3350 but %s detected, expect problems!",
 306                        chipname);
 307         }
 308 }
 309
 310 /* Forward declare this function from the watchdog */
 311 void coh901327_watchdog_reset(void);
 312
 313 static void u300_restart(char mode, const char *cmd)
 314 {
 315         switch (mode) {
 316         case 's':
 317         case 'h':
 318 #ifdef CONFIG_COH901327_WATCHDOG
 319                 coh901327_watchdog_reset();
 320 #endif
 321                 break;
 322         default:
 323                 /* Do nothing */
 324                 break;
 325         }
 326         /* Wait for system do die/reset. */
 327         while (1);
 328 }
 329
 330 /* These are mostly to get the right device names for the clock lookups */
 331 static struct of_dev_auxdata u300_auxdata_lookup[] __initdata = {
 332         OF_DEV_AUXDATA("stericsson,pinctrl-u300", U300_SYSCON_BASE,
 333                 "pinctrl-u300", NULL),
 334         OF_DEV_AUXDATA("stericsson,gpio-coh901", U300_GPIO_BASE,
 335                 "u300-gpio", &u300_gpio_plat),
 336         OF_DEV_AUXDATA("stericsson,coh901327", U300_WDOG_BASE,
 337                 "coh901327_wdog", NULL),
 338         OF_DEV_AUXDATA("stericsson,coh901331", U300_RTC_BASE,
 339                 "rtc-coh901331", NULL),
 340         OF_DEV_AUXDATA("stericsson,coh901318", U300_DMAC_BASE,
 341                 "coh901318", NULL),
 342         OF_DEV_AUXDATA("stericsson,fsmc-nand", U300_NAND_IF_PHYS_BASE,
 343                 "fsmc-nand", NULL),
 344         OF_DEV_AUXDATA("arm,primecell", U300_UART0_BASE,
 345                 "uart0", NULL),
 346         OF_DEV_AUXDATA("arm,primecell", U300_UART1_BASE,
 347                 "uart1", NULL),
 348         OF_DEV_AUXDATA("arm,primecell", U300_SPI_BASE,
 349                 "pl022", NULL),
 350         OF_DEV_AUXDATA("st,ddci2c", U300_I2C0_BASE,
 351                 "stu300.0", NULL),
 352         OF_DEV_AUXDATA("st,ddci2c", U300_I2C1_BASE,
 353                 "stu300.1", NULL),
 354         OF_DEV_AUXDATA("arm,primecell", U300_MMCSD_BASE,
 355                 "mmci", NULL),
 356         { /* sentinel */ },
 357 };
 358
 359 static void __init u300_init_irq_dt(void)
 360 {
 361         struct device_node *syscon;
 362         struct clk *clk;
 363
 364         syscon = of_find_node_by_path("/syscon@c0011000");
 365         if (!syscon) {
 366                 pr_crit("could not find syscon node\n");
 367                 return;
 368         }
 369         syscon_base = of_iomap(syscon, 0);
 370         if (!syscon_base) {
 371                 pr_crit("could not remap syscon\n");
 372                 return;
 373         }
 374         /* initialize clocking early, we want to clock the INTCON */
 375         u300_clk_init(syscon_base);
 376
 377         /* Bootstrap EMIF and SEMI clocks */
 378         clk = clk_get_sys("pl172", NULL);
 379         BUG_ON(IS_ERR(clk));
 380         clk_prepare_enable(clk);
 381         clk = clk_get_sys("semi", NULL);
 382         BUG_ON(IS_ERR(clk));
 383         clk_prepare_enable(clk);
 384
 385         /* Clock the interrupt controller */
 386         clk = clk_get_sys("intcon", NULL);
 387         BUG_ON(IS_ERR(clk));
 388         clk_prepare_enable(clk);
 389
 390         irqchip_init();
 391 }
 392
 393 static void __init u300_init_machine_dt(void)
 394 {
 395         u16 val;
 396
 397         /* Check what platform we run and print some status information */
 398         u300_init_check_chip();
 399
 400         /* Initialize pinmuxing */
 401         pinctrl_register_mappings(u300_pinmux_map,
 402                                   ARRAY_SIZE(u300_pinmux_map));
 403
 404         of_platform_populate(NULL, of_default_bus_match_table,
 405                         u300_auxdata_lookup, NULL);
 406
 407         /* Enable SEMI self refresh */
 408         val = readw(syscon_base + U300_SYSCON_SMCR) |
 409                 U300_SYSCON_SMCR_SEMI_SREFREQ_ENABLE;
 410         writew(val, syscon_base + U300_SYSCON_SMCR);
 411 }
 412
 413 static const char * u300_board_compat[] = {
 414         "stericsson,u300",
 415         NULL,
 416 };
 417
 418 DT_MACHINE_START(U300_DT, "U300 S335/B335 (Device Tree)")
 419         .map_io         = u300_map_io,
 420         .init_irq       = u300_init_irq_dt,
 421         .init_time      = clocksource_of_init,
 422         .init_machine   = u300_init_machine_dt,
 423         .restart        = u300_restart,
 424         .dt_compat      = u300_board_compat,
 425 MACHINE_END