arch/arm/mach-u300/core.c

   1 /*
   2  *
   3  * arch/arm/mach-u300/core.c
   4  *
   5  *
   6  * Copyright (C) 2007-2010 ST-Ericsson SA
   7  * License terms: GNU General Public License (GPL) version 2
   8  * Core platform support, IRQ handling and device definitions.
   9  * Author: Linus Walleij <linus.walleij@stericsson.com>
  10  */
  11 #include <linux/kernel.h>
  12 #include <linux/init.h>
  13 #include <linux/spinlock.h>
  14 #include <linux/interrupt.h>
  15 #include <linux/bitops.h>
  16 #include <linux/device.h>
  17 #include <linux/mm.h>
  18 #include <linux/termios.h>
  19 #include <linux/dmaengine.h>
  20 #include <linux/amba/bus.h>
  21 #include <linux/amba/serial.h>
  22 #include <linux/platform_device.h>
  23 #include <linux/gpio.h>
  24 #include <linux/clk.h>
  25 #include <linux/err.h>
  26 #include <linux/mtd/nand.h>
  27 #include <linux/mtd/fsmc.h>
  28 #include <linux/dma-mapping.h>
  29
  30 #include <asm/types.h>
  31 #include <asm/setup.h>
  32 #include <asm/memory.h>
  33 #include <asm/hardware/vic.h>
  34 #include <asm/mach/map.h>
  35 #include <asm/mach/irq.h>
  36
  37 #include <mach/coh901318.h>
  38 #include <mach/hardware.h>
  39 #include <mach/syscon.h>
  40 #include <mach/dma_channels.h>
  41
  42 #include "clock.h"
  43 #include "mmc.h"
  44 #include "spi.h"
  45 #include "i2c.h"
  46
  47 /*
  48  * Static I/O mappings that are needed for booting the U300 platforms. The
  49  * only things we need are the areas where we find the timer, syscon and
  50  * intcon, since the remaining device drivers will map their own memory
  51  * physical to virtual as the need arise.
  52  */
  53 static struct map_desc u300_io_desc[] __initdata = {
  54         {
  55                 .virtual        = U300_SLOW_PER_VIRT_BASE,
  56                 .pfn            = __phys_to_pfn(U300_SLOW_PER_PHYS_BASE),
  57                 .length         = SZ_64K,
  58                 .type           = MT_DEVICE,
  59         },
  60         {
  61                 .virtual        = U300_AHB_PER_VIRT_BASE,
  62                 .pfn            = __phys_to_pfn(U300_AHB_PER_PHYS_BASE),
  63                 .length         = SZ_32K,
  64                 .type           = MT_DEVICE,
  65         },
  66         {
  67                 .virtual        = U300_FAST_PER_VIRT_BASE,
  68                 .pfn            = __phys_to_pfn(U300_FAST_PER_PHYS_BASE),
  69                 .length         = SZ_32K,
  70                 .type           = MT_DEVICE,
  71         },
  72         {
  73                 .virtual        = 0xffff2000, /* TCM memory */
  74                 .pfn            = __phys_to_pfn(0xffff2000),
  75                 .length         = SZ_16K,
  76                 .type           = MT_DEVICE,
  77         },
  78
  79         /*
  80          * This overlaps with the IRQ vectors etc at 0xffff0000, so these
  81          * may have to be moved to 0x00000000 in order to use the ROM.
  82          */
  83         /*
  84         {
  85                 .virtual        = U300_BOOTROM_VIRT_BASE,
  86                 .pfn            = __phys_to_pfn(U300_BOOTROM_PHYS_BASE),
  87                 .length         = SZ_64K,
  88                 .type           = MT_ROM,
  89         },
  90         */
  91 };
  92
  93 void __init u300_map_io(void)
  94 {
  95         iotable_init(u300_io_desc, ARRAY_SIZE(u300_io_desc));
  96         /* We enable a real big DMA buffer if need be. */
  97         init_consistent_dma_size(SZ_4M);
  98 }
  99
 100 /*
 101  * Declaration of devices found on the U300 board and
 102  * their respective memory locations.
 103  */
 104
 105 static struct amba_pl011_data uart0_plat_data = {
 106 #ifdef CONFIG_COH901318
 107         .dma_filter = coh901318_filter_id,
 108         .dma_rx_param = (void *) U300_DMA_UART0_RX,
 109         .dma_tx_param = (void *) U300_DMA_UART0_TX,
 110 #endif
 111 };
 112
 113 static struct amba_device uart0_device = {
 114         .dev = {
 115                 .coherent_dma_mask = ~0,
 116                 .init_name = "uart0", /* Slow device at 0x3000 offset */
 117                 .platform_data = &uart0_plat_data,
 118         },
 119         .res = {
 120                 .start = U300_UART0_BASE,
 121                 .end   = U300_UART0_BASE + SZ_4K - 1,
 122                 .flags = IORESOURCE_MEM,
 123         },
 124         .irq = { IRQ_U300_UART0, NO_IRQ },
 125 };
 126
 127 /* The U335 have an additional UART1 on the APP CPU */
 128 #ifdef CONFIG_MACH_U300_BS335
 129 static struct amba_pl011_data uart1_plat_data = {
 130 #ifdef CONFIG_COH901318
 131         .dma_filter = coh901318_filter_id,
 132         .dma_rx_param = (void *) U300_DMA_UART1_RX,
 133         .dma_tx_param = (void *) U300_DMA_UART1_TX,
 134 #endif
 135 };
 136
 137 static struct amba_device uart1_device = {
 138         .dev = {
 139                 .coherent_dma_mask = ~0,
 140                 .init_name = "uart1", /* Fast device at 0x7000 offset */
 141                 .platform_data = &uart1_plat_data,
 142         },
 143         .res = {
 144                 .start = U300_UART1_BASE,
 145                 .end   = U300_UART1_BASE + SZ_4K - 1,
 146                 .flags = IORESOURCE_MEM,
 147         },
 148         .irq = { IRQ_U300_UART1, NO_IRQ },
 149 };
 150 #endif
 151
 152 static struct amba_device pl172_device = {
 153         .dev = {
 154                 .init_name = "pl172", /* AHB device at 0x4000 offset */
 155                 .platform_data = NULL,
 156         },
 157         .res = {
 158                 .start = U300_EMIF_CFG_BASE,
 159                 .end   = U300_EMIF_CFG_BASE + SZ_4K - 1,
 160                 .flags = IORESOURCE_MEM,
 161         },
 162 };
 163
 164
 165 /*
 166  * Everything within this next ifdef deals with external devices connected to
 167  * the APP SPI bus.
 168  */
 169 static struct amba_device pl022_device = {
 170         .dev = {
 171                 .coherent_dma_mask = ~0,
 172                 .init_name = "pl022", /* Fast device at 0x6000 offset */
 173         },
 174         .res = {
 175                 .start = U300_SPI_BASE,
 176                 .end   = U300_SPI_BASE + SZ_4K - 1,
 177                 .flags = IORESOURCE_MEM,
 178         },
 179         .irq = {IRQ_U300_SPI, NO_IRQ },
 180         /*
 181          * This device has a DMA channel but the Linux driver does not use
 182          * it currently.
 183          */
 184 };
 185
 186 static struct amba_device mmcsd_device = {
 187         .dev = {
 188                 .init_name = "mmci", /* Fast device at 0x1000 offset */
 189                 .platform_data = NULL, /* Added later */
 190         },
 191         .res = {
 192                 .start = U300_MMCSD_BASE,
 193                 .end   = U300_MMCSD_BASE + SZ_4K - 1,
 194                 .flags = IORESOURCE_MEM,
 195         },
 196         .irq = {IRQ_U300_MMCSD_MCIINTR0, IRQ_U300_MMCSD_MCIINTR1 },
 197         /*
 198          * This device has a DMA channel but the Linux driver does not use
 199          * it currently.
 200          */
 201 };
 202
 203 /*
 204  * The order of device declaration may be important, since some devices
 205  * have dependencies on other devices being initialized first.
 206  */
 207 static struct amba_device *amba_devs[] __initdata = {
 208         &uart0_device,
 209 #ifdef CONFIG_MACH_U300_BS335
 210         &uart1_device,
 211 #endif
 212         &pl022_device,
 213         &pl172_device,
 214         &mmcsd_device,
 215 };
 216
 217 /* Here follows a list of all hw resources that the platform devices
 218  * allocate. Note, clock dependencies are not included
 219  */
 220
 221 static struct resource gpio_resources[] = {
 222         {
 223                 .start = U300_GPIO_BASE,
 224                 .end   = (U300_GPIO_BASE + SZ_4K - 1),
 225                 .flags = IORESOURCE_MEM,
 226         },
 227         {
 228                 .name  = "gpio0",
 229                 .start = IRQ_U300_GPIO_PORT0,
 230                 .end   = IRQ_U300_GPIO_PORT0,
 231                 .flags = IORESOURCE_IRQ,
 232         },
 233         {
 234                 .name  = "gpio1",
 235                 .start = IRQ_U300_GPIO_PORT1,
 236                 .end   = IRQ_U300_GPIO_PORT1,
 237                 .flags = IORESOURCE_IRQ,
 238         },
 239         {
 240                 .name  = "gpio2",
 241                 .start = IRQ_U300_GPIO_PORT2,
 242                 .end   = IRQ_U300_GPIO_PORT2,
 243                 .flags = IORESOURCE_IRQ,
 244         },
 245 #ifdef U300_COH901571_3
 246         {
 247                 .name  = "gpio3",
 248                 .start = IRQ_U300_GPIO_PORT3,
 249                 .end   = IRQ_U300_GPIO_PORT3,
 250                 .flags = IORESOURCE_IRQ,
 251         },
 252         {
 253                 .name  = "gpio4",
 254                 .start = IRQ_U300_GPIO_PORT4,
 255                 .end   = IRQ_U300_GPIO_PORT4,
 256                 .flags = IORESOURCE_IRQ,
 257         },
 258 #ifdef CONFIG_MACH_U300_BS335
 259         {
 260                 .name  = "gpio5",
 261                 .start = IRQ_U300_GPIO_PORT5,
 262                 .end   = IRQ_U300_GPIO_PORT5,
 263                 .flags = IORESOURCE_IRQ,
 264         },
 265         {
 266                 .name  = "gpio6",
 267                 .start = IRQ_U300_GPIO_PORT6,
 268                 .end   = IRQ_U300_GPIO_PORT6,
 269                 .flags = IORESOURCE_IRQ,
 270         },
 271 #endif /* CONFIG_MACH_U300_BS335 */
 272 #endif /* U300_COH901571_3 */
 273 };
 274
 275 static struct resource keypad_resources[] = {
 276         {
 277                 .start = U300_KEYPAD_BASE,
 278                 .end   = U300_KEYPAD_BASE + SZ_4K - 1,
 279                 .flags = IORESOURCE_MEM,
 280         },
 281         {
 282                 .name  = "coh901461-press",
 283                 .start = IRQ_U300_KEYPAD_KEYBF,
 284                 .end   = IRQ_U300_KEYPAD_KEYBF,
 285                 .flags = IORESOURCE_IRQ,
 286         },
 287         {
 288                 .name  = "coh901461-release",
 289                 .start = IRQ_U300_KEYPAD_KEYBR,
 290                 .end   = IRQ_U300_KEYPAD_KEYBR,
 291                 .flags = IORESOURCE_IRQ,
 292         },
 293 };
 294
 295 static struct resource rtc_resources[] = {
 296         {
 297                 .start = U300_RTC_BASE,
 298                 .end   = U300_RTC_BASE + SZ_4K - 1,
 299                 .flags = IORESOURCE_MEM,
 300         },
 301         {
 302                 .start = IRQ_U300_RTC,
 303                 .end   = IRQ_U300_RTC,
 304                 .flags = IORESOURCE_IRQ,
 305         },
 306 };
 307
 308 /*
 309  * Fsmc does have IRQs: #43 and #44 (NFIF and NFIF2)
 310  * but these are not yet used by the driver.
 311  */
 312 static struct resource fsmc_resources[] = {
 313         {
 314                 .name  = "nand_data",
 315                 .start = U300_NAND_CS0_PHYS_BASE,
 316                 .end   = U300_NAND_CS0_PHYS_BASE + SZ_16K - 1,
 317                 .flags = IORESOURCE_MEM,
 318         },
 319         {
 320                 .name  = "fsmc_regs",
 321                 .start = U300_NAND_IF_PHYS_BASE,
 322                 .end   = U300_NAND_IF_PHYS_BASE + SZ_4K - 1,
 323                 .flags = IORESOURCE_MEM,
 324         },
 325 };
 326
 327 static struct resource i2c0_resources[] = {
 328         {
 329                 .start = U300_I2C0_BASE,
 330                 .end   = U300_I2C0_BASE + SZ_4K - 1,
 331                 .flags = IORESOURCE_MEM,
 332         },
 333         {
 334                 .start = IRQ_U300_I2C0,
 335                 .end   = IRQ_U300_I2C0,
 336                 .flags = IORESOURCE_IRQ,
 337         },
 338 };
 339
 340 static struct resource i2c1_resources[] = {
 341         {
 342                 .start = U300_I2C1_BASE,
 343                 .end   = U300_I2C1_BASE + SZ_4K - 1,
 344                 .flags = IORESOURCE_MEM,
 345         },
 346         {
 347                 .start = IRQ_U300_I2C1,
 348                 .end   = IRQ_U300_I2C1,
 349                 .flags = IORESOURCE_IRQ,
 350         },
 351
 352 };
 353
 354 static struct resource wdog_resources[] = {
 355         {
 356                 .start = U300_WDOG_BASE,
 357                 .end   = U300_WDOG_BASE + SZ_4K - 1,
 358                 .flags = IORESOURCE_MEM,
 359         },
 360         {
 361                 .start = IRQ_U300_WDOG,
 362                 .end   = IRQ_U300_WDOG,
 363                 .flags = IORESOURCE_IRQ,
 364         }
 365 };
 366
 367 /* TODO: These should be protected by suitable #ifdef's */
 368 static struct resource ave_resources[] = {
 369         {
 370                 .name  = "AVE3e I/O Area",
 371                 .start = U300_VIDEOENC_BASE,
 372                 .end   = U300_VIDEOENC_BASE + SZ_512K - 1,
 373                 .flags = IORESOURCE_MEM,
 374         },
 375         {
 376                 .name  = "AVE3e IRQ0",
 377                 .start = IRQ_U300_VIDEO_ENC_0,
 378                 .end   = IRQ_U300_VIDEO_ENC_0,
 379                 .flags = IORESOURCE_IRQ,
 380         },
 381         {
 382                 .name  = "AVE3e IRQ1",
 383                 .start = IRQ_U300_VIDEO_ENC_1,
 384                 .end   = IRQ_U300_VIDEO_ENC_1,
 385                 .flags = IORESOURCE_IRQ,
 386         },
 387         {
 388                 .name  = "AVE3e Physmem Area",
 389                 .start = 0, /* 0 will be remapped to reserved memory */
 390                 .end   = SZ_1M - 1,
 391                 .flags = IORESOURCE_MEM,
 392         },
 393         /*
 394          * The AVE3e requires two regions of 256MB that it considers
 395          * "invisible". The hardware will not be able to access these
 396          * addresses, so they should never point to system RAM.
 397          */
 398         {
 399                 .name  = "AVE3e Reserved 0",
 400                 .start = 0xd0000000,
 401                 .end   = 0xd0000000 + SZ_256M - 1,
 402                 .flags = IORESOURCE_MEM,
 403         },
 404         {
 405                 .name  = "AVE3e Reserved 1",
 406                 .start = 0xe0000000,
 407                 .end   = 0xe0000000 + SZ_256M - 1,
 408                 .flags = IORESOURCE_MEM,
 409         },
 410 };
 411
 412 static struct resource dma_resource[] = {
 413         {
 414                 .start = U300_DMAC_BASE,
 415                 .end = U300_DMAC_BASE + PAGE_SIZE - 1,
 416                 .flags =  IORESOURCE_MEM,
 417         },
 418         {
 419                 .start = IRQ_U300_DMA,
 420                 .end = IRQ_U300_DMA,
 421                 .flags =  IORESOURCE_IRQ,
 422         }
 423 };
 424
 425 #ifdef CONFIG_MACH_U300_BS335
 426 /* points out all dma slave channels.
 427  * Syntax is [A1, B1, A2, B2, .... ,-1,-1]
 428  * Select all channels from A to B, end of list is marked with -1,-1
 429  */
 430 static int dma_slave_channels[] = {
 431         U300_DMA_MSL_TX_0, U300_DMA_SPI_RX,
 432         U300_DMA_UART1_TX, U300_DMA_UART1_RX, -1, -1};
 433
 434 /* points out all dma memcpy channels. */
 435 static int dma_memcpy_channels[] = {
 436         U300_DMA_GENERAL_PURPOSE_0, U300_DMA_GENERAL_PURPOSE_8, -1, -1};
 437
 438 #else /* CONFIG_MACH_U300_BS335 */
 439
 440 static int dma_slave_channels[] = {U300_DMA_MSL_TX_0, U300_DMA_SPI_RX, -1, -1};
 441 static int dma_memcpy_channels[] = {
 442         U300_DMA_GENERAL_PURPOSE_0, U300_DMA_GENERAL_PURPOSE_10, -1, -1};
 443
 444 #endif
 445
 446 /** register dma for memory access
 447  *
 448  * active  1 means dma intends to access memory
 449  *         0 means dma wont access memory
 450  */
 451 static void coh901318_access_memory_state(struct device *dev, bool active)
 452 {
 453 }
 454
 455 #define flags_memcpy_config (COH901318_CX_CFG_CH_DISABLE | \
 456                         COH901318_CX_CFG_RM_MEMORY_TO_MEMORY | \
 457                         COH901318_CX_CFG_LCR_DISABLE | \
 458                         COH901318_CX_CFG_TC_IRQ_ENABLE | \
 459                         COH901318_CX_CFG_BE_IRQ_ENABLE)
 460 #define flags_memcpy_lli_chained (COH901318_CX_CTRL_TC_ENABLE | \
 461                         COH901318_CX_CTRL_BURST_COUNT_32_BYTES | \
 462                         COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | \
 463                         COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE | \
 464                         COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | \
 465                         COH901318_CX_CTRL_DST_ADDR_INC_ENABLE | \
 466                         COH901318_CX_CTRL_MASTER_MODE_M1RW | \
 467                         COH901318_CX_CTRL_TCP_DISABLE | \
 468                         COH901318_CX_CTRL_TC_IRQ_DISABLE | \
 469                         COH901318_CX_CTRL_HSP_DISABLE | \
 470                         COH901318_CX_CTRL_HSS_DISABLE | \
 471                         COH901318_CX_CTRL_DDMA_LEGACY | \
 472                         COH901318_CX_CTRL_PRDD_SOURCE)
 473 #define flags_memcpy_lli (COH901318_CX_CTRL_TC_ENABLE | \
 474                         COH901318_CX_CTRL_BURST_COUNT_32_BYTES | \
 475                         COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | \
 476                         COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE | \
 477                         COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | \
 478                         COH901318_CX_CTRL_DST_ADDR_INC_ENABLE | \
 479                         COH901318_CX_CTRL_MASTER_MODE_M1RW | \
 480                         COH901318_CX_CTRL_TCP_DISABLE | \
 481                         COH901318_CX_CTRL_TC_IRQ_DISABLE | \
 482                         COH901318_CX_CTRL_HSP_DISABLE | \
 483                         COH901318_CX_CTRL_HSS_DISABLE | \
 484                         COH901318_CX_CTRL_DDMA_LEGACY | \
 485                         COH901318_CX_CTRL_PRDD_SOURCE)
 486 #define flags_memcpy_lli_last (COH901318_CX_CTRL_TC_ENABLE | \
 487                         COH901318_CX_CTRL_BURST_COUNT_32_BYTES | \
 488                         COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | \
 489                         COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE | \
 490                         COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | \
 491                         COH901318_CX_CTRL_DST_ADDR_INC_ENABLE | \
 492                         COH901318_CX_CTRL_MASTER_MODE_M1RW | \
 493                         COH901318_CX_CTRL_TCP_DISABLE | \
 494                         COH901318_CX_CTRL_TC_IRQ_ENABLE | \
 495                         COH901318_CX_CTRL_HSP_DISABLE | \
 496                         COH901318_CX_CTRL_HSS_DISABLE | \
 497                         COH901318_CX_CTRL_DDMA_LEGACY | \
 498                         COH901318_CX_CTRL_PRDD_SOURCE)
 499
 500 const struct coh_dma_channel chan_config[U300_DMA_CHANNELS] = {
 501         {
 502                 .number = U300_DMA_MSL_TX_0,
 503                 .name = "MSL TX 0",
 504                 .priority_high = 0,
 505                 .dev_addr = U300_MSL_BASE + 0 * 0x40 + 0x20,
 506         },
 507         {
 508                 .number = U300_DMA_MSL_TX_1,
 509                 .name = "MSL TX 1",
 510                 .priority_high = 0,
 511                 .dev_addr = U300_MSL_BASE + 1 * 0x40 + 0x20,
 512                 .param.config = COH901318_CX_CFG_CH_DISABLE |
 513                                 COH901318_CX_CFG_LCR_DISABLE |
 514                                 COH901318_CX_CFG_TC_IRQ_ENABLE |
 515                                 COH901318_CX_CFG_BE_IRQ_ENABLE,
 516                 .param.ctrl_lli_chained = 0 |
 517                                 COH901318_CX_CTRL_TC_ENABLE |
 518                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 519                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 520                                 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
 521                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 522                                 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
 523                                 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
 524                                 COH901318_CX_CTRL_TCP_DISABLE |
 525                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
 526                                 COH901318_CX_CTRL_HSP_ENABLE |
 527                                 COH901318_CX_CTRL_HSS_DISABLE |
 528                                 COH901318_CX_CTRL_DDMA_LEGACY |
 529                                 COH901318_CX_CTRL_PRDD_SOURCE,
 530                 .param.ctrl_lli = 0 |
 531                                 COH901318_CX_CTRL_TC_ENABLE |
 532                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 533                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 534                                 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
 535                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 536                                 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
 537                                 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
 538                                 COH901318_CX_CTRL_TCP_ENABLE |
 539                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
 540                                 COH901318_CX_CTRL_HSP_ENABLE |
 541                                 COH901318_CX_CTRL_HSS_DISABLE |
 542                                 COH901318_CX_CTRL_DDMA_LEGACY |
 543                                 COH901318_CX_CTRL_PRDD_SOURCE,
 544                 .param.ctrl_lli_last = 0 |
 545                                 COH901318_CX_CTRL_TC_ENABLE |
 546                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 547                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 548                                 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
 549                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 550                                 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
 551                                 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
 552                                 COH901318_CX_CTRL_TCP_ENABLE |
 553                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
 554                                 COH901318_CX_CTRL_HSP_ENABLE |
 555                                 COH901318_CX_CTRL_HSS_DISABLE |
 556                                 COH901318_CX_CTRL_DDMA_LEGACY |
 557                                 COH901318_CX_CTRL_PRDD_SOURCE,
 558         },
 559         {
 560                 .number = U300_DMA_MSL_TX_2,
 561                 .name = "MSL TX 2",
 562                 .priority_high = 0,
 563                 .dev_addr = U300_MSL_BASE + 2 * 0x40 + 0x20,
 564                 .param.config = COH901318_CX_CFG_CH_DISABLE |
 565                                 COH901318_CX_CFG_LCR_DISABLE |
 566                                 COH901318_CX_CFG_TC_IRQ_ENABLE |
 567                                 COH901318_CX_CFG_BE_IRQ_ENABLE,
 568                 .param.ctrl_lli_chained = 0 |
 569                                 COH901318_CX_CTRL_TC_ENABLE |
 570                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 571                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 572                                 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
 573                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 574                                 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
 575                                 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
 576                                 COH901318_CX_CTRL_TCP_DISABLE |
 577                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
 578                                 COH901318_CX_CTRL_HSP_ENABLE |
 579                                 COH901318_CX_CTRL_HSS_DISABLE |
 580                                 COH901318_CX_CTRL_DDMA_LEGACY |
 581                                 COH901318_CX_CTRL_PRDD_SOURCE,
 582                 .param.ctrl_lli = 0 |
 583                                 COH901318_CX_CTRL_TC_ENABLE |
 584                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 585                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 586                                 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
 587                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 588                                 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
 589                                 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
 590                                 COH901318_CX_CTRL_TCP_ENABLE |
 591                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
 592                                 COH901318_CX_CTRL_HSP_ENABLE |
 593                                 COH901318_CX_CTRL_HSS_DISABLE |
 594                                 COH901318_CX_CTRL_DDMA_LEGACY |
 595                                 COH901318_CX_CTRL_PRDD_SOURCE,
 596                 .param.ctrl_lli_last = 0 |
 597                                 COH901318_CX_CTRL_TC_ENABLE |
 598                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 599                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 600                                 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
 601                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 602                                 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
 603                                 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
 604                                 COH901318_CX_CTRL_TCP_ENABLE |
 605                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
 606                                 COH901318_CX_CTRL_HSP_ENABLE |
 607                                 COH901318_CX_CTRL_HSS_DISABLE |
 608                                 COH901318_CX_CTRL_DDMA_LEGACY |
 609                                 COH901318_CX_CTRL_PRDD_SOURCE,
 610                 .desc_nbr_max = 10,
 611         },
 612         {
 613                 .number = U300_DMA_MSL_TX_3,
 614                 .name = "MSL TX 3",
 615                 .priority_high = 0,
 616                 .dev_addr = U300_MSL_BASE + 3 * 0x40 + 0x20,
 617                 .param.config = COH901318_CX_CFG_CH_DISABLE |
 618                                 COH901318_CX_CFG_LCR_DISABLE |
 619                                 COH901318_CX_CFG_TC_IRQ_ENABLE |
 620                                 COH901318_CX_CFG_BE_IRQ_ENABLE,
 621                 .param.ctrl_lli_chained = 0 |
 622                                 COH901318_CX_CTRL_TC_ENABLE |
 623                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 624                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 625                                 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
 626                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 627                                 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
 628                                 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
 629                                 COH901318_CX_CTRL_TCP_DISABLE |
 630                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
 631                                 COH901318_CX_CTRL_HSP_ENABLE |
 632                                 COH901318_CX_CTRL_HSS_DISABLE |
 633                                 COH901318_CX_CTRL_DDMA_LEGACY |
 634                                 COH901318_CX_CTRL_PRDD_SOURCE,
 635                 .param.ctrl_lli = 0 |
 636                                 COH901318_CX_CTRL_TC_ENABLE |
 637                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 638                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 639                                 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
 640                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 641                                 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
 642                                 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
 643                                 COH901318_CX_CTRL_TCP_ENABLE |
 644                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
 645                                 COH901318_CX_CTRL_HSP_ENABLE |
 646                                 COH901318_CX_CTRL_HSS_DISABLE |
 647                                 COH901318_CX_CTRL_DDMA_LEGACY |
 648                                 COH901318_CX_CTRL_PRDD_SOURCE,
 649                 .param.ctrl_lli_last = 0 |
 650                                 COH901318_CX_CTRL_TC_ENABLE |
 651                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 652                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 653                                 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
 654                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 655                                 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
 656                                 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
 657                                 COH901318_CX_CTRL_TCP_ENABLE |
 658                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
 659                                 COH901318_CX_CTRL_HSP_ENABLE |
 660                                 COH901318_CX_CTRL_HSS_DISABLE |
 661                                 COH901318_CX_CTRL_DDMA_LEGACY |
 662                                 COH901318_CX_CTRL_PRDD_SOURCE,
 663         },
 664         {
 665                 .number = U300_DMA_MSL_TX_4,
 666                 .name = "MSL TX 4",
 667                 .priority_high = 0,
 668                 .dev_addr = U300_MSL_BASE + 4 * 0x40 + 0x20,
 669                 .param.config = COH901318_CX_CFG_CH_DISABLE |
 670                                 COH901318_CX_CFG_LCR_DISABLE |
 671                                 COH901318_CX_CFG_TC_IRQ_ENABLE |
 672                                 COH901318_CX_CFG_BE_IRQ_ENABLE,
 673                 .param.ctrl_lli_chained = 0 |
 674                                 COH901318_CX_CTRL_TC_ENABLE |
 675                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 676                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 677                                 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
 678                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 679                                 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
 680                                 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
 681                                 COH901318_CX_CTRL_TCP_DISABLE |
 682                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
 683                                 COH901318_CX_CTRL_HSP_ENABLE |
 684                                 COH901318_CX_CTRL_HSS_DISABLE |
 685                                 COH901318_CX_CTRL_DDMA_LEGACY |
 686                                 COH901318_CX_CTRL_PRDD_SOURCE,
 687                 .param.ctrl_lli = 0 |
 688                                 COH901318_CX_CTRL_TC_ENABLE |
 689                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 690                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 691                                 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
 692                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 693                                 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
 694                                 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
 695                                 COH901318_CX_CTRL_TCP_ENABLE |
 696                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
 697                                 COH901318_CX_CTRL_HSP_ENABLE |
 698                                 COH901318_CX_CTRL_HSS_DISABLE |
 699                                 COH901318_CX_CTRL_DDMA_LEGACY |
 700                                 COH901318_CX_CTRL_PRDD_SOURCE,
 701                 .param.ctrl_lli_last = 0 |
 702                                 COH901318_CX_CTRL_TC_ENABLE |
 703                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 704                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 705                                 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
 706                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 707                                 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
 708                                 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
 709                                 COH901318_CX_CTRL_TCP_ENABLE |
 710                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
 711                                 COH901318_CX_CTRL_HSP_ENABLE |
 712                                 COH901318_CX_CTRL_HSS_DISABLE |
 713                                 COH901318_CX_CTRL_DDMA_LEGACY |
 714                                 COH901318_CX_CTRL_PRDD_SOURCE,
 715         },
 716         {
 717                 .number = U300_DMA_MSL_TX_5,
 718                 .name = "MSL TX 5",
 719                 .priority_high = 0,
 720                 .dev_addr = U300_MSL_BASE + 5 * 0x40 + 0x20,
 721         },
 722         {
 723                 .number = U300_DMA_MSL_TX_6,
 724                 .name = "MSL TX 6",
 725                 .priority_high = 0,
 726                 .dev_addr = U300_MSL_BASE + 6 * 0x40 + 0x20,
 727         },
 728         {
 729                 .number = U300_DMA_MSL_RX_0,
 730                 .name = "MSL RX 0",
 731                 .priority_high = 0,
 732                 .dev_addr = U300_MSL_BASE + 0 * 0x40 + 0x220,
 733         },
 734         {
 735                 .number = U300_DMA_MSL_RX_1,
 736                 .name = "MSL RX 1",
 737                 .priority_high = 0,
 738                 .dev_addr = U300_MSL_BASE + 1 * 0x40 + 0x220,
 739                 .param.config = COH901318_CX_CFG_CH_DISABLE |
 740                                 COH901318_CX_CFG_LCR_DISABLE |
 741                                 COH901318_CX_CFG_TC_IRQ_ENABLE |
 742                                 COH901318_CX_CFG_BE_IRQ_ENABLE,
 743                 .param.ctrl_lli_chained = 0 |
 744                                 COH901318_CX_CTRL_TC_ENABLE |
 745                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 746                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 747                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
 748                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 749                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
 750                                 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
 751                                 COH901318_CX_CTRL_TCP_DISABLE |
 752                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
 753                                 COH901318_CX_CTRL_HSP_ENABLE |
 754                                 COH901318_CX_CTRL_HSS_DISABLE |
 755                                 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
 756                                 COH901318_CX_CTRL_PRDD_DEST,
 757                 .param.ctrl_lli = 0,
 758                 .param.ctrl_lli_last = 0 |
 759                                 COH901318_CX_CTRL_TC_ENABLE |
 760                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 761                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 762                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
 763                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 764                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
 765                                 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
 766                                 COH901318_CX_CTRL_TCP_DISABLE |
 767                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
 768                                 COH901318_CX_CTRL_HSP_ENABLE |
 769                                 COH901318_CX_CTRL_HSS_DISABLE |
 770                                 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
 771                                 COH901318_CX_CTRL_PRDD_DEST,
 772         },
 773         {
 774                 .number = U300_DMA_MSL_RX_2,
 775                 .name = "MSL RX 2",
 776                 .priority_high = 0,
 777                 .dev_addr = U300_MSL_BASE + 2 * 0x40 + 0x220,
 778                 .param.config = COH901318_CX_CFG_CH_DISABLE |
 779                                 COH901318_CX_CFG_LCR_DISABLE |
 780                                 COH901318_CX_CFG_TC_IRQ_ENABLE |
 781                                 COH901318_CX_CFG_BE_IRQ_ENABLE,
 782                 .param.ctrl_lli_chained = 0 |
 783                                 COH901318_CX_CTRL_TC_ENABLE |
 784                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 785                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 786                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
 787                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 788                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
 789                                 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
 790                                 COH901318_CX_CTRL_TCP_DISABLE |
 791                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
 792                                 COH901318_CX_CTRL_HSP_ENABLE |
 793                                 COH901318_CX_CTRL_HSS_DISABLE |
 794                                 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
 795                                 COH901318_CX_CTRL_PRDD_DEST,
 796                 .param.ctrl_lli = 0 |
 797                                 COH901318_CX_CTRL_TC_ENABLE |
 798                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 799                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 800                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
 801                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 802                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
 803                                 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
 804                                 COH901318_CX_CTRL_TCP_DISABLE |
 805                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
 806                                 COH901318_CX_CTRL_HSP_ENABLE |
 807                                 COH901318_CX_CTRL_HSS_DISABLE |
 808                                 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
 809                                 COH901318_CX_CTRL_PRDD_DEST,
 810                 .param.ctrl_lli_last = 0 |
 811                                 COH901318_CX_CTRL_TC_ENABLE |
 812                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 813                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 814                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
 815                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 816                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
 817                                 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
 818                                 COH901318_CX_CTRL_TCP_DISABLE |
 819                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
 820                                 COH901318_CX_CTRL_HSP_ENABLE |
 821                                 COH901318_CX_CTRL_HSS_DISABLE |
 822                                 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
 823                                 COH901318_CX_CTRL_PRDD_DEST,
 824         },
 825         {
 826                 .number = U300_DMA_MSL_RX_3,
 827                 .name = "MSL RX 3",
 828                 .priority_high = 0,
 829                 .dev_addr = U300_MSL_BASE + 3 * 0x40 + 0x220,
 830                 .param.config = COH901318_CX_CFG_CH_DISABLE |
 831                                 COH901318_CX_CFG_LCR_DISABLE |
 832                                 COH901318_CX_CFG_TC_IRQ_ENABLE |
 833                                 COH901318_CX_CFG_BE_IRQ_ENABLE,
 834                 .param.ctrl_lli_chained = 0 |
 835                                 COH901318_CX_CTRL_TC_ENABLE |
 836                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 837                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 838                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
 839                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 840                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
 841                                 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
 842                                 COH901318_CX_CTRL_TCP_DISABLE |
 843                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
 844                                 COH901318_CX_CTRL_HSP_ENABLE |
 845                                 COH901318_CX_CTRL_HSS_DISABLE |
 846                                 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
 847                                 COH901318_CX_CTRL_PRDD_DEST,
 848                 .param.ctrl_lli = 0 |
 849                                 COH901318_CX_CTRL_TC_ENABLE |
 850                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 851                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 852                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
 853                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 854                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
 855                                 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
 856                                 COH901318_CX_CTRL_TCP_DISABLE |
 857                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
 858                                 COH901318_CX_CTRL_HSP_ENABLE |
 859                                 COH901318_CX_CTRL_HSS_DISABLE |
 860                                 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
 861                                 COH901318_CX_CTRL_PRDD_DEST,
 862                 .param.ctrl_lli_last = 0 |
 863                                 COH901318_CX_CTRL_TC_ENABLE |
 864                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 865                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 866                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
 867                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 868                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
 869                                 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
 870                                 COH901318_CX_CTRL_TCP_DISABLE |
 871                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
 872                                 COH901318_CX_CTRL_HSP_ENABLE |
 873                                 COH901318_CX_CTRL_HSS_DISABLE |
 874                                 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
 875                                 COH901318_CX_CTRL_PRDD_DEST,
 876         },
 877         {
 878                 .number = U300_DMA_MSL_RX_4,
 879                 .name = "MSL RX 4",
 880                 .priority_high = 0,
 881                 .dev_addr = U300_MSL_BASE + 4 * 0x40 + 0x220,
 882                 .param.config = COH901318_CX_CFG_CH_DISABLE |
 883                                 COH901318_CX_CFG_LCR_DISABLE |
 884                                 COH901318_CX_CFG_TC_IRQ_ENABLE |
 885                                 COH901318_CX_CFG_BE_IRQ_ENABLE,
 886                 .param.ctrl_lli_chained = 0 |
 887                                 COH901318_CX_CTRL_TC_ENABLE |
 888                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 889                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 890                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
 891                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 892                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
 893                                 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
 894                                 COH901318_CX_CTRL_TCP_DISABLE |
 895                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
 896                                 COH901318_CX_CTRL_HSP_ENABLE |
 897                                 COH901318_CX_CTRL_HSS_DISABLE |
 898                                 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
 899                                 COH901318_CX_CTRL_PRDD_DEST,
 900                 .param.ctrl_lli = 0 |
 901                                 COH901318_CX_CTRL_TC_ENABLE |
 902                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 903                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 904                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
 905                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 906                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
 907                                 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
 908                                 COH901318_CX_CTRL_TCP_DISABLE |
 909                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
 910                                 COH901318_CX_CTRL_HSP_ENABLE |
 911                                 COH901318_CX_CTRL_HSS_DISABLE |
 912                                 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
 913                                 COH901318_CX_CTRL_PRDD_DEST,
 914                 .param.ctrl_lli_last = 0 |
 915                                 COH901318_CX_CTRL_TC_ENABLE |
 916                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 917                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 918                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
 919                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 920                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
 921                                 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
 922                                 COH901318_CX_CTRL_TCP_DISABLE |
 923                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
 924                                 COH901318_CX_CTRL_HSP_ENABLE |
 925                                 COH901318_CX_CTRL_HSS_DISABLE |
 926                                 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
 927                                 COH901318_CX_CTRL_PRDD_DEST,
 928         },
 929         {
 930                 .number = U300_DMA_MSL_RX_5,
 931                 .name = "MSL RX 5",
 932                 .priority_high = 0,
 933                 .dev_addr = U300_MSL_BASE + 5 * 0x40 + 0x220,
 934                 .param.config = COH901318_CX_CFG_CH_DISABLE |
 935                                 COH901318_CX_CFG_LCR_DISABLE |
 936                                 COH901318_CX_CFG_TC_IRQ_ENABLE |
 937                                 COH901318_CX_CFG_BE_IRQ_ENABLE,
 938                 .param.ctrl_lli_chained = 0 |
 939                                 COH901318_CX_CTRL_TC_ENABLE |
 940                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 941                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 942                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
 943                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 944                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
 945                                 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
 946                                 COH901318_CX_CTRL_TCP_DISABLE |
 947                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
 948                                 COH901318_CX_CTRL_HSP_ENABLE |
 949                                 COH901318_CX_CTRL_HSS_DISABLE |
 950                                 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
 951                                 COH901318_CX_CTRL_PRDD_DEST,
 952                 .param.ctrl_lli = 0 |
 953                                 COH901318_CX_CTRL_TC_ENABLE |
 954                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 955                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 956                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
 957                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 958                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
 959                                 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
 960                                 COH901318_CX_CTRL_TCP_DISABLE |
 961                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
 962                                 COH901318_CX_CTRL_HSP_ENABLE |
 963                                 COH901318_CX_CTRL_HSS_DISABLE |
 964                                 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
 965                                 COH901318_CX_CTRL_PRDD_DEST,
 966                 .param.ctrl_lli_last = 0 |
 967                                 COH901318_CX_CTRL_TC_ENABLE |
 968                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 969                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 970                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
 971                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 972                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
 973                                 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
 974                                 COH901318_CX_CTRL_TCP_DISABLE |
 975                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
 976                                 COH901318_CX_CTRL_HSP_ENABLE |
 977                                 COH901318_CX_CTRL_HSS_DISABLE |
 978                                 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
 979                                 COH901318_CX_CTRL_PRDD_DEST,
 980         },
 981         {
 982                 .number = U300_DMA_MSL_RX_6,
 983                 .name = "MSL RX 6",
 984                 .priority_high = 0,
 985                 .dev_addr = U300_MSL_BASE + 6 * 0x40 + 0x220,
 986         },
 987         /*
 988          * Don't set up device address, burst count or size of src
 989          * or dst bus for this peripheral - handled by PrimeCell
 990          * DMA extension.
 991          */
 992         {
 993                 .number = U300_DMA_MMCSD_RX_TX,
 994                 .name = "MMCSD RX TX",
 995                 .priority_high = 0,
 996                 .param.config = COH901318_CX_CFG_CH_DISABLE |
 997                                 COH901318_CX_CFG_LCR_DISABLE |
 998                                 COH901318_CX_CFG_TC_IRQ_ENABLE |
 999                                 COH901318_CX_CFG_BE_IRQ_ENABLE,
1000                 .param.ctrl_lli_chained = 0 |
1001                                 COH901318_CX_CTRL_TC_ENABLE |
1002                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1003                                 COH901318_CX_CTRL_TCP_ENABLE |
1004                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1005                                 COH901318_CX_CTRL_HSP_ENABLE |
1006                                 COH901318_CX_CTRL_HSS_DISABLE |
1007                                 COH901318_CX_CTRL_DDMA_LEGACY,
1008                 .param.ctrl_lli = 0 |
1009                                 COH901318_CX_CTRL_TC_ENABLE |
1010                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1011                                 COH901318_CX_CTRL_TCP_ENABLE |
1012                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1013                                 COH901318_CX_CTRL_HSP_ENABLE |
1014                                 COH901318_CX_CTRL_HSS_DISABLE |
1015                                 COH901318_CX_CTRL_DDMA_LEGACY,
1016                 .param.ctrl_lli_last = 0 |
1017                                 COH901318_CX_CTRL_TC_ENABLE |
1018                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1019                                 COH901318_CX_CTRL_TCP_DISABLE |
1020                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
1021                                 COH901318_CX_CTRL_HSP_ENABLE |
1022                                 COH901318_CX_CTRL_HSS_DISABLE |
1023                                 COH901318_CX_CTRL_DDMA_LEGACY,
1024
1025         },
1026         {
1027                 .number = U300_DMA_MSPRO_TX,
1028                 .name = "MSPRO TX",
1029                 .priority_high = 0,
1030         },
1031         {
1032                 .number = U300_DMA_MSPRO_RX,
1033                 .name = "MSPRO RX",
1034                 .priority_high = 0,
1035         },
1036         /*
1037          * Don't set up device address, burst count or size of src
1038          * or dst bus for this peripheral - handled by PrimeCell
1039          * DMA extension.
1040          */
1041         {
1042                 .number = U300_DMA_UART0_TX,
1043                 .name = "UART0 TX",
1044                 .priority_high = 0,
1045                 .param.config = COH901318_CX_CFG_CH_DISABLE |
1046                                 COH901318_CX_CFG_LCR_DISABLE |
1047                                 COH901318_CX_CFG_TC_IRQ_ENABLE |
1048                                 COH901318_CX_CFG_BE_IRQ_ENABLE,
1049                 .param.ctrl_lli_chained = 0 |
1050                                 COH901318_CX_CTRL_TC_ENABLE |
1051                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1052                                 COH901318_CX_CTRL_TCP_ENABLE |
1053                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1054                                 COH901318_CX_CTRL_HSP_ENABLE |
1055                                 COH901318_CX_CTRL_HSS_DISABLE |
1056                                 COH901318_CX_CTRL_DDMA_LEGACY,
1057                 .param.ctrl_lli = 0 |
1058                                 COH901318_CX_CTRL_TC_ENABLE |
1059                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1060                                 COH901318_CX_CTRL_TCP_ENABLE |
1061                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
1062                                 COH901318_CX_CTRL_HSP_ENABLE |
1063                                 COH901318_CX_CTRL_HSS_DISABLE |
1064                                 COH901318_CX_CTRL_DDMA_LEGACY,
1065                 .param.ctrl_lli_last = 0 |
1066                                 COH901318_CX_CTRL_TC_ENABLE |
1067                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1068                                 COH901318_CX_CTRL_TCP_ENABLE |
1069                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
1070                                 COH901318_CX_CTRL_HSP_ENABLE |
1071                                 COH901318_CX_CTRL_HSS_DISABLE |
1072                                 COH901318_CX_CTRL_DDMA_LEGACY,
1073         },
1074         {
1075                 .number = U300_DMA_UART0_RX,
1076                 .name = "UART0 RX",
1077                 .priority_high = 0,
1078                 .param.config = COH901318_CX_CFG_CH_DISABLE |
1079                                 COH901318_CX_CFG_LCR_DISABLE |
1080                                 COH901318_CX_CFG_TC_IRQ_ENABLE |
1081                                 COH901318_CX_CFG_BE_IRQ_ENABLE,
1082                 .param.ctrl_lli_chained = 0 |
1083                                 COH901318_CX_CTRL_TC_ENABLE |
1084                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1085                                 COH901318_CX_CTRL_TCP_ENABLE |
1086                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1087                                 COH901318_CX_CTRL_HSP_ENABLE |
1088                                 COH901318_CX_CTRL_HSS_DISABLE |
1089                                 COH901318_CX_CTRL_DDMA_LEGACY,
1090                 .param.ctrl_lli = 0 |
1091                                 COH901318_CX_CTRL_TC_ENABLE |
1092                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1093                                 COH901318_CX_CTRL_TCP_ENABLE |
1094                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
1095                                 COH901318_CX_CTRL_HSP_ENABLE |
1096                                 COH901318_CX_CTRL_HSS_DISABLE |
1097                                 COH901318_CX_CTRL_DDMA_LEGACY,
1098                 .param.ctrl_lli_last = 0 |
1099                                 COH901318_CX_CTRL_TC_ENABLE |
1100                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1101                                 COH901318_CX_CTRL_TCP_ENABLE |
1102                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
1103                                 COH901318_CX_CTRL_HSP_ENABLE |
1104                                 COH901318_CX_CTRL_HSS_DISABLE |
1105                                 COH901318_CX_CTRL_DDMA_LEGACY,
1106         },
1107         {
1108                 .number = U300_DMA_APEX_TX,
1109                 .name = "APEX TX",
1110                 .priority_high = 0,
1111         },
1112         {
1113                 .number = U300_DMA_APEX_RX,
1114                 .name = "APEX RX",
1115                 .priority_high = 0,
1116         },
1117         {
1118                 .number = U300_DMA_PCM_I2S0_TX,
1119                 .name = "PCM I2S0 TX",
1120                 .priority_high = 1,
1121                 .dev_addr = U300_PCM_I2S0_BASE + 0x14,
1122                 .param.config = COH901318_CX_CFG_CH_DISABLE |
1123                                 COH901318_CX_CFG_LCR_DISABLE |
1124                                 COH901318_CX_CFG_TC_IRQ_ENABLE |
1125                                 COH901318_CX_CFG_BE_IRQ_ENABLE,
1126                 .param.ctrl_lli_chained = 0 |
1127                                 COH901318_CX_CTRL_TC_ENABLE |
1128                                 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1129                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1130                                 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
1131                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1132                                 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
1133                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1134                                 COH901318_CX_CTRL_TCP_DISABLE |
1135                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1136                                 COH901318_CX_CTRL_HSP_ENABLE |
1137                                 COH901318_CX_CTRL_HSS_DISABLE |
1138                                 COH901318_CX_CTRL_DDMA_LEGACY |
1139                                 COH901318_CX_CTRL_PRDD_SOURCE,
1140                 .param.ctrl_lli = 0 |
1141                                 COH901318_CX_CTRL_TC_ENABLE |
1142                                 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1143                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1144                                 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
1145                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1146                                 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
1147                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1148                                 COH901318_CX_CTRL_TCP_ENABLE |
1149                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1150                                 COH901318_CX_CTRL_HSP_ENABLE |
1151                                 COH901318_CX_CTRL_HSS_DISABLE |
1152                                 COH901318_CX_CTRL_DDMA_LEGACY |
1153                                 COH901318_CX_CTRL_PRDD_SOURCE,
1154                 .param.ctrl_lli_last = 0 |
1155                                 COH901318_CX_CTRL_TC_ENABLE |
1156                                 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1157                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1158                                 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
1159                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1160                                 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
1161                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1162                                 COH901318_CX_CTRL_TCP_ENABLE |
1163                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1164                                 COH901318_CX_CTRL_HSP_ENABLE |
1165                                 COH901318_CX_CTRL_HSS_DISABLE |
1166                                 COH901318_CX_CTRL_DDMA_LEGACY |
1167                                 COH901318_CX_CTRL_PRDD_SOURCE,
1168         },
1169         {
1170                 .number = U300_DMA_PCM_I2S0_RX,
1171                 .name = "PCM I2S0 RX",
1172                 .priority_high = 1,
1173                 .dev_addr = U300_PCM_I2S0_BASE + 0x10,
1174                 .param.config = COH901318_CX_CFG_CH_DISABLE |
1175                                 COH901318_CX_CFG_LCR_DISABLE |
1176                                 COH901318_CX_CFG_TC_IRQ_ENABLE |
1177                                 COH901318_CX_CFG_BE_IRQ_ENABLE,
1178                 .param.ctrl_lli_chained = 0 |
1179                                 COH901318_CX_CTRL_TC_ENABLE |
1180                                 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1181                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1182                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
1183                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1184                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
1185                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1186                                 COH901318_CX_CTRL_TCP_DISABLE |
1187                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1188                                 COH901318_CX_CTRL_HSP_ENABLE |
1189                                 COH901318_CX_CTRL_HSS_DISABLE |
1190                                 COH901318_CX_CTRL_DDMA_LEGACY |
1191                                 COH901318_CX_CTRL_PRDD_DEST,
1192                 .param.ctrl_lli = 0 |
1193                                 COH901318_CX_CTRL_TC_ENABLE |
1194                                 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1195                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1196                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
1197                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1198                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
1199                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1200                                 COH901318_CX_CTRL_TCP_ENABLE |
1201                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1202                                 COH901318_CX_CTRL_HSP_ENABLE |
1203                                 COH901318_CX_CTRL_HSS_DISABLE |
1204                                 COH901318_CX_CTRL_DDMA_LEGACY |
1205                                 COH901318_CX_CTRL_PRDD_DEST,
1206                 .param.ctrl_lli_last = 0 |
1207                                 COH901318_CX_CTRL_TC_ENABLE |
1208                                 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1209                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1210                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
1211                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1212                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
1213                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1214                                 COH901318_CX_CTRL_TCP_ENABLE |
1215                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
1216                                 COH901318_CX_CTRL_HSP_ENABLE |
1217                                 COH901318_CX_CTRL_HSS_DISABLE |
1218                                 COH901318_CX_CTRL_DDMA_LEGACY |
1219                                 COH901318_CX_CTRL_PRDD_DEST,
1220         },
1221         {
1222                 .number = U300_DMA_PCM_I2S1_TX,
1223                 .name = "PCM I2S1 TX",
1224                 .priority_high = 1,
1225                 .dev_addr =  U300_PCM_I2S1_BASE + 0x14,
1226                 .param.config = COH901318_CX_CFG_CH_DISABLE |
1227                                 COH901318_CX_CFG_LCR_DISABLE |
1228                                 COH901318_CX_CFG_TC_IRQ_ENABLE |
1229                                 COH901318_CX_CFG_BE_IRQ_ENABLE,
1230                 .param.ctrl_lli_chained = 0 |
1231                                 COH901318_CX_CTRL_TC_ENABLE |
1232                                 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1233                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1234                                 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
1235                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1236                                 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
1237                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1238                                 COH901318_CX_CTRL_TCP_DISABLE |
1239                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1240                                 COH901318_CX_CTRL_HSP_ENABLE |
1241                                 COH901318_CX_CTRL_HSS_DISABLE |
1242                                 COH901318_CX_CTRL_DDMA_LEGACY |
1243                                 COH901318_CX_CTRL_PRDD_SOURCE,
1244                 .param.ctrl_lli = 0 |
1245                                 COH901318_CX_CTRL_TC_ENABLE |
1246                                 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1247                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1248                                 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
1249                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1250                                 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
1251                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1252                                 COH901318_CX_CTRL_TCP_ENABLE |
1253                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1254                                 COH901318_CX_CTRL_HSP_ENABLE |
1255                                 COH901318_CX_CTRL_HSS_DISABLE |
1256                                 COH901318_CX_CTRL_DDMA_LEGACY |
1257                                 COH901318_CX_CTRL_PRDD_SOURCE,
1258                 .param.ctrl_lli_last = 0 |
1259                                 COH901318_CX_CTRL_TC_ENABLE |
1260                                 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1261                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1262                                 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
1263                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1264                                 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
1265                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1266                                 COH901318_CX_CTRL_TCP_ENABLE |
1267                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
1268                                 COH901318_CX_CTRL_HSP_ENABLE |
1269                                 COH901318_CX_CTRL_HSS_DISABLE |
1270                                 COH901318_CX_CTRL_DDMA_LEGACY |
1271                                 COH901318_CX_CTRL_PRDD_SOURCE,
1272         },
1273         {
1274                 .number = U300_DMA_PCM_I2S1_RX,
1275                 .name = "PCM I2S1 RX",
1276                 .priority_high = 1,
1277                 .dev_addr = U300_PCM_I2S1_BASE + 0x10,
1278                 .param.config = COH901318_CX_CFG_CH_DISABLE |
1279                                 COH901318_CX_CFG_LCR_DISABLE |
1280                                 COH901318_CX_CFG_TC_IRQ_ENABLE |
1281                                 COH901318_CX_CFG_BE_IRQ_ENABLE,
1282                 .param.ctrl_lli_chained = 0 |
1283                                 COH901318_CX_CTRL_TC_ENABLE |
1284                                 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1285                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1286                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
1287                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1288                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
1289                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1290                                 COH901318_CX_CTRL_TCP_DISABLE |
1291                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1292                                 COH901318_CX_CTRL_HSP_ENABLE |
1293                                 COH901318_CX_CTRL_HSS_DISABLE |
1294                                 COH901318_CX_CTRL_DDMA_LEGACY |
1295                                 COH901318_CX_CTRL_PRDD_DEST,
1296                 .param.ctrl_lli = 0 |
1297                                 COH901318_CX_CTRL_TC_ENABLE |
1298                                 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1299                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1300                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
1301                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1302                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
1303                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1304                                 COH901318_CX_CTRL_TCP_ENABLE |
1305                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1306                                 COH901318_CX_CTRL_HSP_ENABLE |
1307                                 COH901318_CX_CTRL_HSS_DISABLE |
1308                                 COH901318_CX_CTRL_DDMA_LEGACY |
1309                                 COH901318_CX_CTRL_PRDD_DEST,
1310                 .param.ctrl_lli_last = 0 |
1311                                 COH901318_CX_CTRL_TC_ENABLE |
1312                                 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1313                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1314                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
1315                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1316                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
1317                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1318                                 COH901318_CX_CTRL_TCP_ENABLE |
1319                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
1320                                 COH901318_CX_CTRL_HSP_ENABLE |
1321                                 COH901318_CX_CTRL_HSS_DISABLE |
1322                                 COH901318_CX_CTRL_DDMA_LEGACY |
1323                                 COH901318_CX_CTRL_PRDD_DEST,
1324         },
1325         {
1326                 .number = U300_DMA_XGAM_CDI,
1327                 .name = "XGAM CDI",
1328                 .priority_high = 0,
1329         },
1330         {
1331                 .number = U300_DMA_XGAM_PDI,
1332                 .name = "XGAM PDI",
1333                 .priority_high = 0,
1334         },
1335         /*
1336          * Don't set up device address, burst count or size of src
1337          * or dst bus for this peripheral - handled by PrimeCell
1338          * DMA extension.
1339          */
1340         {
1341                 .number = U300_DMA_SPI_TX,
1342                 .name = "SPI TX",
1343                 .priority_high = 0,
1344                 .param.config = COH901318_CX_CFG_CH_DISABLE |
1345                                 COH901318_CX_CFG_LCR_DISABLE |
1346                                 COH901318_CX_CFG_TC_IRQ_ENABLE |
1347                                 COH901318_CX_CFG_BE_IRQ_ENABLE,
1348                 .param.ctrl_lli_chained = 0 |
1349                                 COH901318_CX_CTRL_TC_ENABLE |
1350                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1351                                 COH901318_CX_CTRL_TCP_DISABLE |
1352                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1353                                 COH901318_CX_CTRL_HSP_ENABLE |
1354                                 COH901318_CX_CTRL_HSS_DISABLE |
1355                                 COH901318_CX_CTRL_DDMA_LEGACY,
1356                 .param.ctrl_lli = 0 |
1357                                 COH901318_CX_CTRL_TC_ENABLE |
1358                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1359                                 COH901318_CX_CTRL_TCP_DISABLE |
1360                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
1361                                 COH901318_CX_CTRL_HSP_ENABLE |
1362                                 COH901318_CX_CTRL_HSS_DISABLE |
1363                                 COH901318_CX_CTRL_DDMA_LEGACY,
1364                 .param.ctrl_lli_last = 0 |
1365                                 COH901318_CX_CTRL_TC_ENABLE |
1366                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1367                                 COH901318_CX_CTRL_TCP_DISABLE |
1368                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
1369                                 COH901318_CX_CTRL_HSP_ENABLE |
1370                                 COH901318_CX_CTRL_HSS_DISABLE |
1371                                 COH901318_CX_CTRL_DDMA_LEGACY,
1372         },
1373         {
1374                 .number = U300_DMA_SPI_RX,
1375                 .name = "SPI RX",
1376                 .priority_high = 0,
1377                 .param.config = COH901318_CX_CFG_CH_DISABLE |
1378                                 COH901318_CX_CFG_LCR_DISABLE |
1379                                 COH901318_CX_CFG_TC_IRQ_ENABLE |
1380                                 COH901318_CX_CFG_BE_IRQ_ENABLE,
1381                 .param.ctrl_lli_chained = 0 |
1382                                 COH901318_CX_CTRL_TC_ENABLE |
1383                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1384                                 COH901318_CX_CTRL_TCP_DISABLE |
1385                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1386                                 COH901318_CX_CTRL_HSP_ENABLE |
1387                                 COH901318_CX_CTRL_HSS_DISABLE |
1388                                 COH901318_CX_CTRL_DDMA_LEGACY,
1389                 .param.ctrl_lli = 0 |
1390                                 COH901318_CX_CTRL_TC_ENABLE |
1391                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1392                                 COH901318_CX_CTRL_TCP_DISABLE |
1393                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
1394                                 COH901318_CX_CTRL_HSP_ENABLE |
1395                                 COH901318_CX_CTRL_HSS_DISABLE |
1396                                 COH901318_CX_CTRL_DDMA_LEGACY,
1397                 .param.ctrl_lli_last = 0 |
1398                                 COH901318_CX_CTRL_TC_ENABLE |
1399                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1400                                 COH901318_CX_CTRL_TCP_DISABLE |
1401                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
1402                                 COH901318_CX_CTRL_HSP_ENABLE |
1403                                 COH901318_CX_CTRL_HSS_DISABLE |
1404                                 COH901318_CX_CTRL_DDMA_LEGACY,
1405
1406         },
1407         {
1408                 .number = U300_DMA_GENERAL_PURPOSE_0,
1409                 .name = "GENERAL 00",
1410                 .priority_high = 0,
1411
1412                 .param.config = flags_memcpy_config,
1413                 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1414                 .param.ctrl_lli = flags_memcpy_lli,
1415                 .param.ctrl_lli_last = flags_memcpy_lli_last,
1416         },
1417         {
1418                 .number = U300_DMA_GENERAL_PURPOSE_1,
1419                 .name = "GENERAL 01",
1420                 .priority_high = 0,
1421
1422                 .param.config = flags_memcpy_config,
1423                 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1424                 .param.ctrl_lli = flags_memcpy_lli,
1425                 .param.ctrl_lli_last = flags_memcpy_lli_last,
1426         },
1427         {
1428                 .number = U300_DMA_GENERAL_PURPOSE_2,
1429                 .name = "GENERAL 02",
1430                 .priority_high = 0,
1431
1432                 .param.config = flags_memcpy_config,
1433                 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1434                 .param.ctrl_lli = flags_memcpy_lli,
1435                 .param.ctrl_lli_last = flags_memcpy_lli_last,
1436         },
1437         {
1438                 .number = U300_DMA_GENERAL_PURPOSE_3,
1439                 .name = "GENERAL 03",
1440                 .priority_high = 0,
1441
1442                 .param.config = flags_memcpy_config,
1443                 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1444                 .param.ctrl_lli = flags_memcpy_lli,
1445                 .param.ctrl_lli_last = flags_memcpy_lli_last,
1446         },
1447         {
1448                 .number = U300_DMA_GENERAL_PURPOSE_4,
1449                 .name = "GENERAL 04",
1450                 .priority_high = 0,
1451
1452                 .param.config = flags_memcpy_config,
1453                 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1454                 .param.ctrl_lli = flags_memcpy_lli,
1455                 .param.ctrl_lli_last = flags_memcpy_lli_last,
1456         },
1457         {
1458                 .number = U300_DMA_GENERAL_PURPOSE_5,
1459                 .name = "GENERAL 05",
1460                 .priority_high = 0,
1461
1462                 .param.config = flags_memcpy_config,
1463                 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1464                 .param.ctrl_lli = flags_memcpy_lli,
1465                 .param.ctrl_lli_last = flags_memcpy_lli_last,
1466         },
1467         {
1468                 .number = U300_DMA_GENERAL_PURPOSE_6,
1469                 .name = "GENERAL 06",
1470                 .priority_high = 0,
1471
1472                 .param.config = flags_memcpy_config,
1473                 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1474                 .param.ctrl_lli = flags_memcpy_lli,
1475                 .param.ctrl_lli_last = flags_memcpy_lli_last,
1476         },
1477         {
1478                 .number = U300_DMA_GENERAL_PURPOSE_7,
1479                 .name = "GENERAL 07",
1480                 .priority_high = 0,
1481
1482                 .param.config = flags_memcpy_config,
1483                 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1484                 .param.ctrl_lli = flags_memcpy_lli,
1485                 .param.ctrl_lli_last = flags_memcpy_lli_last,
1486         },
1487         {
1488                 .number = U300_DMA_GENERAL_PURPOSE_8,
1489                 .name = "GENERAL 08",
1490                 .priority_high = 0,
1491
1492                 .param.config = flags_memcpy_config,
1493                 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1494                 .param.ctrl_lli = flags_memcpy_lli,
1495                 .param.ctrl_lli_last = flags_memcpy_lli_last,
1496         },
1497 #ifdef CONFIG_MACH_U300_BS335
1498         {
1499                 .number = U300_DMA_UART1_TX,
1500                 .name = "UART1 TX",
1501                 .priority_high = 0,
1502         },
1503         {
1504                 .number = U300_DMA_UART1_RX,
1505                 .name = "UART1 RX",
1506                 .priority_high = 0,
1507         }
1508 #else
1509         {
1510                 .number = U300_DMA_GENERAL_PURPOSE_9,
1511                 .name = "GENERAL 09",
1512                 .priority_high = 0,
1513
1514                 .param.config = flags_memcpy_config,
1515                 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1516                 .param.ctrl_lli = flags_memcpy_lli,
1517                 .param.ctrl_lli_last = flags_memcpy_lli_last,
1518         },
1519         {
1520                 .number = U300_DMA_GENERAL_PURPOSE_10,
1521                 .name = "GENERAL 10",
1522                 .priority_high = 0,
1523
1524                 .param.config = flags_memcpy_config,
1525                 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1526                 .param.ctrl_lli = flags_memcpy_lli,
1527                 .param.ctrl_lli_last = flags_memcpy_lli_last,
1528         }
1529 #endif
1530 };
1531
1532
1533 static struct coh901318_platform coh901318_platform = {
1534         .chans_slave = dma_slave_channels,
1535         .chans_memcpy = dma_memcpy_channels,
1536         .access_memory_state = coh901318_access_memory_state,
1537         .chan_conf = chan_config,
1538         .max_channels = U300_DMA_CHANNELS,
1539 };
1540
1541 static struct platform_device wdog_device = {
1542         .name = "coh901327_wdog",
1543         .id = -1,
1544         .num_resources = ARRAY_SIZE(wdog_resources),
1545         .resource = wdog_resources,
1546 };
1547
1548 static struct platform_device i2c0_device = {
1549         .name = "stu300",
1550         .id = 0,
1551         .num_resources = ARRAY_SIZE(i2c0_resources),
1552         .resource = i2c0_resources,
1553 };
1554
1555 static struct platform_device i2c1_device = {
1556         .name = "stu300",
1557         .id = 1,
1558         .num_resources = ARRAY_SIZE(i2c1_resources),
1559         .resource = i2c1_resources,
1560 };
1561
1562 static struct platform_device gpio_device = {
1563         .name = "u300-gpio",
1564         .id = -1,
1565         .num_resources = ARRAY_SIZE(gpio_resources),
1566         .resource = gpio_resources,
1567 };
1568
1569 static struct platform_device keypad_device = {
1570         .name = "keypad",
1571         .id = -1,
1572         .num_resources = ARRAY_SIZE(keypad_resources),
1573         .resource = keypad_resources,
1574 };
1575
1576 static struct platform_device rtc_device = {
1577         .name = "rtc-coh901331",
1578         .id = -1,
1579         .num_resources = ARRAY_SIZE(rtc_resources),
1580         .resource = rtc_resources,
1581 };
1582
1583 static struct mtd_partition u300_partitions[] = {
1584         {
1585                 .name = "bootrecords",
1586                 .offset = 0,
1587                 .size = SZ_128K,
1588         },
1589         {
1590                 .name = "free",
1591                 .offset = SZ_128K,
1592                 .size = 8064 * SZ_1K,
1593         },
1594         {
1595                 .name = "platform",
1596                 .offset = 8192 * SZ_1K,
1597                 .size = 253952 * SZ_1K,
1598         },
1599 };
1600
1601 static struct fsmc_nand_platform_data nand_platform_data = {
1602         .partitions = u300_partitions,
1603         .nr_partitions = ARRAY_SIZE(u300_partitions),
1604         .options = NAND_SKIP_BBTSCAN,
1605         .width = FSMC_NAND_BW8,
1606 };
1607
1608 static struct platform_device nand_device = {
1609         .name = "fsmc-nand",
1610         .id = -1,
1611         .resource = fsmc_resources,
1612         .num_resources = ARRAY_SIZE(fsmc_resources),
1613         .dev = {
1614                 .platform_data = &nand_platform_data,
1615         },
1616 };
1617
1618 static struct platform_device ave_device = {
1619         .name = "video_enc",
1620         .id = -1,
1621         .num_resources = ARRAY_SIZE(ave_resources),
1622         .resource = ave_resources,
1623 };
1624
1625 static struct platform_device dma_device = {
1626         .name           = "coh901318",
1627         .id             = -1,
1628         .resource       = dma_resource,
1629         .num_resources  = ARRAY_SIZE(dma_resource),
1630         .dev = {
1631                 .platform_data = &coh901318_platform,
1632                 .coherent_dma_mask = ~0,
1633         },
1634 };
1635
1636 /*
1637  * Notice that AMBA devices are initialized before platform devices.
1638  *
1639  */
1640 static struct platform_device *platform_devs[] __initdata = {
1641         &dma_device,
1642         &i2c0_device,
1643         &i2c1_device,
1644         &keypad_device,
1645         &rtc_device,
1646         &gpio_device,
1647         &nand_device,
1648         &wdog_device,
1649         &ave_device
1650 };
1651
1652
1653 /*
1654  * Interrupts: the U300 platforms have two pl190 ARM PrimeCells connected
1655  * together so some interrupts are connected to the first one and some
1656  * to the second one.
1657  */
1658 void __init u300_init_irq(void)
1659 {
1660         u32 mask[2] = {0, 0};
1661         struct clk *clk;
1662         int i;
1663
1664         /* initialize clocking early, we want to clock the INTCON */
1665         u300_clock_init();
1666
1667         /* Clock the interrupt controller */
1668         clk = clk_get_sys("intcon", NULL);
1669         BUG_ON(IS_ERR(clk));
1670         clk_enable(clk);
1671
1672         for (i = 0; i < NR_IRQS; i++)
1673                 set_bit(i, (unsigned long *) &mask[0]);
1674         vic_init((void __iomem *) U300_INTCON0_VBASE, 0, mask[0], mask[0]);
1675         vic_init((void __iomem *) U300_INTCON1_VBASE, 32, mask[1], mask[1]);
1676 }
1677
1678
1679 /*
1680  * U300 platforms peripheral handling
1681  */
1682 struct db_chip {
1683         u16 chipid;
1684         const char *name;
1685 };
1686
1687 /*
1688  * This is a list of the Digital Baseband chips used in the U300 platform.
1689  */
1690 static struct db_chip db_chips[] __initdata = {
1691         {
1692                 .chipid = 0xb800,
1693                 .name = "DB3000",
1694         },
1695         {
1696                 .chipid = 0xc000,
1697                 .name = "DB3100",
1698         },
1699         {
1700                 .chipid = 0xc800,
1701                 .name = "DB3150",
1702         },
1703         {
1704                 .chipid = 0xd800,
1705                 .name = "DB3200",
1706         },
1707         {
1708                 .chipid = 0xe000,
1709                 .name = "DB3250",
1710         },
1711         {
1712                 .chipid = 0xe800,
1713                 .name = "DB3210",
1714         },
1715         {
1716                 .chipid = 0xf000,
1717                 .name = "DB3350 P1x",
1718         },
1719         {
1720                 .chipid = 0xf100,
1721                 .name = "DB3350 P2x",
1722         },
1723         {
1724                 .chipid = 0x0000, /* List terminator */
1725                 .name = NULL,
1726         }
1727 };
1728
1729 static void __init u300_init_check_chip(void)
1730 {
1731
1732         u16 val;
1733         struct db_chip *chip;
1734         const char *chipname;
1735         const char unknown[] = "UNKNOWN";
1736
1737         /* Read out and print chip ID */
1738         val = readw(U300_SYSCON_VBASE + U300_SYSCON_CIDR);
1739         /* This is in funky bigendian order... */
1740         val = (val & 0xFFU) << 8 | (val >> 8);
1741         chip = db_chips;
1742         chipname = unknown;
1743
1744         for ( ; chip->chipid; chip++) {
1745                 if (chip->chipid == (val & 0xFF00U)) {
1746                         chipname = chip->name;
1747                         break;
1748                 }
1749         }
1750         printk(KERN_INFO "Initializing U300 system on %s baseband chip " \
1751                "(chip ID 0x%04x)\n", chipname, val);
1752
1753 #ifdef CONFIG_MACH_U300_BS330
1754         if ((val & 0xFF00U) != 0xd800) {
1755                 printk(KERN_ERR "Platform configured for BS330 " \
1756                        "with DB3200 but %s detected, expect problems!",
1757                        chipname);
1758         }
1759 #endif
1760 #ifdef CONFIG_MACH_U300_BS335
1761         if ((val & 0xFF00U) != 0xf000 && (val & 0xFF00U) != 0xf100) {
1762                 printk(KERN_ERR "Platform configured for BS335 " \
1763                        " with DB3350 but %s detected, expect problems!",
1764                        chipname);
1765         }
1766 #endif
1767 #ifdef CONFIG_MACH_U300_BS365
1768         if ((val & 0xFF00U) != 0xe800) {
1769                 printk(KERN_ERR "Platform configured for BS365 " \
1770                        "with DB3210 but %s detected, expect problems!",
1771                        chipname);
1772         }
1773 #endif
1774
1775
1776 }
1777
1778 /*
1779  * Some devices and their resources require reserved physical memory from
1780  * the end of the available RAM. This function traverses the list of devices
1781  * and assigns actual addresses to these.
1782  */
1783 static void __init u300_assign_physmem(void)
1784 {
1785         unsigned long curr_start = __pa(high_memory);
1786         int i, j;
1787
1788         for (i = 0; i < ARRAY_SIZE(platform_devs); i++) {
1789                 for (j = 0; j < platform_devs[i]->num_resources; j++) {
1790                         struct resource *const res =
1791                           &platform_devs[i]->resource[j];
1792
1793                         if (IORESOURCE_MEM == res->flags &&
1794                                      0 == res->start) {
1795                                 res->start  = curr_start;
1796                                 res->end   += curr_start;
1797                                 curr_start += resource_size(res);
1798
1799                                 printk(KERN_INFO "core.c: Mapping RAM " \
1800                                        "%#x-%#x to device %s:%s\n",
1801                                         res->start, res->end,
1802                                        platform_devs[i]->name, res->name);
1803                         }
1804                 }
1805         }
1806 }
1807
1808 void __init u300_init_devices(void)
1809 {
1810         int i;
1811         u16 val;
1812
1813         /* Check what platform we run and print some status information */
1814         u300_init_check_chip();
1815
1816         /* Set system to run at PLL208, max performance, a known state. */
1817         val = readw(U300_SYSCON_VBASE + U300_SYSCON_CCR);
1818         val &= ~U300_SYSCON_CCR_CLKING_PERFORMANCE_MASK;
1819         writew(val, U300_SYSCON_VBASE + U300_SYSCON_CCR);
1820         /* Wait for the PLL208 to lock if not locked in yet */
1821         while (!(readw(U300_SYSCON_VBASE + U300_SYSCON_CSR) &
1822                  U300_SYSCON_CSR_PLL208_LOCK_IND));
1823         /* Initialize SPI device with some board specifics */
1824         u300_spi_init(&pl022_device);
1825
1826         /* Register the AMBA devices in the AMBA bus abstraction layer */
1827         for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
1828                 struct amba_device *d = amba_devs[i];
1829                 amba_device_register(d, &iomem_resource);
1830         }
1831
1832         u300_assign_physmem();
1833
1834         /* Register subdevices on the I2C buses */
1835         u300_i2c_register_board_devices();
1836
1837         /* Register the platform devices */
1838         platform_add_devices(platform_devs, ARRAY_SIZE(platform_devs));
1839
1840         /* Register subdevices on the SPI bus */
1841         u300_spi_register_board_devices();
1842
1843 #ifndef CONFIG_MACH_U300_SEMI_IS_SHARED
1844         /*
1845          * Enable SEMI self refresh. Self-refresh of the SDRAM is entered when
1846          * both subsystems are requesting this mode.
1847          * If we not share the Acc SDRAM, this is never the case. Therefore
1848          * enable it here from the App side.
1849          */
1850         val = readw(U300_SYSCON_VBASE + U300_SYSCON_SMCR) |
1851                 U300_SYSCON_SMCR_SEMI_SREFREQ_ENABLE;
1852         writew(val, U300_SYSCON_VBASE + U300_SYSCON_SMCR);
1853 #endif /* CONFIG_MACH_U300_SEMI_IS_SHARED */
1854 }
1855
1856 static int core_module_init(void)
1857 {
1858         /*
1859          * This needs to be initialized later: it needs the input framework
1860          * to be initialized first.
1861          */
1862         return mmc_init(&mmcsd_device);
1863 }
1864 module_init(core_module_init);