arch/arm/mach-tegra/usb_phy.c

   1 /*
   2  * arch/arm/mach-tegra/usb_phy.c
   3  *
   4  * Copyright (C) 2010 Google, Inc.
   5  *
   6  * Author:
   7  *      Erik Gilling <konkers@google.com>
   8  *      Benoit Goby <benoit@android.com>
   9  *
  10  * This software is licensed under the terms of the GNU General Public
  11  * License version 2, as published by the Free Software Foundation, and
  12  * may be copied, distributed, and modified under those terms.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  */
  20
  21 #include <linux/resource.h>
  22 #include <linux/delay.h>
  23 #include <linux/slab.h>
  24 #include <linux/err.h>
  25 #include <linux/platform_device.h>
  26 #include <linux/io.h>
  27 #include <linux/gpio.h>
  28 #include <asm/mach-types.h>
  29 #include <mach/usb_phy.h>
  30 #include <mach/iomap.h>
  31
  32 #define USB_USBSTS              0x144
  33 #define   USB_USBSTS_PCI        (1 << 2)
  34
  35 #define ULPI_VIEWPORT           0x170
  36 #define   ULPI_WAKEUP           (1 << 31)
  37 #define   ULPI_RUN              (1 << 30)
  38 #define   ULPI_RD_RW_WRITE      (1 << 29)
  39 #define   ULPI_RD_RW_READ       (0 << 29)
  40 #define   ULPI_PORT(x)          (((x) & 0x7) << 24)
  41 #define   ULPI_ADDR(x)          (((x) & 0xff) << 16)
  42 #define   ULPI_DATA_RD(x)       (((x) & 0xff) << 8)
  43 #define   ULPI_DATA_WR(x)       (((x) & 0xff) << 0)
  44
  45 #define USB_PORTSC1             0x184
  46 #define   USB_PORTSC1_PTS(x)    (((x) & 0x3) << 30)
  47 #define   USB_PORTSC1_PSPD(x)   (((x) & 0x3) << 26)
  48 #define   USB_PORTSC1_PHCD      (1 << 23)
  49 #define   USB_PORTSC1_WKOC      (1 << 22)
  50 #define   USB_PORTSC1_WKDS      (1 << 21)
  51 #define   USB_PORTSC1_WKCN      (1 << 20)
  52 #define   USB_PORTSC1_PTC(x)    (((x) & 0xf) << 16)
  53 #define   USB_PORTSC1_PP        (1 << 12)
  54 #define   USB_PORTSC1_SUSP      (1 << 7)
  55 #define   USB_PORTSC1_PE        (1 << 2)
  56 #define   USB_PORTSC1_CCS       (1 << 0)
  57
  58 #define USB_SUSP_CTRL           0x400
  59 #define   USB_WAKE_ON_CNNT_EN_DEV       (1 << 3)
  60 #define   USB_WAKE_ON_DISCON_EN_DEV     (1 << 4)
  61 #define   USB_SUSP_CLR          (1 << 5)
  62 #define   USB_PHY_CLK_VALID     (1 << 7)
  63 #define   UTMIP_RESET                   (1 << 11)
  64 #define   UHSIC_RESET                   (1 << 11)
  65 #define   UTMIP_PHY_ENABLE              (1 << 12)
  66 #define   ULPI_PHY_ENABLE       (1 << 13)
  67 #define   USB_SUSP_SET          (1 << 14)
  68 #define   USB_WAKEUP_DEBOUNCE_COUNT(x)  (((x) & 0x7) << 16)
  69
  70 #define USB1_LEGACY_CTRL        0x410
  71 #define   USB1_NO_LEGACY_MODE                   (1 << 0)
  72 #define   USB1_VBUS_SENSE_CTL_MASK              (3 << 1)
  73 #define   USB1_VBUS_SENSE_CTL_VBUS_WAKEUP       (0 << 1)
  74 #define   USB1_VBUS_SENSE_CTL_AB_SESS_VLD_OR_VBUS_WAKEUP \
  75                                                 (1 << 1)
  76 #define   USB1_VBUS_SENSE_CTL_AB_SESS_VLD       (2 << 1)
  77 #define   USB1_VBUS_SENSE_CTL_A_SESS_VLD        (3 << 1)
  78
  79 #define ULPI_TIMING_CTRL_0      0x424
  80 #define   ULPI_OUTPUT_PINMUX_BYP        (1 << 10)
  81 #define   ULPI_CLKOUT_PINMUX_BYP        (1 << 11)
  82
  83 #define ULPI_TIMING_CTRL_1      0x428
  84 #define   ULPI_DATA_TRIMMER_LOAD        (1 << 0)
  85 #define   ULPI_DATA_TRIMMER_SEL(x)      (((x) & 0x7) << 1)
  86 #define   ULPI_STPDIRNXT_TRIMMER_LOAD   (1 << 16)
  87 #define   ULPI_STPDIRNXT_TRIMMER_SEL(x) (((x) & 0x7) << 17)
  88 #define   ULPI_DIR_TRIMMER_LOAD         (1 << 24)
  89 #define   ULPI_DIR_TRIMMER_SEL(x)       (((x) & 0x7) << 25)
  90
  91 #define UTMIP_PLL_CFG1          0x804
  92 #define   UTMIP_XTAL_FREQ_COUNT(x)              (((x) & 0xfff) << 0)
  93 #define   UTMIP_PLLU_ENABLE_DLY_COUNT(x)        (((x) & 0x1f) << 27)
  94
  95 #define UTMIP_XCVR_CFG0         0x808
  96 #define   UTMIP_XCVR_SETUP(x)                   (((x) & 0xf) << 0)
  97 #define   UTMIP_XCVR_LSRSLEW(x)                 (((x) & 0x3) << 8)
  98 #define   UTMIP_XCVR_LSFSLEW(x)                 (((x) & 0x3) << 10)
  99 #define   UTMIP_FORCE_PD_POWERDOWN              (1 << 14)
 100 #define   UTMIP_FORCE_PD2_POWERDOWN             (1 << 16)
 101 #define   UTMIP_FORCE_PDZI_POWERDOWN            (1 << 18)
 102 #define   UTMIP_XCVR_HSSLEW_MSB(x)              (((x) & 0x7f) << 25)
 103
 104 #define UTMIP_BIAS_CFG0         0x80c
 105 #define   UTMIP_OTGPD                   (1 << 11)
 106 #define   UTMIP_BIASPD                  (1 << 10)
 107
 108 #define UTMIP_HSRX_CFG0         0x810
 109 #define   UTMIP_ELASTIC_LIMIT(x)        (((x) & 0x1f) << 10)
 110 #define   UTMIP_IDLE_WAIT(x)            (((x) & 0x1f) << 15)
 111
 112 #define UTMIP_HSRX_CFG1         0x814
 113 #define   UTMIP_HS_SYNC_START_DLY(x)    (((x) & 0x1f) << 1)
 114
 115 #define UTMIP_TX_CFG0           0x820
 116 #define   UTMIP_FS_PREABMLE_J           (1 << 19)
 117 #define   UTMIP_HS_DISCON_DISABLE       (1 << 8)
 118
 119 #define UTMIP_MISC_CFG0         0x824
 120 #define   UTMIP_SUSPEND_EXIT_ON_EDGE    (1 << 22)
 121
 122 #define UTMIP_MISC_CFG1         0x828
 123 #define   UTMIP_PLL_ACTIVE_DLY_COUNT(x) (((x) & 0x1f) << 18)
 124 #define   UTMIP_PLLU_STABLE_COUNT(x)    (((x) & 0xfff) << 6)
 125
 126 #define UTMIP_DEBOUNCE_CFG0     0x82c
 127 #define   UTMIP_BIAS_DEBOUNCE_A(x)      (((x) & 0xffff) << 0)
 128
 129 #define UTMIP_BAT_CHRG_CFG0     0x830
 130 #define   UTMIP_PD_CHRG                 (1 << 0)
 131
 132 #define UTMIP_SPARE_CFG0        0x834
 133 #define   FUSE_SETUP_SEL                (1 << 3);
 134
 135 #define UTMIP_XCVR_CFG1         0x838
 136 #define   UTMIP_FORCE_PDDISC_POWERDOWN  (1 << 0)
 137 #define   UTMIP_FORCE_PDCHRP_POWERDOWN  (1 << 2)
 138 #define   UTMIP_FORCE_PDDR_POWERDOWN    (1 << 4)
 139 #define   UTMIP_XCVR_TERM_RANGE_ADJ(x)  (((x) & 0xf) << 18)
 140
 141 #define UTMIP_BIAS_CFG1         0x83c
 142 #define   UTMIP_BIAS_PDTRK_COUNT(x)     (((x) & 0x1f) << 3)
 143
 144 static DEFINE_SPINLOCK(utmip_pad_lock);
 145 static int utmip_pad_count;
 146
 147 static const int udc_freq_table[] = {
 148         12000000,
 149         13000000,
 150         19200000,
 151         26000000,
 152 };
 153
 154 static const u8 udc_delay_table[][4] = {
 155         /* ENABLE_DLY, STABLE_CNT, ACTIVE_DLY, XTAL_FREQ_CNT */
 156         {0x02,         0x2F,       0x04,       0x76}, /* 12 MHz */
 157         {0x02,         0x33,       0x05,       0x7F}, /* 13 MHz */
 158         {0x03,         0x4B,       0x06,       0xBB}, /* 19.2 MHz */
 159         {0x04,         0x66,       0x09,       0xFE}, /* 26 Mhz */
 160 };
 161
 162 static const u16 udc_debounce_table[] = {
 163         0x7530, /* 12 MHz */
 164         0x7EF4, /* 13 MHz */
 165         0xBB80, /* 19.2 MHz */
 166         0xFDE8, /* 26 MHz */
 167 };
 168
 169 static struct tegra_utmip_config utmip_default[] = {
 170         [0] = {
 171                 .hssync_start_delay = 9,
 172                 .idle_wait_delay = 17,
 173                 .elastic_limit = 16,
 174                 .term_range_adj = 6,
 175                 .xcvr_setup = 9,
 176                 .xcvr_lsfslew = 1,
 177                 .xcvr_lsrslew = 1,
 178         },
 179         [2] = {
 180                 .hssync_start_delay = 9,
 181                 .idle_wait_delay = 17,
 182                 .elastic_limit = 16,
 183                 .term_range_adj = 6,
 184                 .xcvr_setup = 9,
 185                 .xcvr_lsfslew = 2,
 186                 .xcvr_lsrslew = 2,
 187         },
 188 };
 189
 190 static int utmip_pad_open(struct tegra_usb_phy *phy)
 191 {
 192         phy->pad_clk = clk_get_sys("utmip-pad", NULL);
 193         if (IS_ERR(phy->pad_clk)) {
 194                 pr_err("%s: can't get utmip pad clock\n", __func__);
 195                 return -1;
 196         }
 197
 198         if (phy->instance == 0) {
 199                 phy->pad_regs = phy->regs;
 200         } else {
 201                 phy->pad_regs = ioremap(TEGRA_USB_BASE, TEGRA_USB_SIZE);
 202                 if (!phy->pad_regs) {
 203                         pr_err("%s: can't remap usb registers\n", __func__);
 204                         clk_put(phy->pad_clk);
 205                         return -ENOMEM;
 206                 }
 207         }
 208         return 0;
 209 }
 210
 211 static void utmip_pad_close(struct tegra_usb_phy *phy)
 212 {
 213         if (phy->instance != 0)
 214                 iounmap(phy->pad_regs);
 215         clk_put(phy->pad_clk);
 216 }
 217
 218 static void utmip_pad_power_on(struct tegra_usb_phy *phy)
 219 {
 220         unsigned long val, flags;
 221         void __iomem *base = phy->pad_regs;
 222
 223         clk_enable(phy->pad_clk);
 224
 225         spin_lock_irqsave(&utmip_pad_lock, flags);
 226
 227         if (utmip_pad_count++ == 0) {
 228                 val = readl(base + UTMIP_BIAS_CFG0);
 229                 val &= ~(UTMIP_OTGPD | UTMIP_BIASPD);
 230                 writel(val, base + UTMIP_BIAS_CFG0);
 231         }
 232
 233         spin_unlock_irqrestore(&utmip_pad_lock, flags);
 234
 235         clk_disable(phy->pad_clk);
 236 }
 237
 238 static int utmip_pad_power_off(struct tegra_usb_phy *phy)
 239 {
 240         unsigned long val, flags;
 241         void __iomem *base = phy->pad_regs;
 242
 243         if (!utmip_pad_count) {
 244                 pr_err("%s: utmip pad already powered off\n", __func__);
 245                 return -1;
 246         }
 247
 248         clk_enable(phy->pad_clk);
 249
 250         spin_lock_irqsave(&utmip_pad_lock, flags);
 251
 252         if (--utmip_pad_count == 0) {
 253                 val = readl(base + UTMIP_BIAS_CFG0);
 254                 val |= UTMIP_OTGPD | UTMIP_BIASPD;
 255                 writel(val, base + UTMIP_BIAS_CFG0);
 256         }
 257
 258         spin_unlock_irqrestore(&utmip_pad_lock, flags);
 259
 260         clk_disable(phy->pad_clk);
 261
 262         return 0;
 263 }
 264
 265 static int utmi_wait_register(void __iomem *reg, u32 mask, u32 result)
 266 {
 267         unsigned long timeout = 2000;
 268         do {
 269                 if ((readl(reg) & mask) == result)
 270                         return 0;
 271                 udelay(1);
 272                 timeout--;
 273         } while (timeout);
 274         return -1;
 275 }
 276
 277 static void utmi_phy_clk_disable(struct tegra_usb_phy *phy)
 278 {
 279         unsigned long val;
 280         void __iomem *base = phy->regs;
 281
 282         if (phy->instance == 0) {
 283                 val = readl(base + USB_SUSP_CTRL);
 284                 val |= USB_SUSP_SET;
 285                 writel(val, base + USB_SUSP_CTRL);
 286
 287                 udelay(10);
 288
 289                 val = readl(base + USB_SUSP_CTRL);
 290                 val &= ~USB_SUSP_SET;
 291                 writel(val, base + USB_SUSP_CTRL);
 292         }
 293
 294         if (phy->instance == 2) {
 295                 val = readl(base + USB_PORTSC1);
 296                 val |= USB_PORTSC1_PHCD;
 297                 writel(val, base + USB_PORTSC1);
 298         }
 299
 300         if (utmi_wait_register(base + USB_SUSP_CTRL, USB_PHY_CLK_VALID, 0) < 0)
 301                 pr_err("%s: timeout waiting for phy to stabilize\n", __func__);
 302 }
 303
 304 static void utmi_phy_clk_enable(struct tegra_usb_phy *phy)
 305 {
 306         unsigned long val;
 307         void __iomem *base = phy->regs;
 308
 309         if (phy->instance == 0) {
 310                 val = readl(base + USB_SUSP_CTRL);
 311                 val |= USB_SUSP_CLR;
 312                 writel(val, base + USB_SUSP_CTRL);
 313
 314                 udelay(10);
 315
 316                 val = readl(base + USB_SUSP_CTRL);
 317                 val &= ~USB_SUSP_CLR;
 318                 writel(val, base + USB_SUSP_CTRL);
 319         }
 320
 321         if (phy->instance == 2) {
 322                 val = readl(base + USB_PORTSC1);
 323                 val &= ~USB_PORTSC1_PHCD;
 324                 writel(val, base + USB_PORTSC1);
 325         }
 326
 327         if (utmi_wait_register(base + USB_SUSP_CTRL, USB_PHY_CLK_VALID,
 328                                                      USB_PHY_CLK_VALID))
 329                 pr_err("%s: timeout waiting for phy to stabilize\n", __func__);
 330 }
 331
 332 static void utmi_phy_power_on(struct tegra_usb_phy *phy)
 333 {
 334         unsigned long val;
 335         void __iomem *base = phy->regs;
 336         struct tegra_utmip_config *config = phy->config;
 337
 338         val = readl(base + USB_SUSP_CTRL);
 339         val |= UTMIP_RESET;
 340         writel(val, base + USB_SUSP_CTRL);
 341
 342         if (phy->instance == 0) {
 343                 val = readl(base + USB1_LEGACY_CTRL);
 344                 val |= USB1_NO_LEGACY_MODE;
 345                 writel(val, base + USB1_LEGACY_CTRL);
 346         }
 347
 348         val = readl(base + UTMIP_TX_CFG0);
 349         val &= ~UTMIP_FS_PREABMLE_J;
 350         writel(val, base + UTMIP_TX_CFG0);
 351
 352         val = readl(base + UTMIP_HSRX_CFG0);
 353         val &= ~(UTMIP_IDLE_WAIT(~0) | UTMIP_ELASTIC_LIMIT(~0));
 354         val |= UTMIP_IDLE_WAIT(config->idle_wait_delay);
 355         val |= UTMIP_ELASTIC_LIMIT(config->elastic_limit);
 356         writel(val, base + UTMIP_HSRX_CFG0);
 357
 358         val = readl(base + UTMIP_HSRX_CFG1);
 359         val &= ~UTMIP_HS_SYNC_START_DLY(~0);
 360         val |= UTMIP_HS_SYNC_START_DLY(config->hssync_start_delay);
 361         writel(val, base + UTMIP_HSRX_CFG1);
 362
 363         val = readl(base + UTMIP_DEBOUNCE_CFG0);
 364         val &= ~UTMIP_BIAS_DEBOUNCE_A(~0);
 365         val |= UTMIP_BIAS_DEBOUNCE_A(udc_debounce_table[phy->freq_sel]);
 366         writel(val, base + UTMIP_DEBOUNCE_CFG0);
 367
 368         val = readl(base + UTMIP_MISC_CFG0);
 369         val &= ~UTMIP_SUSPEND_EXIT_ON_EDGE;
 370         writel(val, base + UTMIP_MISC_CFG0);
 371
 372         val = readl(base + UTMIP_MISC_CFG1);
 373         val &= ~(UTMIP_PLL_ACTIVE_DLY_COUNT(~0) | UTMIP_PLLU_STABLE_COUNT(~0));
 374         val |= UTMIP_PLL_ACTIVE_DLY_COUNT(udc_delay_table[phy->freq_sel][2]) |
 375                 UTMIP_PLLU_STABLE_COUNT(udc_delay_table[phy->freq_sel][1]);
 376         writel(val, base + UTMIP_MISC_CFG1);
 377
 378         val = readl(base + UTMIP_PLL_CFG1);
 379         val &= ~(UTMIP_XTAL_FREQ_COUNT(~0) | UTMIP_PLLU_ENABLE_DLY_COUNT(~0));
 380         val |= UTMIP_XTAL_FREQ_COUNT(udc_delay_table[phy->freq_sel][3]) |
 381                 UTMIP_PLLU_ENABLE_DLY_COUNT(udc_delay_table[phy->freq_sel][0]);
 382         writel(val, base + UTMIP_PLL_CFG1);
 383
 384         if (phy->mode == TEGRA_USB_PHY_MODE_DEVICE) {
 385                 val = readl(base + USB_SUSP_CTRL);
 386                 val &= ~(USB_WAKE_ON_CNNT_EN_DEV | USB_WAKE_ON_DISCON_EN_DEV);
 387                 writel(val, base + USB_SUSP_CTRL);
 388         }
 389
 390         utmip_pad_power_on(phy);
 391
 392         val = readl(base + UTMIP_XCVR_CFG0);
 393         val &= ~(UTMIP_FORCE_PD_POWERDOWN | UTMIP_FORCE_PD2_POWERDOWN |
 394                  UTMIP_FORCE_PDZI_POWERDOWN | UTMIP_XCVR_SETUP(~0) |
 395                  UTMIP_XCVR_LSFSLEW(~0) | UTMIP_XCVR_LSRSLEW(~0) |
 396                  UTMIP_XCVR_HSSLEW_MSB(~0));
 397         val |= UTMIP_XCVR_SETUP(config->xcvr_setup);
 398         val |= UTMIP_XCVR_LSFSLEW(config->xcvr_lsfslew);
 399         val |= UTMIP_XCVR_LSRSLEW(config->xcvr_lsrslew);
 400         writel(val, base + UTMIP_XCVR_CFG0);
 401
 402         val = readl(base + UTMIP_XCVR_CFG1);
 403         val &= ~(UTMIP_FORCE_PDDISC_POWERDOWN | UTMIP_FORCE_PDCHRP_POWERDOWN |
 404                  UTMIP_FORCE_PDDR_POWERDOWN | UTMIP_XCVR_TERM_RANGE_ADJ(~0));
 405         val |= UTMIP_XCVR_TERM_RANGE_ADJ(config->term_range_adj);
 406         writel(val, base + UTMIP_XCVR_CFG1);
 407
 408         val = readl(base + UTMIP_BAT_CHRG_CFG0);
 409         val &= ~UTMIP_PD_CHRG;
 410         writel(val, base + UTMIP_BAT_CHRG_CFG0);
 411
 412         val = readl(base + UTMIP_BIAS_CFG1);
 413         val &= ~UTMIP_BIAS_PDTRK_COUNT(~0);
 414         val |= UTMIP_BIAS_PDTRK_COUNT(0x5);
 415         writel(val, base + UTMIP_BIAS_CFG1);
 416
 417         if (phy->instance == 2) {
 418                 val = readl(base + USB_SUSP_CTRL);
 419                 val |= UTMIP_PHY_ENABLE;
 420                 writel(val, base + USB_SUSP_CTRL);
 421         }
 422
 423         val = readl(base + USB_SUSP_CTRL);
 424         val &= ~UTMIP_RESET;
 425         writel(val, base + USB_SUSP_CTRL);
 426
 427         if (phy->instance == 0) {
 428                 val = readl(base + USB1_LEGACY_CTRL);
 429                 val &= ~USB1_VBUS_SENSE_CTL_MASK;
 430                 val |= USB1_VBUS_SENSE_CTL_A_SESS_VLD;
 431                 writel(val, base + USB1_LEGACY_CTRL);
 432
 433                 val = readl(base + USB_SUSP_CTRL);
 434                 val &= ~USB_SUSP_SET;
 435                 writel(val, base + USB_SUSP_CTRL);
 436         }
 437
 438         utmi_phy_clk_enable(phy);
 439
 440         if (phy->instance == 2) {
 441                 val = readl(base + USB_PORTSC1);
 442                 val &= ~USB_PORTSC1_PTS(~0);
 443                 writel(val, base + USB_PORTSC1);
 444         }
 445 }
 446
 447 static void utmi_phy_power_off(struct tegra_usb_phy *phy)
 448 {
 449         unsigned long val;
 450         void __iomem *base = phy->regs;
 451
 452         utmi_phy_clk_disable(phy);
 453
 454         if (phy->mode == TEGRA_USB_PHY_MODE_DEVICE) {
 455                 val = readl(base + USB_SUSP_CTRL);
 456                 val &= ~USB_WAKEUP_DEBOUNCE_COUNT(~0);
 457                 val |= USB_WAKE_ON_CNNT_EN_DEV | USB_WAKEUP_DEBOUNCE_COUNT(5);
 458                 writel(val, base + USB_SUSP_CTRL);
 459         }
 460
 461         val = readl(base + USB_SUSP_CTRL);
 462         val |= UTMIP_RESET;
 463         writel(val, base + USB_SUSP_CTRL);
 464
 465         val = readl(base + UTMIP_BAT_CHRG_CFG0);
 466         val |= UTMIP_PD_CHRG;
 467         writel(val, base + UTMIP_BAT_CHRG_CFG0);
 468
 469         val = readl(base + UTMIP_XCVR_CFG0);
 470         val |= UTMIP_FORCE_PD_POWERDOWN | UTMIP_FORCE_PD2_POWERDOWN |
 471                UTMIP_FORCE_PDZI_POWERDOWN;
 472         writel(val, base + UTMIP_XCVR_CFG0);
 473
 474         val = readl(base + UTMIP_XCVR_CFG1);
 475         val |= UTMIP_FORCE_PDDISC_POWERDOWN | UTMIP_FORCE_PDCHRP_POWERDOWN |
 476                UTMIP_FORCE_PDDR_POWERDOWN;
 477         writel(val, base + UTMIP_XCVR_CFG1);
 478
 479         utmip_pad_power_off(phy);
 480 }
 481
 482 static void utmi_phy_preresume(struct tegra_usb_phy *phy)
 483 {
 484         unsigned long val;
 485         void __iomem *base = phy->regs;
 486
 487         val = readl(base + UTMIP_TX_CFG0);
 488         val |= UTMIP_HS_DISCON_DISABLE;
 489         writel(val, base + UTMIP_TX_CFG0);
 490 }
 491
 492 static void utmi_phy_postresume(struct tegra_usb_phy *phy)
 493 {
 494         unsigned long val;
 495         void __iomem *base = phy->regs;
 496
 497         val = readl(base + UTMIP_TX_CFG0);
 498         val &= ~UTMIP_HS_DISCON_DISABLE;
 499         writel(val, base + UTMIP_TX_CFG0);
 500 }
 501
 502 static void ulpi_viewport_write(struct tegra_usb_phy *phy, u8 addr, u8 data)
 503 {
 504         unsigned long val;
 505         void __iomem *base = phy->regs;
 506
 507         val = ULPI_RUN | ULPI_RD_RW_WRITE | ULPI_PORT(0);
 508         val |= ULPI_ADDR(addr) | ULPI_DATA_WR(data);
 509         writel(val, base + ULPI_VIEWPORT);
 510
 511         if (utmi_wait_register(base + ULPI_VIEWPORT, ULPI_RUN, 0))
 512                 pr_err("%s: timeout accessing ulpi phy\n", __func__);
 513 }
 514
 515 static void ulpi_phy_power_on(struct tegra_usb_phy *phy)
 516 {
 517         unsigned long val;
 518         void __iomem *base = phy->regs;
 519         struct tegra_ulpi_config *config = phy->config;
 520
 521         gpio_direction_output(config->reset_gpio, 0);
 522         msleep(5);
 523         gpio_direction_output(config->reset_gpio, 1);
 524
 525         clk_enable(phy->clk);
 526         msleep(1);
 527
 528         val = readl(base + USB_SUSP_CTRL);
 529         val |= UHSIC_RESET;
 530         writel(val, base + USB_SUSP_CTRL);
 531
 532         val = readl(base + ULPI_TIMING_CTRL_0);
 533         val |= ULPI_OUTPUT_PINMUX_BYP | ULPI_CLKOUT_PINMUX_BYP;
 534         writel(val, base + ULPI_TIMING_CTRL_0);
 535
 536         val = readl(base + USB_SUSP_CTRL);
 537         val |= ULPI_PHY_ENABLE;
 538         writel(val, base + USB_SUSP_CTRL);
 539
 540         val = 0;
 541         writel(val, base + ULPI_TIMING_CTRL_1);
 542
 543         val |= ULPI_DATA_TRIMMER_SEL(4);
 544         val |= ULPI_STPDIRNXT_TRIMMER_SEL(4);
 545         val |= ULPI_DIR_TRIMMER_SEL(4);
 546         writel(val, base + ULPI_TIMING_CTRL_1);
 547         udelay(10);
 548
 549         val |= ULPI_DATA_TRIMMER_LOAD;
 550         val |= ULPI_STPDIRNXT_TRIMMER_LOAD;
 551         val |= ULPI_DIR_TRIMMER_LOAD;
 552         writel(val, base + ULPI_TIMING_CTRL_1);
 553
 554         val = ULPI_WAKEUP | ULPI_RD_RW_WRITE | ULPI_PORT(0);
 555         writel(val, base + ULPI_VIEWPORT);
 556
 557         if (utmi_wait_register(base + ULPI_VIEWPORT, ULPI_WAKEUP, 0)) {
 558                 pr_err("%s: timeout waiting for ulpi phy wakeup\n", __func__);
 559                 return;
 560         }
 561
 562         /* Fix VbusInvalid due to floating VBUS */
 563         ulpi_viewport_write(phy, 0x08, 0x40);
 564         ulpi_viewport_write(phy, 0x0B, 0x80);
 565
 566         val = readl(base + USB_PORTSC1);
 567         val |= USB_PORTSC1_WKOC | USB_PORTSC1_WKDS | USB_PORTSC1_WKCN;
 568         writel(val, base + USB_PORTSC1);
 569
 570         val = readl(base + USB_SUSP_CTRL);
 571         val |= USB_SUSP_CLR;
 572         writel(val, base + USB_SUSP_CTRL);
 573         udelay(100);
 574
 575         val = readl(base + USB_SUSP_CTRL);
 576         val &= ~USB_SUSP_CLR;
 577         writel(val, base + USB_SUSP_CTRL);
 578 }
 579
 580 static void ulpi_phy_power_off(struct tegra_usb_phy *phy)
 581 {
 582         unsigned long val;
 583         void __iomem *base = phy->regs;
 584         struct tegra_ulpi_config *config = phy->config;
 585
 586         /* Clear WKCN/WKDS/WKOC wake-on events that can cause the USB
 587          * Controller to immediately bring the ULPI PHY out of low power
 588          */
 589         val = readl(base + USB_PORTSC1);
 590         val &= ~(USB_PORTSC1_WKOC | USB_PORTSC1_WKDS | USB_PORTSC1_WKCN);
 591         writel(val, base + USB_PORTSC1);
 592
 593         gpio_direction_output(config->reset_gpio, 0);
 594         clk_disable(phy->clk);
 595 }
 596
 597 struct tegra_usb_phy *tegra_usb_phy_open(int instance, void __iomem *regs,
 598                         void *config, enum tegra_usb_phy_mode phy_mode)
 599 {
 600         struct tegra_usb_phy *phy;
 601         struct tegra_ulpi_config *ulpi_config;
 602         unsigned long parent_rate;
 603         int freq_sel;
 604         int err;
 605
 606         phy = kmalloc(sizeof(struct tegra_usb_phy), GFP_KERNEL);
 607         if (!phy)
 608                 return ERR_PTR(-ENOMEM);
 609
 610         phy->instance = instance;
 611         phy->regs = regs;
 612         phy->config = config;
 613         phy->context.valid = false;
 614         phy->mode = phy_mode;
 615
 616         if (!phy->config) {
 617                 if (instance == 1) {
 618                         pr_err("%s: ulpi phy configuration missing", __func__);
 619                         err = -EINVAL;
 620                         goto err0;
 621                 } else {
 622                         phy->config = &utmip_default[instance];
 623                 }
 624         }
 625
 626         phy->pll_u = clk_get_sys(NULL, "pll_u");
 627         if (IS_ERR(phy->pll_u)) {
 628                 pr_err("Can't get pll_u clock\n");
 629                 err = PTR_ERR(phy->pll_u);
 630                 goto err0;
 631         }
 632         clk_enable(phy->pll_u);
 633
 634         parent_rate = clk_get_rate(clk_get_parent(phy->pll_u));
 635         for (freq_sel = 0; freq_sel < ARRAY_SIZE(udc_freq_table); freq_sel++) {
 636                 if (udc_freq_table[freq_sel] == parent_rate)
 637                         break;
 638         }
 639         if (freq_sel == ARRAY_SIZE(udc_freq_table)) {
 640                 pr_err("invalid pll_u parent rate %ld\n", parent_rate);
 641                 err = -EINVAL;
 642                 goto err1;
 643         }
 644         phy->freq_sel = freq_sel;
 645
 646         if (phy->instance == 1) {
 647                 ulpi_config = config;
 648                 phy->clk = clk_get_sys(NULL, ulpi_config->clk);
 649                 if (IS_ERR(phy->clk)) {
 650                         pr_err("%s: can't get ulpi clock\n", __func__);
 651                         err = -ENXIO;
 652                         goto err1;
 653                 }
 654                 tegra_gpio_enable(ulpi_config->reset_gpio);
 655                 gpio_request(ulpi_config->reset_gpio, "ulpi_phy_reset_b");
 656                 gpio_direction_output(ulpi_config->reset_gpio, 0);
 657         } else {
 658                 err = utmip_pad_open(phy);
 659                 if (err < 0)
 660                         goto err1;
 661         }
 662
 663         return phy;
 664
 665 err1:
 666         clk_disable(phy->pll_u);
 667         clk_put(phy->pll_u);
 668 err0:
 669         kfree(phy);
 670         return ERR_PTR(err);
 671 }
 672
 673 int tegra_usb_phy_power_on(struct tegra_usb_phy *phy)
 674 {
 675         if (phy->instance == 1)
 676                 ulpi_phy_power_on(phy);
 677         else
 678                 utmi_phy_power_on(phy);
 679
 680         return 0;
 681 }
 682
 683 int tegra_usb_phy_power_off(struct tegra_usb_phy *phy)
 684 {
 685         if (phy->instance == 1)
 686                 ulpi_phy_power_off(phy);
 687         else
 688                 utmi_phy_power_off(phy);
 689
 690         return 0;
 691 }
 692
 693 int tegra_usb_phy_preresume(struct tegra_usb_phy *phy)
 694 {
 695         if (phy->instance == 2)
 696                 utmi_phy_preresume(phy);
 697         return 0;
 698 }
 699
 700 int tegra_usb_phy_postresume(struct tegra_usb_phy *phy)
 701 {
 702         if (phy->instance == 2)
 703                 utmi_phy_postresume(phy);
 704         return 0;
 705 }
 706
 707 int tegra_usb_phy_clk_disable(struct tegra_usb_phy *phy)
 708 {
 709         if (phy->instance != 1)
 710                 utmi_phy_clk_disable(phy);
 711
 712         return 0;
 713 }
 714
 715 int tegra_usb_phy_clk_enable(struct tegra_usb_phy *phy)
 716 {
 717         if (phy->instance != 1)
 718                 utmi_phy_clk_enable(phy);
 719
 720         return 0;
 721 }
 722
 723 int tegra_usb_phy_close(struct tegra_usb_phy *phy)
 724 {
 725         if (phy->instance == 1)
 726                 clk_put(phy->clk);
 727         else
 728                 utmip_pad_close(phy);
 729         clk_disable(phy->pll_u);
 730         clk_put(phy->pll_u);
 731         kfree(phy);
 732         return 0;
 733 }