2 * Copyright (C) 2011 Google, Inc.
5 * Colin Cross <ccross@android.com>
7 * This software is licensed under the terms of the GNU General Public
8 * License version 2, as published by the Free Software Foundation, and
9 * may be copied, distributed, and modified under those terms.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
18 #include <linux/kernel.h>
19 #include <linux/device.h>
20 #include <linux/clk.h>
21 #include <linux/err.h>
23 #include <linux/module.h>
24 #include <linux/platform_device.h>
25 #include <linux/platform_data/tegra_emc.h>
27 #include <mach/iomap.h>
29 #include "tegra2_emc.h"
31 #ifdef CONFIG_TEGRA_EMC_SCALING_ENABLE
32 static bool emc_enable = true;
34 static bool emc_enable;
36 module_param(emc_enable, bool, 0644);
38 static struct platform_device *emc_pdev;
39 static void __iomem *emc_regbase;
41 static inline void emc_writel(u32 val, unsigned long addr)
43 writel(val, emc_regbase + addr);
46 static inline u32 emc_readl(unsigned long addr)
48 return readl(emc_regbase + addr);
51 static const unsigned long emc_reg_addr[TEGRA_EMC_NUM_REGS] = {
70 0x74, /* BURST_REFRESH_NUM */
81 0xa0, /* TCLKSTABLE */
84 0xac, /* QUSE_EXTRA */
85 0x114, /* FBIO_CFG6 */
88 0x104, /* FBIO_CFG5 */
89 0x2bc, /* CFG_DIG_DLL */
90 0x2c0, /* DLL_XFORM_DQS */
91 0x2c4, /* DLL_XFORM_QUSE */
92 0x2e0, /* ZCAL_REF_CNT */
93 0x2e4, /* ZCAL_WAIT_CNT */
94 0x2a8, /* AUTO_CAL_INTERVAL */
95 0x2d0, /* CFG_CLKTRIM_0 */
96 0x2d4, /* CFG_CLKTRIM_1 */
97 0x2d8, /* CFG_CLKTRIM_2 */
100 /* Select the closest EMC rate that is higher than the requested rate */
101 long tegra_emc_round_rate(unsigned long rate)
103 struct tegra_emc_pdata *pdata;
106 unsigned long distance = ULONG_MAX;
111 pdata = emc_pdev->dev.platform_data;
113 pr_debug("%s: %lu\n", __func__, rate);
116 * The EMC clock rate is twice the bus rate, and the bus rate is
119 rate = rate / 2 / 1000;
121 for (i = 0; i < pdata->num_tables; i++) {
122 if (pdata->tables[i].rate >= rate &&
123 (pdata->tables[i].rate - rate) < distance) {
124 distance = pdata->tables[i].rate - rate;
132 pr_debug("%s: using %lu\n", __func__, pdata->tables[best].rate);
134 return pdata->tables[best].rate * 2 * 1000;
138 * The EMC registers have shadow registers. When the EMC clock is updated
139 * in the clock controller, the shadow registers are copied to the active
140 * registers, allowing glitchless memory bus frequency changes.
141 * This function updates the shadow registers for a new clock frequency,
142 * and relies on the clock lock on the emc clock to avoid races between
143 * multiple frequency changes
145 int tegra_emc_set_rate(unsigned long rate)
147 struct tegra_emc_pdata *pdata;
154 pdata = emc_pdev->dev.platform_data;
157 * The EMC clock rate is twice the bus rate, and the bus rate is
160 rate = rate / 2 / 1000;
162 for (i = 0; i < pdata->num_tables; i++)
163 if (pdata->tables[i].rate == rate)
166 if (i >= pdata->num_tables)
169 pr_debug("%s: setting to %lu\n", __func__, rate);
171 for (j = 0; j < TEGRA_EMC_NUM_REGS; j++)
172 emc_writel(pdata->tables[i].regs[j], emc_reg_addr[j]);
174 emc_readl(pdata->tables[i].regs[TEGRA_EMC_NUM_REGS - 1]);
179 static int __devinit tegra_emc_probe(struct platform_device *pdev)
181 struct tegra_emc_pdata *pdata;
182 struct resource *res;
185 dev_err(&pdev->dev, "disabled per module parameter\n");
189 pdata = pdev->dev.platform_data;
192 dev_err(&pdev->dev, "missing platform data\n");
196 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
198 dev_err(&pdev->dev, "missing register base\n");
202 emc_regbase = devm_request_and_ioremap(&pdev->dev, res);
204 dev_err(&pdev->dev, "failed to remap registers\n");
212 static struct platform_driver tegra_emc_driver = {
215 .owner = THIS_MODULE,
217 .probe = tegra_emc_probe,
220 static int __init tegra_emc_init(void)
222 return platform_driver_register(&tegra_emc_driver);
224 device_initcall(tegra_emc_init);