2 * arch/arm/mach-tegra/tegra2_dvfs.c
4 * Copyright (C) 2010 Google, Inc.
7 * Colin Cross <ccross@google.com>
9 * This software is licensed under the terms of the GNU General Public
10 * License version 2, as published by the Free Software Foundation, and
11 * may be copied, distributed, and modified under those terms.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
20 #include <linux/kernel.h>
21 #include <linux/init.h>
22 #include <linux/string.h>
23 #include <linux/module.h>
29 #ifdef CONFIG_TEGRA_CORE_DVFS
30 static bool tegra_dvfs_core_disabled;
32 static bool tegra_dvfs_core_disabled = true;
34 #ifdef CONFIG_TEGRA_CPU_DVFS
35 static bool tegra_dvfs_cpu_disabled;
37 static bool tegra_dvfs_cpu_disabled = true;
40 static const int core_millivolts[MAX_DVFS_FREQS] =
41 {950, 1000, 1100, 1200, 1275};
42 static const int cpu_millivolts[MAX_DVFS_FREQS] =
43 {750, 775, 800, 825, 875, 900, 925, 975, 1000, 1050, 1100};
48 static struct dvfs_rail tegra2_dvfs_rail_vdd_cpu = {
50 .max_millivolts = 1100,
51 .min_millivolts = 750,
52 .nominal_millivolts = 1100,
55 static struct dvfs_rail tegra2_dvfs_rail_vdd_core = {
57 .max_millivolts = 1275,
58 .min_millivolts = 950,
59 .nominal_millivolts = 1200,
60 .step = 150, /* step vdd_core by 150 mV to allow vdd_aon to follow */
63 static struct dvfs_rail tegra2_dvfs_rail_vdd_aon = {
65 .max_millivolts = 1275,
66 .min_millivolts = 950,
67 .nominal_millivolts = 1200,
68 #ifndef CONFIG_TEGRA_CORE_DVFS
73 /* vdd_core and vdd_aon must be 50 mV higher than vdd_cpu */
74 static int tegra2_dvfs_rel_vdd_cpu_vdd_core(struct dvfs_rail *vdd_cpu,
75 struct dvfs_rail *vdd_core)
77 if (vdd_cpu->new_millivolts > vdd_cpu->millivolts &&
78 vdd_core->new_millivolts < vdd_cpu->new_millivolts + 50)
79 return vdd_cpu->new_millivolts + 50;
81 if (vdd_core->new_millivolts < vdd_cpu->millivolts + 50)
82 return vdd_cpu->millivolts + 50;
84 return vdd_core->new_millivolts;
87 /* vdd_aon must be within 170 mV of vdd_core */
88 static int tegra2_dvfs_rel_vdd_core_vdd_aon(struct dvfs_rail *vdd_core,
89 struct dvfs_rail *vdd_aon)
91 BUG_ON(abs(vdd_aon->millivolts - vdd_core->millivolts) >
93 return vdd_core->millivolts;
96 static struct dvfs_relationship tegra2_dvfs_relationships[] = {
98 /* vdd_core must be 50 mV higher than vdd_cpu */
99 .from = &tegra2_dvfs_rail_vdd_cpu,
100 .to = &tegra2_dvfs_rail_vdd_core,
101 .solve = tegra2_dvfs_rel_vdd_cpu_vdd_core,
104 /* vdd_aon must be 50 mV higher than vdd_cpu */
105 .from = &tegra2_dvfs_rail_vdd_cpu,
106 .to = &tegra2_dvfs_rail_vdd_aon,
107 .solve = tegra2_dvfs_rel_vdd_cpu_vdd_core,
110 /* vdd_aon must be within 170 mV of vdd_core */
111 .from = &tegra2_dvfs_rail_vdd_core,
112 .to = &tegra2_dvfs_rail_vdd_aon,
113 .solve = tegra2_dvfs_rel_vdd_core_vdd_aon,
117 static struct dvfs_rail *tegra2_dvfs_rails[] = {
118 &tegra2_dvfs_rail_vdd_cpu,
119 &tegra2_dvfs_rail_vdd_core,
120 &tegra2_dvfs_rail_vdd_aon,
123 #define CPU_DVFS(_clk_name, _process_id, _mult, _freqs...) \
125 .clk_name = _clk_name, \
126 .cpu_process_id = _process_id, \
128 .freqs_mult = _mult, \
129 .millivolts = cpu_millivolts, \
131 .dvfs_rail = &tegra2_dvfs_rail_vdd_cpu, \
134 #define CORE_DVFS(_clk_name, _auto, _mult, _freqs...) \
136 .clk_name = _clk_name, \
137 .cpu_process_id = -1, \
139 .freqs_mult = _mult, \
140 .millivolts = core_millivolts, \
141 .auto_dvfs = _auto, \
142 .dvfs_rail = &tegra2_dvfs_rail_vdd_core, \
145 static struct dvfs dvfs_init[] = {
146 /* Cpu voltages (mV): 750, 775, 800, 825, 875, 900, 925, 975, 1000, 1050, 1100 */
147 CPU_DVFS("cpu", 0, MHZ, 314, 314, 314, 456, 456, 608, 608, 760, 817, 912, 1000),
148 CPU_DVFS("cpu", 1, MHZ, 314, 314, 314, 456, 456, 618, 618, 770, 827, 922, 1000),
149 CPU_DVFS("cpu", 2, MHZ, 494, 675, 675, 675, 817, 817, 922, 1000),
150 CPU_DVFS("cpu", 3, MHZ, 730, 760, 845, 845, 1000),
152 /* Core voltages (mV): 950, 1000, 1100, 1200, 1275 */
153 CORE_DVFS("emc", 1, KHZ, 57000, 333000, 333000, 666000, 666000),
157 * The sdhci core calls the clock ops with a spinlock held, which
158 * conflicts with the sleeping dvfs api.
159 * For now, boards must ensure that the core voltage does not drop
160 * below 1V, or that the sdmmc busses are set to 44 MHz or less.
162 CORE_DVFS("sdmmc1", 1, KHZ, 44000, 52000, 52000, 52000, 52000),
163 CORE_DVFS("sdmmc2", 1, KHZ, 44000, 52000, 52000, 52000, 52000),
164 CORE_DVFS("sdmmc3", 1, KHZ, 44000, 52000, 52000, 52000, 52000),
165 CORE_DVFS("sdmmc4", 1, KHZ, 44000, 52000, 52000, 52000, 52000),
168 CORE_DVFS("ndflash", 1, KHZ, 130000, 150000, 158000, 164000, 164000),
169 CORE_DVFS("nor", 1, KHZ, 0, 92000, 92000, 92000, 92000),
170 CORE_DVFS("ide", 1, KHZ, 0, 0, 100000, 100000, 100000),
171 CORE_DVFS("mipi", 1, KHZ, 0, 40000, 40000, 40000, 60000),
172 CORE_DVFS("usbd", 1, KHZ, 0, 0, 0, 480000, 480000),
173 CORE_DVFS("usb2", 1, KHZ, 0, 0, 0, 480000, 480000),
174 CORE_DVFS("usb3", 1, KHZ, 0, 0, 0, 480000, 480000),
175 CORE_DVFS("pcie", 1, KHZ, 0, 0, 0, 250000, 250000),
176 CORE_DVFS("dsi", 1, KHZ, 100000, 100000, 100000, 500000, 500000),
177 CORE_DVFS("tvo", 1, KHZ, 0, 0, 0, 250000, 250000),
180 * The clock rate for the display controllers that determines the
181 * necessary core voltage depends on a divider that is internal
182 * to the display block. Disable auto-dvfs on the display clocks,
183 * and let the display driver call tegra_dvfs_set_rate manually
185 CORE_DVFS("disp1", 0, KHZ, 158000, 158000, 190000, 190000, 190000),
186 CORE_DVFS("disp2", 0, KHZ, 158000, 158000, 190000, 190000, 190000),
187 CORE_DVFS("hdmi", 0, KHZ, 0, 0, 0, 148500, 148500),
190 * These clocks technically depend on the core process id,
191 * but just use the worst case value for now
193 CORE_DVFS("host1x", 1, KHZ, 104500, 133000, 166000, 166000, 166000),
194 CORE_DVFS("epp", 1, KHZ, 133000, 171000, 247000, 300000, 300000),
195 CORE_DVFS("2d", 1, KHZ, 133000, 171000, 247000, 300000, 300000),
196 CORE_DVFS("3d", 1, KHZ, 114000, 161500, 247000, 300000, 300000),
197 CORE_DVFS("mpe", 1, KHZ, 104500, 152000, 228000, 250000, 250000),
198 CORE_DVFS("vi", 1, KHZ, 85000, 100000, 150000, 150000, 150000),
199 CORE_DVFS("sclk", 1, KHZ, 95000, 133000, 190000, 250000, 250000),
200 CORE_DVFS("vde", 1, KHZ, 95000, 123500, 209000, 250000, 250000),
202 CORE_DVFS("NVRM_DEVID_CLK_SRC", 1, MHZ, 480, 600, 800, 1067, 1067),
205 int tegra_dvfs_disable_core_set(const char *arg, const struct kernel_param *kp)
209 ret = param_set_bool(arg, kp);
213 if (tegra_dvfs_core_disabled)
214 tegra_dvfs_rail_disable(&tegra2_dvfs_rail_vdd_core);
216 tegra_dvfs_rail_enable(&tegra2_dvfs_rail_vdd_core);
221 int tegra_dvfs_disable_cpu_set(const char *arg, const struct kernel_param *kp)
225 ret = param_set_bool(arg, kp);
229 if (tegra_dvfs_cpu_disabled)
230 tegra_dvfs_rail_disable(&tegra2_dvfs_rail_vdd_cpu);
232 tegra_dvfs_rail_enable(&tegra2_dvfs_rail_vdd_cpu);
237 int tegra_dvfs_disable_get(char *buffer, const struct kernel_param *kp)
239 return param_get_bool(buffer, kp);
242 static struct kernel_param_ops tegra_dvfs_disable_core_ops = {
243 .set = tegra_dvfs_disable_core_set,
244 .get = tegra_dvfs_disable_get,
247 static struct kernel_param_ops tegra_dvfs_disable_cpu_ops = {
248 .set = tegra_dvfs_disable_cpu_set,
249 .get = tegra_dvfs_disable_get,
252 module_param_cb(disable_core, &tegra_dvfs_disable_core_ops,
253 &tegra_dvfs_core_disabled, 0644);
254 module_param_cb(disable_cpu, &tegra_dvfs_disable_cpu_ops,
255 &tegra_dvfs_cpu_disabled, 0644);
257 void __init tegra2_init_dvfs(void)
263 int cpu_process_id = tegra_cpu_process_id();
265 tegra_dvfs_init_rails(tegra2_dvfs_rails, ARRAY_SIZE(tegra2_dvfs_rails));
266 tegra_dvfs_add_relationships(tegra2_dvfs_relationships,
267 ARRAY_SIZE(tegra2_dvfs_relationships));
269 * VDD_CORE must always be at least 50 mV higher than VDD_CPU
270 * Fill out cpu_core_millivolts based on cpu_millivolts
272 for (i = 0; i < ARRAY_SIZE(dvfs_init); i++) {
275 if (d->cpu_process_id != -1 &&
276 d->cpu_process_id != cpu_process_id)
279 c = tegra_get_clock_by_name(d->clk_name);
282 pr_debug("tegra_dvfs: no clock found for %s\n",
287 ret = tegra_enable_dvfs_on_clk(c, d);
289 pr_err("tegra_dvfs: failed to enable dvfs on %s\n",
293 if (tegra_dvfs_core_disabled)
294 tegra_dvfs_rail_disable(&tegra2_dvfs_rail_vdd_core);
296 if (tegra_dvfs_cpu_disabled)
297 tegra_dvfs_rail_disable(&tegra2_dvfs_rail_vdd_cpu);