2 * Copyright (c) 2012, NVIDIA Corporation. All rights reserved.
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
17 #include <linux/linkage.h>
18 #include <linux/init.h>
20 #include <asm/cache.h>
21 #include <asm/asm-offsets.h>
22 #include <asm/hardware/cache-l2x0.h>
29 #define APB_MISC_GP_HIDREV 0x804
30 #define PMC_SCRATCH41 0x140
32 #define RESET_DATA(x) ((TEGRA_RESET_##x)*4)
34 #ifdef CONFIG_PM_SLEEP
38 * CPU boot vector when restarting the a CPU following
39 * an LP2 transition. Also branched to by LP0 and LP1 resume after
50 #ifdef CONFIG_ARCH_TEGRA_3x_SOC
51 /* Are we on Tegra20? */
52 mov32 r6, TEGRA_APB_MISC_BASE
53 ldr r0, [r6, #APB_MISC_GP_HIDREV]
57 /* Clear the flow controller flags for this CPU. */
58 mov32 r2, TEGRA_FLOW_CTRL_BASE + FLOW_CTRL_CPU0_CSR @ CPU0 CSR
60 /* Clear event & intr flag */
62 #FLOW_CTRL_CSR_INTR_FLAG | FLOW_CTRL_CSR_EVENT_FLAG
63 movw r0, #0x0FFD @ enable, cluster_switch, immed, & bitmaps
69 #ifdef CONFIG_HAVE_ARM_SCU
71 mov32 r0, TEGRA_ARM_PERIF_BASE
77 /* L2 cache resume & re-enable */
78 l2_cache_resume r0, r1, r2, l2x0_saved_regs_addr
84 #ifdef CONFIG_CACHE_L2X0
85 .globl l2x0_saved_regs_addr
91 ENTRY(__tegra_cpu_reset_handler_start)
94 * __tegra_cpu_reset_handler:
96 * Common handler for all CPU reset events.
98 * Register usage within the reset handler:
102 * R7 = CPU present (to the OS) mask
103 * R8 = CPU in LP1 state mask
104 * R9 = CPU in LP2 state mask
107 * R12 = pointer to reset handler data
109 * NOTE: This code is copied to IRAM. All code and data accesses
110 * must be position-independent.
113 .align L1_CACHE_SHIFT
114 ENTRY(__tegra_cpu_reset_handler)
116 cpsid aif, 0x13 @ SVC mode, interrupts disabled
118 mov32 r6, TEGRA_APB_MISC_BASE
119 ldr r6, [r6, #APB_MISC_GP_HIDREV]
121 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
126 # Tegra20 is a Cortex-A9 r1p1
127 mrc p15, 0, r0, c1, c0, 0 @ read system control register
128 orr r0, r0, #1 << 14 @ erratum 716044
129 mcr p15, 0, r0, c1, c0, 0 @ write system control register
130 mrc p15, 0, r0, c15, c0, 1 @ read diagnostic register
131 orr r0, r0, #1 << 4 @ erratum 742230
132 orr r0, r0, #1 << 11 @ erratum 751472
133 mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register
137 #ifdef CONFIG_ARCH_TEGRA_3x_SOC
142 # Tegra30 is a Cortex-A9 r2p9
143 mrc p15, 0, r0, c15, c0, 1 @ read diagnostic register
144 orr r0, r0, #1 << 6 @ erratum 743622
145 orr r0, r0, #1 << 11 @ erratum 751472
146 mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register
151 mrc p15, 0, r10, c0, c0, 5 @ MPIDR
152 and r10, r10, #0x3 @ R10 = CPU number
154 mov r11, r11, lsl r10 @ R11 = CPU mask
155 adr r12, __tegra_cpu_reset_handler_data
158 /* Does the OS know about this CPU? */
159 ldr r7, [r12, #RESET_DATA(MASK_PRESENT)]
160 tst r7, r11 @ if !present
161 bleq __die @ CPU not present (to OS)
164 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
165 /* Are we on Tegra20? */
168 /* If not CPU0, don't let CPU0 reset CPU1 now that CPU1 is coming up. */
169 mov32 r5, TEGRA_PMC_BASE
172 strne r0, [r5, #PMC_SCRATCH41]
176 /* Waking up from LP2? */
177 ldr r9, [r12, #RESET_DATA(MASK_LP2)]
178 tst r9, r11 @ if in_lp2
180 ldr lr, [r12, #RESET_DATA(STARTUP_LP2)]
182 bleq __die @ no LP2 startup handler
189 * Can only be secondary boot (initial or hotplug) but CPU 0
193 bleq __die @ CPU0 cannot be here
194 ldr lr, [r12, #RESET_DATA(STARTUP_SECONDARY)]
196 bleq __die @ no secondary startup handler
201 * We don't know why the CPU reset. Just kill it.
202 * The LR register will contain the address we died at + 4.
207 mov32 r7, TEGRA_PMC_BASE
208 str lr, [r7, #PMC_SCRATCH41]
210 mov32 r7, TEGRA_CLK_RESET_BASE
212 /* Are we on Tegra20? */
213 mov32 r6, TEGRA_APB_MISC_BASE
214 ldr r0, [r6, #APB_MISC_GP_HIDREV]
219 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
222 str r1, [r7, #0x340] @ CLK_RST_CPU_CMPLX_SET
225 #ifdef CONFIG_ARCH_TEGRA_3x_SOC
226 mov32 r6, TEGRA_FLOW_CTRL_BASE
229 moveq r1, #FLOW_CTRL_HALT_CPU0_EVENTS
230 moveq r2, #FLOW_CTRL_CPU0_CSR
231 movne r1, r10, lsl #3
232 addne r2, r1, #(FLOW_CTRL_CPU1_CSR-8)
233 addne r1, r1, #(FLOW_CTRL_HALT_CPU1_EVENTS-8)
235 /* Clear CPU "event" and "interrupt" flags and power gate
236 it when halting but not before it is in the "WFI" state. */
238 orr r0, r0, #FLOW_CTRL_CSR_INTR_FLAG | FLOW_CTRL_CSR_EVENT_FLAG
239 orr r0, r0, #FLOW_CTRL_CSR_ENABLE
242 /* Unconditionally halt this CPU */
243 mov r0, #FLOW_CTRL_WAITEVENT
245 ldr r0, [r6, +r1] @ memory barrier
249 wfi @ CPU should be power gated here
251 /* If the CPU didn't power gate above just kill it's clock. */
254 str r0, [r7, #348] @ CLK_CPU_CMPLX_SET
257 /* If the CPU still isn't dead, just spin here. */
259 ENDPROC(__tegra_cpu_reset_handler)
261 .align L1_CACHE_SHIFT
262 .type __tegra_cpu_reset_handler_data, %object
263 .globl __tegra_cpu_reset_handler_data
264 __tegra_cpu_reset_handler_data:
265 .rept TEGRA_RESET_DATA_SIZE
268 .align L1_CACHE_SHIFT
270 ENTRY(__tegra_cpu_reset_handler_end)