2 * arch/arm/mach-tegra/power.h
4 * Declarations for power state transition code
6 * Copyright (c) 2010, NVIDIA Corporation.
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
13 * This program is distributed in the hope that it will be useful, but WITHOUT
14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
18 * You should have received a copy of the GNU General Public License along
19 * with this program; if not, write to the Free Software Foundation, Inc.,
20 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
23 #ifndef __MACH_TEGRA_POWER_H
24 #define __MACH_TEGRA_POWER_H
28 #define TEGRA_POWER_SDRAM_SELFREFRESH 0x400 /* SDRAM is in self-refresh */
30 #define TEGRA_POWER_PWRREQ_POLARITY 0x1 /* core power request polarity */
31 #define TEGRA_POWER_PWRREQ_OE 0x2 /* core power request enable */
32 #define TEGRA_POWER_SYSCLK_POLARITY 0x4 /* sys clk polarity */
33 #define TEGRA_POWER_SYSCLK_OE 0x8 /* system clock enable */
34 #define TEGRA_POWER_PWRGATE_DIS 0x10 /* power gate disabled */
35 #define TEGRA_POWER_EFFECT_LP0 0x40 /* enter LP0 when CPU pwr gated */
36 #define TEGRA_POWER_CPU_PWRREQ_POLARITY 0x80 /* CPU power request polarity */
37 #define TEGRA_POWER_CPU_PWRREQ_OE 0x100 /* CPU power request enable */
38 #define TEGRA_POWER_PMC_SHIFT 8
39 #define TEGRA_POWER_PMC_MASK 0x1ff
41 /* CPU Context area (1KB per CPU) */
42 #define CONTEXT_SIZE_BYTES_SHIFT 10
43 #define CONTEXT_SIZE_BYTES (1<<CONTEXT_SIZE_BYTES_SHIFT)
45 /* layout of IRAM used for LP1 save & restore */
46 #define TEGRA_IRAM_CODE_AREA TEGRA_IRAM_BASE + SZ_4K
47 #define TEGRA_IRAM_CODE_SIZE SZ_4K
50 extern void *tegra_context_area;
52 u64 tegra_rtc_read_ms(void);
53 void tegra_lp2_set_trigger(unsigned long cycles);
54 unsigned long tegra_lp2_timer_remain(void);
55 void __cortex_a9_save(unsigned int mode);
56 void __cortex_a9_restore(void);
57 void __shut_off_mmu(void);
58 void tegra_lp2_startup(void);
59 unsigned int tegra_suspend_lp2(unsigned int us);
60 void tegra_hotplug_startup(void);