2 * arch/arm/mach-tegra/include/mach/dc.h
4 * Copyright (C) 2010 Google, Inc.
7 * Erik Gilling <konkers@google.com>
9 * This software is licensed under the terms of the GNU General Public
10 * License version 2, as published by the Free Software Foundation, and
11 * may be copied, distributed, and modified under those terms.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
20 #ifndef __MACH_TEGRA_DC_H
21 #define __MACH_TEGRA_DC_H
25 #define TEGRA_MAX_DC 2
26 #define DC_N_WINDOWS 3
28 struct tegra_dc_mode {
43 #define TEGRA_DC_MODE_FLAG_NEG_V_SYNC (1 << 0)
44 #define TEGRA_DC_MODE_FLAG_NEG_H_SYNC (1 << 1)
66 unsigned height; /* mm */
67 unsigned width; /* mm */
69 struct tegra_dc_mode *modes;
76 /* bits for tegra_dc_out.flags */
77 #define TEGRA_DC_OUT_HOTPLUG_HIGH (0 << 1)
78 #define TEGRA_DC_OUT_HOTPLUG_LOW (1 << 1)
79 #define TEGRA_DC_OUT_HOTPLUG_MASK (1 << 1)
80 #define TEGRA_DC_OUT_NVHDCP_POLICY_ALWAYS_ON (0 << 2)
81 #define TEGRA_DC_OUT_NVHDCP_POLICY_ON_DEMAND (1 << 2)
82 #define TEGRA_DC_OUT_NVHDCP_POLICY_MASK (1 << 2)
84 #define TEGRA_DC_ALIGN_MSB 0
85 #define TEGRA_DC_ALIGN_LSB 1
87 #define TEGRA_DC_ORDER_RED_BLUE 0
88 #define TEGRA_DC_ORDER_BLUE_RED 1
91 struct nvmap_handle_ref;
118 struct nvmap_handle_ref *cur_handle;
122 #define TEGRA_WIN_FLAG_ENABLED (1 << 0)
123 #define TEGRA_WIN_FLAG_BLEND_PREMULT (1 << 1)
124 #define TEGRA_WIN_FLAG_BLEND_COVERAGE (1 << 2)
125 #define TEGRA_WIN_FLAG_INVERT_H (1 << 3)
126 #define TEGRA_WIN_FLAG_INVERT_V (1 << 4)
127 #define TEGRA_WIN_FLAG_TILED (1 << 5)
129 #define TEGRA_WIN_BLEND_FLAGS_MASK \
130 (TEGRA_WIN_FLAG_BLEND_PREMULT | TEGRA_WIN_FLAG_BLEND_COVERAGE)
132 /* Note: These are the actual values written to the DC_WIN_COLOR_DEPTH register
133 * and may change in new tegra architectures.
135 #define TEGRA_WIN_FMT_P1 0
136 #define TEGRA_WIN_FMT_P2 1
137 #define TEGRA_WIN_FMT_P4 2
138 #define TEGRA_WIN_FMT_P8 3
139 #define TEGRA_WIN_FMT_B4G4R4A4 4
140 #define TEGRA_WIN_FMT_B5G5R5A 5
141 #define TEGRA_WIN_FMT_B5G6R5 6
142 #define TEGRA_WIN_FMT_AB5G5R5 7
143 #define TEGRA_WIN_FMT_B8G8R8A8 12
144 #define TEGRA_WIN_FMT_R8G8B8A8 13
145 #define TEGRA_WIN_FMT_B6x2G6x2R6x2A8 14
146 #define TEGRA_WIN_FMT_R6x2G6x2B6x2A8 15
147 #define TEGRA_WIN_FMT_YCbCr422 16
148 #define TEGRA_WIN_FMT_YUV422 17
149 #define TEGRA_WIN_FMT_YCbCr420P 18
150 #define TEGRA_WIN_FMT_YUV420P 19
151 #define TEGRA_WIN_FMT_YCbCr422P 20
152 #define TEGRA_WIN_FMT_YUV422P 21
153 #define TEGRA_WIN_FMT_YCbCr422R 22
154 #define TEGRA_WIN_FMT_YUV422R 23
155 #define TEGRA_WIN_FMT_YCbCr422RA 24
156 #define TEGRA_WIN_FMT_YUV422RA 25
158 struct tegra_fb_data {
163 int bits_per_pixel; /* -1 means autodetect */
168 #define TEGRA_FB_FLIP_ON_PROBE (1 << 0)
170 struct tegra_dc_platform_data {
172 unsigned long emc_clk_rate;
173 struct tegra_dc_out *default_out;
174 struct tegra_fb_data *fb;
177 #define TEGRA_DC_FLAG_ENABLED (1 << 0)
179 struct tegra_dc *tegra_dc_get_dc(unsigned idx);
180 struct tegra_dc_win *tegra_dc_get_window(struct tegra_dc *dc, unsigned win);
182 void tegra_dc_enable(struct tegra_dc *dc);
183 void tegra_dc_disable(struct tegra_dc *dc);
185 u32 tegra_dc_get_syncpt_id(const struct tegra_dc *dc);
186 u32 tegra_dc_incr_syncpt_max(struct tegra_dc *dc);
187 void tegra_dc_incr_syncpt_min(struct tegra_dc *dc, u32 val);
189 /* tegra_dc_update_windows and tegra_dc_sync_windows do not support windows
190 * with differenct dcs in one call
192 int tegra_dc_update_windows(struct tegra_dc_win *windows[], int n);
193 int tegra_dc_sync_windows(struct tegra_dc_win *windows[], int n);
195 int tegra_dc_set_mode(struct tegra_dc *dc, const struct tegra_dc_mode *mode);
197 unsigned tegra_dc_get_out_height(struct tegra_dc *dc);
198 unsigned tegra_dc_get_out_width(struct tegra_dc *dc);