2 * arch/arm/mach-tegra/fuse.c
4 * Copyright (C) 2010 Google, Inc.
7 * Colin Cross <ccross@android.com>
9 * This software is licensed under the terms of the GNU General Public
10 * License version 2, as published by the Free Software Foundation, and
11 * may be copied, distributed, and modified under those terms.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
20 #include <linux/kernel.h>
23 #include <mach/iomap.h>
28 #define FUSE_UID_LOW 0x108
29 #define FUSE_UID_HIGH 0x10c
30 #define FUSE_SKU_INFO 0x110
31 #define FUSE_SPARE_BIT 0x200
33 static const char *tegra_revision_name[TEGRA_REVISION_MAX] = {
34 [TEGRA_REVISION_UNKNOWN] = "unknown",
35 [TEGRA_REVISION_A02] = "A02",
36 [TEGRA_REVISION_A03] = "A03",
37 [TEGRA_REVISION_A03p] = "A03 prime",
40 u32 tegra_fuse_readl(unsigned long offset)
42 return tegra_apb_readl(TEGRA_FUSE_BASE + offset);
45 void tegra_fuse_writel(u32 value, unsigned long offset)
47 tegra_apb_writel(value, TEGRA_FUSE_BASE + offset);
50 static inline bool get_spare_fuse(int bit)
52 return tegra_fuse_readl(FUSE_SPARE_BIT + bit * 4);
55 void tegra_init_fuse(void)
57 u32 reg = readl(IO_TO_VIRT(TEGRA_CLK_RESET_BASE + 0x48));
59 writel(reg, IO_TO_VIRT(TEGRA_CLK_RESET_BASE + 0x48));
61 pr_info("Tegra Revision: %s SKU: %d CPU Process: %d Core Process: %d\n",
62 tegra_revision_name[tegra_get_revision()],
63 tegra_sku_id(), tegra_cpu_process_id(),
64 tegra_core_process_id());
67 unsigned long long tegra_chip_uid(void)
69 unsigned long long lo, hi;
71 lo = tegra_fuse_readl(FUSE_UID_LOW);
72 hi = tegra_fuse_readl(FUSE_UID_HIGH);
73 return (hi << 32ull) | lo;
76 int tegra_sku_id(void)
79 u32 reg = tegra_fuse_readl(FUSE_SKU_INFO);
84 int tegra_cpu_process_id(void)
87 u32 reg = tegra_fuse_readl(FUSE_SPARE_BIT);
88 cpu_process_id = (reg >> 6) & 3;
89 return cpu_process_id;
92 int tegra_core_process_id(void)
95 u32 reg = tegra_fuse_readl(FUSE_SPARE_BIT);
96 core_process_id = (reg >> 12) & 3;
97 return core_process_id;
100 enum tegra_revision tegra_get_revision(void)
102 void __iomem *chip_id = IO_ADDRESS(TEGRA_APB_MISC_BASE) + 0x804;
103 u32 id = readl(chip_id);
105 switch ((id >> 16) & 0xf) {
107 return TEGRA_REVISION_A02;
109 if (get_spare_fuse(18) || get_spare_fuse(19))
110 return TEGRA_REVISION_A03p;
112 return TEGRA_REVISION_A03;
114 return TEGRA_REVISION_UNKNOWN;