2 * arch/arm/mach-tegra/flowctrl.c
4 * functions and macros to control the flowcontroller
6 * Copyright (c) 2010-2012, NVIDIA Corporation. All rights reserved.
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms and conditions of the GNU General Public License,
10 * version 2, as published by the Free Software Foundation.
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
17 * You should have received a copy of the GNU General Public License
18 * along with this program. If not, see <http://www.gnu.org/licenses/>.
21 #include <linux/init.h>
22 #include <linux/kernel.h>
24 #include <linux/cpumask.h>
30 static u8 flowctrl_offset_halt_cpu[] = {
31 FLOW_CTRL_HALT_CPU0_EVENTS,
32 FLOW_CTRL_HALT_CPU1_EVENTS,
33 FLOW_CTRL_HALT_CPU1_EVENTS + 8,
34 FLOW_CTRL_HALT_CPU1_EVENTS + 16,
37 static u8 flowctrl_offset_cpu_csr[] = {
40 FLOW_CTRL_CPU1_CSR + 8,
41 FLOW_CTRL_CPU1_CSR + 16,
44 static void flowctrl_update(u8 offset, u32 value)
46 void __iomem *addr = IO_ADDRESS(TEGRA_FLOW_CTRL_BASE) + offset;
50 /* ensure the update has reached the flow controller */
55 u32 flowctrl_read_cpu_csr(unsigned int cpuid)
57 u8 offset = flowctrl_offset_cpu_csr[cpuid];
58 void __iomem *addr = IO_ADDRESS(TEGRA_FLOW_CTRL_BASE) + offset;
63 void flowctrl_write_cpu_csr(unsigned int cpuid, u32 value)
65 return flowctrl_update(flowctrl_offset_cpu_csr[cpuid], value);
68 void flowctrl_write_cpu_halt(unsigned int cpuid, u32 value)
70 return flowctrl_update(flowctrl_offset_halt_cpu[cpuid], value);
73 void flowctrl_cpu_suspend_enter(unsigned int cpuid)
78 reg = flowctrl_read_cpu_csr(cpuid);
79 switch (tegra_chip_id) {
81 /* clear wfe bitmap */
82 reg &= ~TEGRA20_FLOW_CTRL_CSR_WFE_BITMAP;
83 /* clear wfi bitmap */
84 reg &= ~TEGRA20_FLOW_CTRL_CSR_WFI_BITMAP;
85 /* pwr gating on wfe */
86 reg |= TEGRA20_FLOW_CTRL_CSR_WFE_CPU0 << cpuid;
91 /* clear wfe bitmap */
92 reg &= ~TEGRA30_FLOW_CTRL_CSR_WFE_BITMAP;
93 /* clear wfi bitmap */
94 reg &= ~TEGRA30_FLOW_CTRL_CSR_WFI_BITMAP;
95 /* pwr gating on wfi */
96 reg |= TEGRA30_FLOW_CTRL_CSR_WFI_CPU0 << cpuid;
99 reg |= FLOW_CTRL_CSR_INTR_FLAG; /* clear intr flag */
100 reg |= FLOW_CTRL_CSR_EVENT_FLAG; /* clear event flag */
101 reg |= FLOW_CTRL_CSR_ENABLE; /* pwr gating */
102 flowctrl_write_cpu_csr(cpuid, reg);
104 for (i = 0; i < num_possible_cpus(); i++) {
107 reg = flowctrl_read_cpu_csr(i);
108 reg |= FLOW_CTRL_CSR_EVENT_FLAG;
109 reg |= FLOW_CTRL_CSR_INTR_FLAG;
110 flowctrl_write_cpu_csr(i, reg);
114 void flowctrl_cpu_suspend_exit(unsigned int cpuid)
118 /* Disable powergating via flow controller for CPU0 */
119 reg = flowctrl_read_cpu_csr(cpuid);
120 switch (tegra_chip_id) {
122 /* clear wfe bitmap */
123 reg &= ~TEGRA20_FLOW_CTRL_CSR_WFE_BITMAP;
124 /* clear wfi bitmap */
125 reg &= ~TEGRA20_FLOW_CTRL_CSR_WFI_BITMAP;
130 /* clear wfe bitmap */
131 reg &= ~TEGRA30_FLOW_CTRL_CSR_WFE_BITMAP;
132 /* clear wfi bitmap */
133 reg &= ~TEGRA30_FLOW_CTRL_CSR_WFI_BITMAP;
136 reg &= ~FLOW_CTRL_CSR_ENABLE; /* clear enable */
137 reg |= FLOW_CTRL_CSR_INTR_FLAG; /* clear intr */
138 reg |= FLOW_CTRL_CSR_EVENT_FLAG; /* clear event */
139 flowctrl_write_cpu_csr(cpuid, reg);