2 * CPU idle driver for Tegra CPUs
4 * Copyright (c) 2010-2012, NVIDIA Corporation.
5 * Copyright (c) 2011 Google, Inc.
6 * Author: Colin Cross <ccross@android.com>
7 * Gary King <gking@nvidia.com>
9 * Rework for 3.3 by Peter De Schrijver <pdeschrijver@nvidia.com>
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
16 * This program is distributed in the hope that it will be useful, but WITHOUT
17 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
18 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
22 #include <linux/kernel.h>
23 #include <linux/module.h>
24 #include <linux/cpuidle.h>
25 #include <linux/cpu_pm.h>
26 #include <linux/clockchips.h>
27 #include <linux/clk/tegra.h>
29 #include <asm/cpuidle.h>
30 #include <asm/proc-fns.h>
31 #include <asm/suspend.h>
32 #include <asm/smp_plat.h>
37 #ifdef CONFIG_PM_SLEEP
38 static int tegra30_idle_lp2(struct cpuidle_device *dev,
39 struct cpuidle_driver *drv,
43 static struct cpuidle_driver tegra_idle_driver = {
46 #ifdef CONFIG_PM_SLEEP
52 [0] = ARM_CPUIDLE_WFI_STATE_PWR(600),
53 #ifdef CONFIG_PM_SLEEP
55 .enter = tegra30_idle_lp2,
57 .target_residency = 2200,
59 .flags = CPUIDLE_FLAG_TIME_VALID,
60 .name = "powered-down",
61 .desc = "CPU power gated",
67 #ifdef CONFIG_PM_SLEEP
68 static bool tegra30_cpu_cluster_power_down(struct cpuidle_device *dev,
69 struct cpuidle_driver *drv,
72 struct cpuidle_state *state = &drv->states[index];
73 u32 cpu_on_time = state->exit_latency;
74 u32 cpu_off_time = state->target_residency - state->exit_latency;
76 /* All CPUs entering LP2 is not working.
77 * Don't let CPU0 enter LP2 when any secondary CPU is online.
79 if (num_online_cpus() > 1 || !tegra_cpu_rail_off_ready()) {
84 clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, &dev->cpu);
86 tegra_idle_lp2_last(cpu_on_time, cpu_off_time);
88 clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &dev->cpu);
94 static bool tegra30_cpu_core_power_down(struct cpuidle_device *dev,
95 struct cpuidle_driver *drv,
98 clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, &dev->cpu);
102 save_cpu_arch_register();
104 cpu_suspend(0, tegra30_sleep_cpu_secondary_finish);
106 restore_cpu_arch_register();
108 clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &dev->cpu);
113 static inline bool tegra30_cpu_core_power_down(struct cpuidle_device *dev,
114 struct cpuidle_driver *drv,
121 static int tegra30_idle_lp2(struct cpuidle_device *dev,
122 struct cpuidle_driver *drv,
125 u32 cpu = is_smp() ? cpu_logical_map(dev->cpu) : dev->cpu;
126 bool entered_lp2 = false;
131 last_cpu = tegra_set_cpu_in_lp2(cpu);
136 entered_lp2 = tegra30_cpu_cluster_power_down(dev, drv,
141 entered_lp2 = tegra30_cpu_core_power_down(dev, drv, index);
145 tegra_clear_cpu_in_lp2(cpu);
151 return (entered_lp2) ? index : 0;
155 int __init tegra30_cpuidle_init(void)
157 #ifdef CONFIG_PM_SLEEP
158 tegra_tear_down_cpu = tegra30_tear_down_cpu;
160 return cpuidle_register(&tegra_idle_driver, NULL);