2 * arch/arm/mach-tegra/common.c
4 * Copyright (C) 2010 Google, Inc.
7 * Colin Cross <ccross@android.com>
9 * This software is licensed under the terms of the GNU General Public
10 * License version 2, as published by the Free Software Foundation, and
11 * may be copied, distributed, and modified under those terms.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
20 #include <linux/init.h>
22 #include <linux/clk.h>
23 #include <linux/delay.h>
24 #include <linux/of_irq.h>
26 #include <asm/hardware/cache-l2x0.h>
27 #include <asm/hardware/gic.h>
29 #include <mach/iomap.h>
36 static const struct of_device_id tegra_dt_irq_match[] __initconst = {
37 { .compatible = "arm,cortex-a9-gic", .data = gic_of_init },
41 void __init tegra_dt_init_irq(void)
44 of_irq_init(tegra_dt_irq_match);
48 void tegra_assert_system_reset(char mode, const char *cmd)
50 void __iomem *reset = IO_ADDRESS(TEGRA_PMC_BASE + 0);
53 reg = readl_relaxed(reset);
55 writel_relaxed(reg, reset);
58 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
59 static __initdata struct tegra_clk_init_table tegra20_clk_init_table[] = {
60 /* name parent rate enabled */
61 { "clk_m", NULL, 0, true },
62 { "pll_p", "clk_m", 216000000, true },
63 { "pll_p_out1", "pll_p", 28800000, true },
64 { "pll_p_out2", "pll_p", 48000000, true },
65 { "pll_p_out3", "pll_p", 72000000, true },
66 { "pll_p_out4", "pll_p", 108000000, true },
67 { "sclk", "pll_p_out4", 108000000, true },
68 { "hclk", "sclk", 108000000, true },
69 { "pclk", "hclk", 54000000, true },
70 { "csite", NULL, 0, true },
71 { "emc", NULL, 0, true },
72 { "cpu", NULL, 0, true },
77 static void __init tegra_init_cache(u32 tag_latency, u32 data_latency)
79 #ifdef CONFIG_CACHE_L2X0
80 void __iomem *p = IO_ADDRESS(TEGRA_ARM_PERIF_BASE) + 0x3000;
81 u32 aux_ctrl, cache_type;
83 writel_relaxed(tag_latency, p + L2X0_TAG_LATENCY_CTRL);
84 writel_relaxed(data_latency, p + L2X0_DATA_LATENCY_CTRL);
86 cache_type = readl(p + L2X0_CACHE_TYPE);
87 aux_ctrl = (cache_type & 0x700) << (17-8);
88 aux_ctrl |= 0x6C000001;
90 l2x0_init(p, aux_ctrl, 0x8200c3fe);
95 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
96 void __init tegra20_init_early(void)
98 disable_hlt(); /* idle WFI usage needs to be confirmed */
101 tegra2_init_clocks();
102 tegra_clk_init_from_table(tegra20_clk_init_table);
103 tegra_init_cache(0x331, 0x441);
106 #ifdef CONFIG_ARCH_TEGRA_3x_SOC
107 void __init tegra30_init_early(void)
109 tegra_init_cache(0x441, 0x551);