arch/arm/mach-tegra/board-stingray-power.c

   1 /*
   2  * Copyright (C) 2010 Motorola, Inc.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  *
   8  * This program is distributed in the hope that it will be useful,
   9  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11  * GNU General Public License for more details.
  12  *
  13  * You should have received a copy of the GNU General Public License
  14  * along with this program; if not, write to the Free Software
  15  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
  16  * 02111-1307, USA
  17  */
  18 #include <linux/gpio.h>
  19 #include <linux/i2c.h>
  20 #include <linux/init.h>
  21 #include <linux/io.h>
  22 #include <linux/irq.h>
  23 #include <linux/kernel.h>
  24 #include <linux/leds-ld-cpcap.h>
  25 #include <linux/module.h>
  26 #include <linux/platform_device.h>
  27 #include <linux/radio_ctrl/mdm6600_ctrl.h>
  28 #include <linux/radio_ctrl/wrigley_ctrl.h>
  29 #include <linux/reboot.h>
  30 #include <linux/regulator/consumer.h>
  31 #include <linux/regulator/driver.h>
  32 #include <linux/regulator/machine.h>
  33 #include <linux/regulator/max8649.h>
  34 #include <linux/spi/cpcap.h>
  35 #include <linux/spi/cpcap-regbits.h>
  36 #include <linux/spi/spi.h>
  37 #include <linux/l3g4200d.h>
  38
  39 #include <mach/gpio.h>
  40 #include <mach/iomap.h>
  41 #include <mach/irqs.h>
  42
  43 #include "board-stingray.h"
  44 #include "gpio-names.h"
  45
  46 /* For the PWR + VOL UP reset, CPCAP can perform a hard or a soft reset. A hard
  47  * reset will reset the entire system, where a soft reset will reset only the
  48  * T20. Uncomment this line to use soft resets (should not be enabled on
  49  * production builds). */
  50 /* #define ENABLE_SOFT_RESET_DEBUGGING */
  51
  52 static struct cpcap_device *cpcap_di;
  53
  54 static int cpcap_validity_reboot(struct notifier_block *this,
  55                                  unsigned long code, void *cmd)
  56 {
  57         int ret = -1;
  58         int result = NOTIFY_DONE;
  59         char *mode = cmd;
  60
  61         dev_info(&(cpcap_di->spi->dev), "Saving power down reason.\n");
  62
  63         if (code == SYS_RESTART) {
  64                 if (mode != NULL && !strncmp("outofcharge", mode, 12)) {
  65                         /* Set the outofcharge bit in the cpcap */
  66                         ret = cpcap_regacc_write(cpcap_di, CPCAP_REG_VAL1,
  67                                                  CPCAP_BIT_OUT_CHARGE_ONLY,
  68                                                  CPCAP_BIT_OUT_CHARGE_ONLY);
  69                         if (ret) {
  70                                 dev_err(&(cpcap_di->spi->dev),
  71                                         "outofcharge cpcap set failure.\n");
  72                                 result = NOTIFY_BAD;
  73                         }
  74                         /* Set the soft reset bit in the cpcap */
  75                         cpcap_regacc_write(cpcap_di, CPCAP_REG_VAL1,
  76                                            CPCAP_BIT_SOFT_RESET,
  77                                            CPCAP_BIT_SOFT_RESET);
  78                         if (ret) {
  79                                 dev_err(&(cpcap_di->spi->dev),
  80                                         "reset cpcap set failure.\n");
  81                                 result = NOTIFY_BAD;
  82                         }
  83                 }
  84
  85                 /* Check if we are starting recovery mode */
  86                 if (mode != NULL && !strncmp("recovery", mode, 9)) {
  87                         /* Set the fota (recovery mode) bit in the cpcap */
  88                         ret = cpcap_regacc_write(cpcap_di, CPCAP_REG_VAL1,
  89                                 CPCAP_BIT_FOTA_MODE, CPCAP_BIT_FOTA_MODE);
  90                         if (ret) {
  91                                 dev_err(&(cpcap_di->spi->dev),
  92                                         "Recovery cpcap set failure.\n");
  93                                 result = NOTIFY_BAD;
  94                         }
  95                 } else {
  96                         /* Set the fota (recovery mode) bit in the cpcap */
  97                         ret = cpcap_regacc_write(cpcap_di, CPCAP_REG_VAL1, 0,
  98                                                  CPCAP_BIT_FOTA_MODE);
  99                         if (ret) {
 100                                 dev_err(&(cpcap_di->spi->dev),
 101                                         "Recovery cpcap clear failure.\n");
 102                                 result = NOTIFY_BAD;
 103                         }
 104                 }
 105                 /* Check if we are going into fast boot mode */
 106                 if (mode != NULL && !strncmp("bootloader", mode, 11)) {
 107                         /* Set the bootmode bit in the cpcap */
 108                         ret = cpcap_regacc_write(cpcap_di, CPCAP_REG_VAL1,
 109                                 CPCAP_BIT_BOOT_MODE, CPCAP_BIT_BOOT_MODE);
 110                         if (ret) {
 111                                 dev_err(&(cpcap_di->spi->dev),
 112                                         "Boot mode cpcap set failure.\n");
 113                                 result = NOTIFY_BAD;
 114                         }
 115                 }
 116         } else {
 117                 ret = cpcap_regacc_write(cpcap_di, CPCAP_REG_VAL1,
 118                                          0,
 119                                          CPCAP_BIT_OUT_CHARGE_ONLY);
 120                 if (ret) {
 121                         dev_err(&(cpcap_di->spi->dev),
 122                                 "outofcharge cpcap set failure.\n");
 123                         result = NOTIFY_BAD;
 124                 }
 125
 126                 /* Clear the soft reset bit in the cpcap */
 127                 ret = cpcap_regacc_write(cpcap_di, CPCAP_REG_VAL1, 0,
 128                                          CPCAP_BIT_SOFT_RESET);
 129                 if (ret) {
 130                         dev_err(&(cpcap_di->spi->dev),
 131                                 "SW Reset cpcap set failure.\n");
 132                         result = NOTIFY_BAD;
 133                 }
 134                 /* Clear the fota (recovery mode) bit in the cpcap */
 135                 ret = cpcap_regacc_write(cpcap_di, CPCAP_REG_VAL1, 0,
 136                                          CPCAP_BIT_FOTA_MODE);
 137                 if (ret) {
 138                         dev_err(&(cpcap_di->spi->dev),
 139                                 "Recovery cpcap clear failure.\n");
 140                         result = NOTIFY_BAD;
 141                 }
 142         }
 143
 144         /* Always clear the kpanic bit */
 145         ret = cpcap_regacc_write(cpcap_di, CPCAP_REG_VAL1,
 146                                  0, CPCAP_BIT_AP_KERNEL_PANIC);
 147         if (ret) {
 148                 dev_err(&(cpcap_di->spi->dev),
 149                         "Clear kernel panic bit failure.\n");
 150                 result = NOTIFY_BAD;
 151         }
 152
 153         return result;
 154 }
 155 static struct notifier_block validity_reboot_notifier = {
 156         .notifier_call = cpcap_validity_reboot,
 157 };
 158
 159 static int cpcap_validity_probe(struct platform_device *pdev)
 160 {
 161         int err;
 162
 163         if (pdev->dev.platform_data == NULL) {
 164                 dev_err(&pdev->dev, "no platform_data\n");
 165                 return -EINVAL;
 166         }
 167
 168         cpcap_di = pdev->dev.platform_data;
 169
 170         cpcap_regacc_write(cpcap_di, CPCAP_REG_VAL1,
 171                            (CPCAP_BIT_AP_KERNEL_PANIC | CPCAP_BIT_SOFT_RESET),
 172                            (CPCAP_BIT_AP_KERNEL_PANIC | CPCAP_BIT_SOFT_RESET));
 173
 174         register_reboot_notifier(&validity_reboot_notifier);
 175
 176         /* CORE_PWR_REQ is only properly connected on P1 hardware and later */
 177         if (stingray_revision() >= STINGRAY_REVISION_P1) {
 178                 err = cpcap_uc_start(cpcap_di, CPCAP_MACRO_14);
 179                 dev_info(&pdev->dev, "Started macro 14: %d\n", err);
 180         } else
 181                 dev_info(&pdev->dev, "Not starting macro 14 (no hw support)\n");
 182
 183         /* Enable workaround to allow soft resets to work */
 184         cpcap_regacc_write(cpcap_di, CPCAP_REG_PGC,
 185                            CPCAP_BIT_SYS_RST_MODE, CPCAP_BIT_SYS_RST_MODE);
 186         err = cpcap_uc_start(cpcap_di, CPCAP_MACRO_15);
 187         dev_info(&pdev->dev, "Started macro 15: %d\n", err);
 188
 189         return 0;
 190 }
 191
 192 static int cpcap_validity_remove(struct platform_device *pdev)
 193 {
 194         unregister_reboot_notifier(&validity_reboot_notifier);
 195         cpcap_di = NULL;
 196
 197         return 0;
 198 }
 199
 200 static struct platform_driver cpcap_validity_driver = {
 201         .probe = cpcap_validity_probe,
 202         .remove = cpcap_validity_remove,
 203         .driver = {
 204                 .name = "cpcap_validity",
 205                 .owner  = THIS_MODULE,
 206         },
 207 };
 208
 209 static struct platform_device cpcap_validity_device = {
 210         .name   = "cpcap_validity",
 211         .id     = -1,
 212         .dev    = {
 213                 .platform_data  = NULL,
 214         },
 215 };
 216
 217 static struct platform_device cpcap_3mm5_device = {
 218         .name   = "cpcap_3mm5",
 219         .id     = -1,
 220         .dev    = {
 221                 .platform_data  = NULL,
 222         },
 223 };
 224
 225 static struct cpcap_whisper_pdata whisper_pdata = {
 226         .data_gpio = TEGRA_GPIO_PV4,
 227         .pwr_gpio  = TEGRA_GPIO_PT2,
 228         .uartmux   = 1,
 229 };
 230
 231 static struct platform_device cpcap_whisper_device = {
 232         .name   = "cpcap_whisper",
 233         .id     = -1,
 234         .dev    = {
 235                 .platform_data  = &whisper_pdata,
 236         },
 237 };
 238
 239 static struct cpcap_led stingray_privacy_led ={
 240         .blink_able = 0,
 241         .cpcap_register = CPCAP_REG_BLEDC,
 242         .cpcap_reg_mask = 0x03FF,
 243         .cpcap_reg_period = 0x0000,
 244         .cpcap_reg_duty_cycle = 0x0038,
 245         .cpcap_reg_current = 0x0002,
 246         .class_name = LD_PRIVACY_LED_DEV,
 247         .led_regulator = "sw5_led2",
 248 };
 249
 250 static struct platform_device cpcap_privacy_led = {
 251         .name   = LD_CPCAP_LED_DRV,
 252         .id     = 2,
 253         .dev    = {
 254                 .platform_data  = &stingray_privacy_led,
 255         },
 256 };
 257
 258 static struct cpcap_led stingray_notification_led ={
 259         .blink_able = 1,
 260         .cpcap_register = CPCAP_REG_ADLC,
 261         .cpcap_reg_mask = 0x7FFF,
 262         .cpcap_reg_period = 0x0000,
 263         .cpcap_reg_duty_cycle = 0x03F0,
 264         .cpcap_reg_current = 0x0008,
 265         .class_name = LD_NOTIF_LED_DEV,
 266         .led_regulator = "sw5_led3",
 267 };
 268
 269 static struct platform_device cpcap_notification_led = {
 270         .name   = LD_CPCAP_LED_DRV,
 271         .id     = 3,
 272         .dev    = {
 273                 .platform_data  = &stingray_notification_led,
 274         },
 275 };
 276
 277 static struct platform_device *cpcap_devices[] = {
 278         &cpcap_validity_device,
 279         &cpcap_notification_led,
 280         &cpcap_privacy_led,
 281         &cpcap_3mm5_device,
 282 };
 283
 284 struct cpcap_spi_init_data stingray_cpcap_spi_init[] = {
 285         {CPCAP_REG_S1C1,      0x0000},
 286         {CPCAP_REG_S1C2,      0x0000},
 287         {CPCAP_REG_S2C1,      0x4830},
 288         {CPCAP_REG_S2C2,      0x3030},
 289         {CPCAP_REG_S3C,       0x0439},
 290         {CPCAP_REG_S4C1,      0x4930},
 291         {CPCAP_REG_S4C2,      0x301C},
 292         {CPCAP_REG_S5C,       0x0000},
 293         {CPCAP_REG_S6C,       0x0000},
 294         {CPCAP_REG_VRF1C,     0x0000},
 295         {CPCAP_REG_VRF2C,     0x0000},
 296         {CPCAP_REG_VRFREFC,   0x0000},
 297         {CPCAP_REG_VAUDIOC,   0x0065},
 298         {CPCAP_REG_ADCC1,     0x9000},
 299         {CPCAP_REG_ADCC2,     0x4136},
 300         {CPCAP_REG_USBC1,     0x1201},
 301         {CPCAP_REG_USBC3,     0x7DFB},
 302         {CPCAP_REG_OWDC,      0x0003},
 303         {CPCAP_REG_ADLC,      0x0000},
 304 };
 305
 306 unsigned short cpcap_regulator_mode_values[CPCAP_NUM_REGULATORS] = {
 307         [CPCAP_SW2]      = 0x0800,
 308         [CPCAP_SW4]      = 0x0900,
 309         [CPCAP_SW5]      = 0x0022,
 310         [CPCAP_VCAM]     = 0x0007,
 311         [CPCAP_VCSI]     = 0x0007,
 312         [CPCAP_VDAC]     = 0x0003,
 313         [CPCAP_VDIG]     = 0x0005,
 314         [CPCAP_VFUSE]    = 0x0080,
 315         [CPCAP_VHVIO]    = 0x0002,
 316         [CPCAP_VSDIO]    = 0x0002,
 317         [CPCAP_VPLL]     = 0x0001,
 318         [CPCAP_VRF1]     = 0x000C,
 319         [CPCAP_VRF2]     = 0x0003,
 320         [CPCAP_VRFREF]   = 0x0003,
 321         [CPCAP_VWLAN1]   = 0x0005,
 322         [CPCAP_VWLAN2]   = 0x0008,
 323         [CPCAP_VSIM]     = 0x0003,
 324         [CPCAP_VSIMCARD] = 0x1E00,
 325         [CPCAP_VVIB]     = 0x0001,
 326         [CPCAP_VUSB]     = 0x000C,
 327         [CPCAP_VAUDIO]   = 0x0004,
 328 };
 329
 330 unsigned short cpcap_regulator_off_mode_values[CPCAP_NUM_REGULATORS] = {
 331         [CPCAP_SW2]      = 0x0000,
 332         [CPCAP_SW4]      = 0x0000,
 333         [CPCAP_SW5]      = 0x0000,
 334         [CPCAP_VCAM]     = 0x0000,
 335         [CPCAP_VCSI]     = 0x0000,
 336         [CPCAP_VDAC]     = 0x0000,
 337         [CPCAP_VDIG]     = 0x0000,
 338         [CPCAP_VFUSE]    = 0x0000,
 339         [CPCAP_VHVIO]    = 0x0000,
 340         [CPCAP_VSDIO]    = 0x0000,
 341         [CPCAP_VPLL]     = 0x0000,
 342         [CPCAP_VRF1]     = 0x0000,
 343         [CPCAP_VRF2]     = 0x0000,
 344         [CPCAP_VRFREF]   = 0x0000,
 345         [CPCAP_VWLAN1]   = 0x0000,
 346         [CPCAP_VWLAN2]   = 0x0000,
 347         [CPCAP_VSIM]     = 0x0000,
 348         [CPCAP_VSIMCARD] = 0x0000,
 349         [CPCAP_VVIB]     = 0x0000,
 350         [CPCAP_VUSB]     = 0x0000,
 351         [CPCAP_VAUDIO]   = 0x0000,
 352 };
 353
 354 #define REGULATOR_CONSUMER(name, device) { .supply = name, .dev_name = device, }
 355 #define REGULATOR_CONSUMER_BY_DEVICE(name, device) \
 356         { .supply = name, .dev = device, }
 357
 358 struct regulator_consumer_supply cpcap_sw2_consumers[] = {
 359         REGULATOR_CONSUMER("sw2", NULL),
 360         REGULATOR_CONSUMER("vdd_core", NULL),
 361 };
 362
 363 struct regulator_consumer_supply cpcap_sw4_consumers[] = {
 364         REGULATOR_CONSUMER("sw4", NULL),
 365         REGULATOR_CONSUMER("vdd_aon", NULL),
 366 };
 367
 368 struct regulator_consumer_supply cpcap_sw5_consumers[] = {
 369         REGULATOR_CONSUMER_BY_DEVICE("sw5_led2", &cpcap_privacy_led.dev),
 370         REGULATOR_CONSUMER_BY_DEVICE("sw5_led3", &cpcap_notification_led.dev),
 371 };
 372
 373 struct regulator_consumer_supply cpcap_vcam_consumers[] = {
 374         REGULATOR_CONSUMER("vcc", "2-000c" /* focuser */),
 375 };
 376
 377 struct regulator_consumer_supply cpcap_vhvio_consumers[] = {
 378         REGULATOR_CONSUMER("vhvio", NULL /* lighting_driver */),
 379         REGULATOR_CONSUMER("vcc", "2-0068" /* gyro*/),
 380         REGULATOR_CONSUMER("vcc", "3-000c" /* magnetometer */),
 381         REGULATOR_CONSUMER("vcc", "0-0077" /* barometer */),
 382         REGULATOR_CONSUMER("vcc", "3-000f" /* accelerometer */),
 383 };
 384
 385 struct regulator_consumer_supply cpcap_vcsi_consumers[] = {
 386         REGULATOR_CONSUMER("vcsi", "tegra_camera"),
 387 };
 388
 389 struct regulator_consumer_supply cpcap_vusb_consumers[] = {
 390         REGULATOR_CONSUMER_BY_DEVICE("vusb", &cpcap_whisper_device.dev),
 391 };
 392
 393 struct regulator_consumer_supply cpcap_vaudio_consumers[] = {
 394         REGULATOR_CONSUMER("vaudio", NULL /* mic opamp */),
 395 };
 396
 397 struct regulator_consumer_supply cpcap_vdig_consumers[] = {
 398         REGULATOR_CONSUMER("vdig", NULL /* gps */),
 399 };
 400 static struct regulator_init_data cpcap_regulator[CPCAP_NUM_REGULATORS] = {
 401         [CPCAP_SW2] = {
 402                 .constraints = {
 403                         .min_uV                 = 1000000,
 404                         .max_uV                 = 1200000,
 405                         .valid_ops_mask         = REGULATOR_CHANGE_VOLTAGE,
 406                         .always_on              = 1,
 407                 },
 408                 .num_consumer_supplies  = ARRAY_SIZE(cpcap_sw2_consumers),
 409                 .consumer_supplies      = cpcap_sw2_consumers,
 410         },
 411         [CPCAP_SW4] = {
 412                 .constraints = {
 413                         .min_uV                 = 1000000,
 414                         .max_uV                 = 1200000,
 415                         .valid_ops_mask         = REGULATOR_CHANGE_VOLTAGE,
 416                         .always_on              = 1,
 417                 },
 418                 .num_consumer_supplies  = ARRAY_SIZE(cpcap_sw4_consumers),
 419                 .consumer_supplies      = cpcap_sw4_consumers,
 420         },
 421         [CPCAP_SW5] = {
 422                 .constraints = {
 423                         .min_uV                 = 5050000,
 424                         .max_uV                 = 5050000,
 425                         .valid_ops_mask         = REGULATOR_CHANGE_STATUS,
 426                 },
 427                 .num_consumer_supplies  = ARRAY_SIZE(cpcap_sw5_consumers),
 428                 .consumer_supplies      = cpcap_sw5_consumers,
 429         },
 430         [CPCAP_VCAM] = {
 431                 .constraints = {
 432                         .min_uV                 = 2900000,
 433                         .max_uV                 = 2900000,
 434                         .valid_ops_mask         = REGULATOR_CHANGE_STATUS,
 435                         .apply_uV               = 1,
 436
 437                 },
 438                 .num_consumer_supplies  = ARRAY_SIZE(cpcap_vcam_consumers),
 439                 .consumer_supplies      = cpcap_vcam_consumers,
 440         },
 441         [CPCAP_VCSI] = {
 442                 .constraints = {
 443                         .min_uV                 = 1200000,
 444                         .max_uV                 = 1200000,
 445                         .valid_ops_mask         = REGULATOR_CHANGE_STATUS,
 446                         .boot_on                = 1,
 447                         .apply_uV               = 1,
 448                 },
 449                 .num_consumer_supplies  = ARRAY_SIZE(cpcap_vcsi_consumers),
 450                 .consumer_supplies      = cpcap_vcsi_consumers,
 451         },
 452         [CPCAP_VDAC] = {
 453                 .constraints = {
 454                         .min_uV                 = 1800000,
 455                         .max_uV                 = 1800000,
 456                         .valid_ops_mask         = REGULATOR_CHANGE_STATUS,
 457                         .apply_uV               = 1,
 458                 },
 459         },
 460         [CPCAP_VDIG] = {
 461                 .constraints = {
 462                         .min_uV                 = 1875000,
 463                         .max_uV                 = 1875000,
 464                         .valid_ops_mask         = 0,
 465                         .always_on              = 1,
 466                         .apply_uV               = 1,
 467                 },
 468                 .num_consumer_supplies  = ARRAY_SIZE(cpcap_vdig_consumers),
 469                 .consumer_supplies      = cpcap_vdig_consumers,
 470         },
 471         [CPCAP_VFUSE] = {
 472                 .constraints = {
 473                         .min_uV                 = 1500000,
 474                         .max_uV                 = 3150000,
 475                         .valid_ops_mask         = (REGULATOR_CHANGE_VOLTAGE |
 476                                                    REGULATOR_CHANGE_STATUS),
 477                 },
 478         },
 479         [CPCAP_VHVIO] = {
 480                 .constraints = {
 481                         .min_uV                 = 2775000,
 482                         .max_uV                 = 2775000,
 483                         .valid_ops_mask         = REGULATOR_CHANGE_STATUS,
 484                         .always_on              = 1,
 485                         .apply_uV               = 1,
 486                 },
 487                 .num_consumer_supplies  = ARRAY_SIZE(cpcap_vhvio_consumers),
 488                 .consumer_supplies      = cpcap_vhvio_consumers,
 489         },
 490         [CPCAP_VSDIO] = {
 491                 .constraints = {
 492                         .min_uV                 = 3000000,
 493                         .max_uV                 = 3000000,
 494                         .valid_ops_mask         = 0,
 495                         .always_on              = 1,
 496                         .apply_uV               = 1,
 497                 },
 498         },
 499         [CPCAP_VPLL] = {
 500                 .constraints = {
 501                         .min_uV                 = 1800000,
 502                         .max_uV                 = 1800000,
 503                         .valid_ops_mask         = 0,
 504                         .always_on              = 1,
 505                         .apply_uV               = 1,
 506                 },
 507         },
 508         [CPCAP_VRF1] = {
 509                 .constraints = {
 510                         .min_uV                 = 2500000,
 511                         .max_uV                 = 2775000,
 512                         .valid_ops_mask         = 0,
 513                 },
 514         },
 515         [CPCAP_VRF2] = {
 516                 .constraints = {
 517                         .min_uV                 = 2775000,
 518                         .max_uV                 = 2775000,
 519                         .valid_ops_mask         = 0,
 520                 },
 521         },
 522         [CPCAP_VRFREF] = {
 523                 .constraints = {
 524                         .min_uV                 = 2500000,
 525                         .max_uV                 = 2775000,
 526                         .valid_ops_mask         = 0,
 527                 },
 528         },
 529         [CPCAP_VWLAN1] = {
 530                 .constraints = {
 531                         .min_uV                 = 1800000,
 532                         .max_uV                 = 1900000,
 533                         .valid_ops_mask         = 0,
 534                         .always_on              = 1,
 535                 },
 536         },
 537         [CPCAP_VWLAN2] = {
 538                 .constraints = {
 539                         .min_uV                 = 3300000,
 540                         .max_uV                 = 3300000,
 541                         .valid_ops_mask         = 0,
 542                         .always_on              = 1,
 543                         .apply_uV               = 1,
 544                 },
 545         },
 546         [CPCAP_VSIM] = {
 547                 .constraints = {
 548                         .min_uV                 = 1800000,
 549                         .max_uV                 = 2900000,
 550                         .valid_ops_mask         = 0,
 551                 },
 552         },
 553         [CPCAP_VSIMCARD] = {
 554                 .constraints = {
 555                         .min_uV                 = 1800000,
 556                         .max_uV                 = 2900000,
 557                         .valid_ops_mask         = 0,
 558                 },
 559         },
 560         [CPCAP_VVIB] = {
 561                 .constraints = {
 562                         .min_uV                 = 1300000,
 563                         .max_uV                 = 3000000,
 564                         .valid_ops_mask         = 0,
 565                 },
 566         },
 567         [CPCAP_VUSB] = {
 568                 .constraints = {
 569                         .min_uV                 = 3300000,
 570                         .max_uV                 = 3300000,
 571                         .valid_ops_mask         = REGULATOR_CHANGE_STATUS,
 572                         .apply_uV               = 1,
 573                 },
 574                 .num_consumer_supplies  = ARRAY_SIZE(cpcap_vusb_consumers),
 575                 .consumer_supplies      = cpcap_vusb_consumers,
 576         },
 577         [CPCAP_VAUDIO] = {
 578                 .constraints = {
 579                         .min_uV                 = 2775000,
 580                         .max_uV                 = 2775000,
 581                         .valid_modes_mask       = (REGULATOR_MODE_NORMAL |
 582                                                    REGULATOR_MODE_STANDBY),
 583                         .valid_ops_mask         = REGULATOR_CHANGE_MODE,
 584                         .always_on              = 1,
 585                         .apply_uV               = 1,
 586                 },
 587                 .num_consumer_supplies  = ARRAY_SIZE(cpcap_vaudio_consumers),
 588                 .consumer_supplies      = cpcap_vaudio_consumers,
 589         },
 590 };
 591
 592 static struct cpcap_adc_ato stingray_cpcap_adc_ato = {
 593         .ato_in = 0x0480,
 594         .atox_in = 0,
 595         .adc_ps_factor_in = 0x0200,
 596         .atox_ps_factor_in = 0,
 597         .ato_out = 0,
 598         .atox_out = 0,
 599         .adc_ps_factor_out = 0,
 600         .atox_ps_factor_out = 0,
 601 };
 602
 603 static struct cpcap_platform_data stingray_cpcap_data = {
 604         .init = stingray_cpcap_spi_init,
 605         .init_len = ARRAY_SIZE(stingray_cpcap_spi_init),
 606         .regulator_mode_values = cpcap_regulator_mode_values,
 607         .regulator_off_mode_values = cpcap_regulator_off_mode_values,
 608         .regulator_init = cpcap_regulator,
 609         .adc_ato = &stingray_cpcap_adc_ato,
 610         .ac_changed = NULL,
 611         .batt_changed = NULL,
 612         .usb_changed = NULL,
 613         .hwcfg = {
 614                 (CPCAP_HWCFG0_SEC_STBY_SW3 |
 615                  CPCAP_HWCFG0_SEC_STBY_SW4 |
 616                  CPCAP_HWCFG0_SEC_STBY_VAUDIO |
 617                  CPCAP_HWCFG0_SEC_STBY_VCAM |
 618                  CPCAP_HWCFG0_SEC_STBY_VCSI |
 619                  CPCAP_HWCFG0_SEC_STBY_VHVIO |
 620                  CPCAP_HWCFG0_SEC_STBY_VPLL |
 621                  CPCAP_HWCFG0_SEC_STBY_VSDIO),
 622                 (CPCAP_HWCFG1_SEC_STBY_VWLAN1 |
 623                  CPCAP_HWCFG1_SEC_STBY_VWLAN2)}
 624 };
 625
 626 static struct spi_board_info stingray_spi_board_info[] __initdata = {
 627         {
 628                 .modalias = "cpcap",
 629                 .bus_num = 1,
 630                 .chip_select = 0,
 631                 .mode = SPI_MODE_0,
 632                 .max_speed_hz = 10000000,
 633                 .controller_data = &stingray_cpcap_data,
 634                 .irq = INT_EXTERNAL_PMU,
 635         },
 636 };
 637
 638 struct regulator_consumer_supply max8649_consumers[] = {
 639         REGULATOR_CONSUMER("vdd_cpu", NULL /* cpu */),
 640 };
 641
 642 struct regulator_init_data max8649_regulator_init_data[] = {
 643         {
 644                 .constraints = {
 645                         .min_uV                 = 770000,
 646                         .max_uV                 = 1100000,
 647                         .valid_ops_mask         = REGULATOR_CHANGE_VOLTAGE,
 648                         .always_on              = 1,
 649                 },
 650                 .num_consumer_supplies  = ARRAY_SIZE(max8649_consumers),
 651                 .consumer_supplies      = max8649_consumers,
 652         },
 653 };
 654
 655 struct max8649_platform_data stingray_max8649_pdata = {
 656         .regulator = max8649_regulator_init_data,
 657         .mode = 1,
 658         .extclk = 0,
 659         .ramp_timing = MAX8649_RAMP_32MV,
 660         .ramp_down = 0,
 661 };
 662
 663 static struct i2c_board_info __initdata stingray_i2c_bus4_power_info[] = {
 664         {
 665                 I2C_BOARD_INFO("max8649", 0x60),
 666                 .platform_data = &stingray_max8649_pdata,
 667         },
 668 };
 669
 670 static struct mdm_ctrl_platform_data mdm_ctrl_platform_data = {
 671         .gpios[MDM_CTRL_GPIO_AP_STATUS_0] = {
 672                 TEGRA_GPIO_PC1, MDM_GPIO_DIRECTION_OUT, 0, 0, "mdm_ap_status0"},
 673         .gpios[MDM_CTRL_GPIO_AP_STATUS_1] = {
 674                 TEGRA_GPIO_PC6, MDM_GPIO_DIRECTION_OUT, 0, 0, "mdm_ap_status1"},
 675         .gpios[MDM_CTRL_GPIO_AP_STATUS_2] = {
 676                 TEGRA_GPIO_PQ3, MDM_GPIO_DIRECTION_OUT, 0, 0, "mdm_ap_status2"},
 677         .gpios[MDM_CTRL_GPIO_BP_STATUS_0] = {
 678                 TEGRA_GPIO_PK3, MDM_GPIO_DIRECTION_IN, 0, 0, "mdm_bp_status0"},
 679         .gpios[MDM_CTRL_GPIO_BP_STATUS_1] = {
 680                 TEGRA_GPIO_PK4, MDM_GPIO_DIRECTION_IN, 0, 0, "mdm_bp_status1"},
 681         .gpios[MDM_CTRL_GPIO_BP_STATUS_2] = {
 682                 TEGRA_GPIO_PK2, MDM_GPIO_DIRECTION_IN, 0, 0, "mdm_bp_status2"},
 683         .gpios[MDM_CTRL_GPIO_BP_RESOUT]   = {
 684                 TEGRA_GPIO_PS4, MDM_GPIO_DIRECTION_IN, 0, 0, "mdm_bp_resout"},
 685         .gpios[MDM_CTRL_GPIO_BP_RESIN]    = {
 686                 TEGRA_GPIO_PZ1, MDM_GPIO_DIRECTION_OUT, 0, 0, "mdm_bp_resin"},
 687         .gpios[MDM_CTRL_GPIO_BP_PWRON]    = {
 688                 TEGRA_GPIO_PS6, MDM_GPIO_DIRECTION_OUT, 0, 0, "mdm_bp_pwr_on"},
 689         .cmd_gpios = {TEGRA_GPIO_PQ5, TEGRA_GPIO_PS5},
 690 };
 691
 692 static struct platform_device mdm_ctrl_platform_device = {
 693         .name = MDM_CTRL_MODULE_NAME,
 694         .id = -1,
 695         .dev = {
 696                 .platform_data = &mdm_ctrl_platform_data,
 697         },
 698 };
 699
 700 static struct wrigley_ctrl_platform_data wrigley_ctrl_pdata = {
 701         .gpio_disable = TEGRA_GPIO_PG0,
 702         .gpio_reset = TEGRA_GPIO_PI6,
 703         .gpio_force_flash = TEGRA_GPIO_PT5,
 704 };
 705
 706 static struct platform_device wrigley_ctrl_pdev = {
 707         .name = "wrigley",
 708         .id = -1,
 709         .dev = {
 710                 .platform_data = &wrigley_ctrl_pdata,
 711         },
 712 };
 713
 714 static void mdm_ctrl_register(void)
 715 {
 716         int i;
 717
 718         for (i = 0; i < MDM_CTRL_NUM_GPIOS; i++)
 719                 tegra_gpio_enable(mdm_ctrl_platform_data.gpios[i].number);
 720
 721         if (stingray_qbp_usb_hw_bypass_enabled()) {
 722                 /* The default AP status is "no bypass", so we must override it */
 723                 mdm_ctrl_platform_data.gpios[MDM_CTRL_GPIO_AP_STATUS_0]. \
 724                                 default_value = 1;
 725                 mdm_ctrl_platform_data.gpios[MDM_CTRL_GPIO_AP_STATUS_1]. \
 726                                 default_value = 0;
 727                 mdm_ctrl_platform_data.gpios[MDM_CTRL_GPIO_AP_STATUS_2]. \
 728                                 default_value = 0;
 729         }
 730
 731         platform_device_register(&mdm_ctrl_platform_device);
 732 }
 733
 734 static void wrigley_ctrl_register(void)
 735 {
 736         tegra_gpio_enable(wrigley_ctrl_pdata.gpio_reset);
 737         tegra_gpio_enable(wrigley_ctrl_pdata.gpio_disable);
 738         tegra_gpio_enable(wrigley_ctrl_pdata.gpio_force_flash);
 739         platform_device_register(&wrigley_ctrl_pdev);
 740 }
 741
 742 int __init stingray_power_init(void)
 743 {
 744         int i;
 745         unsigned long pmc_cntrl_0;
 746
 747         /* Enable CORE_PWR_REQ signal from T20. The signal must be enabled
 748          * before the CPCAP uC firmware is started. */
 749         pmc_cntrl_0 = readl(IO_ADDRESS(TEGRA_PMC_BASE));
 750         pmc_cntrl_0 |= 0x00000200;
 751         writel(pmc_cntrl_0, IO_ADDRESS(TEGRA_PMC_BASE));
 752
 753         if (stingray_revision() <= STINGRAY_REVISION_M1)
 754                 stingray_max8649_pdata.mode = 3;
 755
 756 #ifdef ENABLE_SOFT_RESET_DEBUGGING
 757         /* Only P3 and later hardware supports CPCAP resetting the T20. */
 758         if (stingray_revision() >= STINGRAY_REVISION_P3)
 759                 stingray_cpcap_data.hwcfg[1] |= CPCAP_HWCFG1_SOFT_RESET_HOST;
 760 #endif
 761
 762         tegra_gpio_enable(TEGRA_GPIO_PT2);
 763         gpio_request(TEGRA_GPIO_PT2, "usb_host_pwr_en");
 764         gpio_direction_output(TEGRA_GPIO_PT2, 0);
 765
 766         spi_register_board_info(stingray_spi_board_info,
 767                                 ARRAY_SIZE(stingray_spi_board_info));
 768
 769         for (i = 0; i < ARRAY_SIZE(cpcap_devices); i++)
 770                 cpcap_device_register(cpcap_devices[i]);
 771
 772         if (!stingray_qbp_usb_hw_bypass_enabled())
 773                 cpcap_device_register(&cpcap_whisper_device);
 774
 775         (void) cpcap_driver_register(&cpcap_validity_driver);
 776
 777         i2c_register_board_info(3, stingray_i2c_bus4_power_info,
 778                 ARRAY_SIZE(stingray_i2c_bus4_power_info));
 779
 780         if (stingray_hw_has_cdma()) {
 781                 mdm_ctrl_register();
 782                 wrigley_ctrl_register();
 783         }
 784
 785         return 0;
 786 }