arch/arm/mach-tegra/board-harmony.c

   1 /*
   2  * arch/arm/mach-tegra/board-harmony.c
   3  *
   4  * Copyright (C) 2010 Google, Inc.
   5  *
   6  * This software is licensed under the terms of the GNU General Public
   7  * License version 2, as published by the Free Software Foundation, and
   8  * may be copied, distributed, and modified under those terms.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  */
  16
  17 #include <linux/kernel.h>
  18 #include <linux/init.h>
  19 #include <linux/platform_device.h>
  20 #include <linux/serial_8250.h>
  21 #include <linux/clk.h>
  22 #include <linux/mtd/mtd.h>
  23 #include <linux/mtd/partitions.h>
  24 #include <linux/dma-mapping.h>
  25 #include <linux/pda_power.h>
  26 #include <linux/io.h>
  27 #include <linux/delay.h>
  28
  29 #include <asm/mach-types.h>
  30 #include <asm/mach/arch.h>
  31 #include <asm/mach/time.h>
  32 #include <asm/setup.h>
  33
  34 #include <mach/iomap.h>
  35 #include <mach/irqs.h>
  36 #include <mach/nand.h>
  37 #include <mach/clk.h>
  38
  39 #include "clock.h"
  40 #include "board.h"
  41 #include "board-harmony.h"
  42 #include "clock.h"
  43 #include "devices.h"
  44
  45 /* NVidia bootloader tags */
  46 #define ATAG_NVIDIA             0x41000801
  47
  48 #define ATAG_NVIDIA_RM                  0x1
  49 #define ATAG_NVIDIA_DISPLAY             0x2
  50 #define ATAG_NVIDIA_FRAMEBUFFER         0x3
  51 #define ATAG_NVIDIA_CHIPSHMOO           0x4
  52 #define ATAG_NVIDIA_CHIPSHMOOPHYS       0x5
  53 #define ATAG_NVIDIA_PRESERVED_MEM_0     0x10000
  54 #define ATAG_NVIDIA_PRESERVED_MEM_N     2
  55 #define ATAG_NVIDIA_FORCE_32            0x7fffffff
  56
  57 struct tag_tegra {
  58         __u32 bootarg_key;
  59         __u32 bootarg_len;
  60         char bootarg[1];
  61 };
  62
  63 static int __init parse_tag_nvidia(const struct tag *tag)
  64 {
  65
  66         return 0;
  67 }
  68 __tagtable(ATAG_NVIDIA, parse_tag_nvidia);
  69
  70 static struct tegra_nand_chip_parms nand_chip_parms[] = {
  71         /* Samsung K5E2G1GACM */
  72         [0] = {
  73                 .vendor_id   = 0xEC,
  74                 .device_id   = 0xAA,
  75                 .capacity    = 256,
  76                 .timing      = {
  77                         .trp            = 21,
  78                         .trh            = 15,
  79                         .twp            = 21,
  80                         .twh            = 15,
  81                         .tcs            = 31,
  82                         .twhr           = 60,
  83                         .tcr_tar_trr    = 20,
  84                         .twb            = 100,
  85                         .trp_resp       = 30,
  86                         .tadl           = 100,
  87                 },
  88         },
  89         /* Hynix H5PS1GB3EFR */
  90         [1] = {
  91                 .vendor_id   = 0xAD,
  92                 .device_id   = 0xDC,
  93                 .capacity    = 512,
  94                 .timing      = {
  95                         .trp            = 12,
  96                         .trh            = 10,
  97                         .twp            = 12,
  98                         .twh            = 10,
  99                         .tcs            = 20,
 100                         .twhr           = 80,
 101                         .tcr_tar_trr    = 20,
 102                         .twb            = 100,
 103                         .trp_resp       = 20,
 104                         .tadl           = 70,
 105                 },
 106         },
 107 };
 108
 109 struct tegra_nand_platform harmony_nand_data = {
 110         .max_chips      = 8,
 111         .chip_parms     = nand_chip_parms,
 112         .nr_chip_parms  = ARRAY_SIZE(nand_chip_parms),
 113 };
 114
 115 static struct resource resources_nand[] = {
 116         [0] = {
 117                 .start  = INT_NANDFLASH,
 118                 .end    = INT_NANDFLASH,
 119                 .flags  = IORESOURCE_IRQ,
 120         },
 121 };
 122
 123 struct platform_device tegra_nand_device = {
 124         .name           = "tegra_nand",
 125         .id             = -1,
 126         .num_resources  = ARRAY_SIZE(resources_nand),
 127         .resource       = resources_nand,
 128         .dev            = {
 129                 .platform_data = &harmony_nand_data,
 130         },
 131 };
 132
 133 static struct plat_serial8250_port debug_uart_platform_data[] = {
 134         {
 135                 .membase        = IO_ADDRESS(TEGRA_UARTD_BASE),
 136                 .mapbase        = TEGRA_UARTD_BASE,
 137                 .irq            = INT_UARTD,
 138                 .flags          = UPF_BOOT_AUTOCONF,
 139                 .iotype         = UPIO_MEM,
 140                 .regshift       = 2,
 141                 .uartclk        = 216000000,
 142         }, {
 143                 .flags          = 0
 144         }
 145 };
 146
 147 static struct platform_device debug_uart = {
 148         .name = "serial8250",
 149         .id = PLAT8250_DEV_PLATFORM,
 150         .dev = {
 151                 .platform_data = debug_uart_platform_data,
 152         },
 153 };
 154
 155 /* PDA power */
 156 static struct pda_power_pdata pda_power_pdata = {
 157 };
 158
 159 static struct platform_device pda_power_device = {
 160         .name   = "pda_power",
 161         .id     = -1,
 162         .dev    = {
 163                 .platform_data  = &pda_power_pdata,
 164         },
 165 };
 166
 167 static struct platform_device *harmony_devices[] __initdata = {
 168         &debug_uart,
 169         &pmu_device,
 170         &tegra_nand_device,
 171         &tegra_udc_device,
 172         &pda_power_device,
 173         &tegra_i2c_device1,
 174         &tegra_i2c_device2,
 175         &tegra_i2c_device3,
 176         &tegra_i2c_device4,
 177         &tegra_spi_device1,
 178         &tegra_spi_device2,
 179         &tegra_spi_device3,
 180         &tegra_spi_device4,
 181         &tegra_gart_device,
 182 };
 183
 184 static void __init tegra_harmony_fixup(struct machine_desc *desc,
 185         struct tag *tags, char **cmdline, struct meminfo *mi)
 186 {
 187         mi->nr_banks = 2;
 188         mi->bank[0].start = PHYS_OFFSET;
 189         mi->bank[0].size = 448 * SZ_1M;
 190         mi->bank[1].start = SZ_512M;
 191         mi->bank[1].size = SZ_512M;
 192 }
 193
 194 static __initdata struct tegra_clk_init_table harmony_clk_init_table[] = {
 195         /* name         parent          rate            enabled */
 196         { "uartd",      "pll_p",        216000000,      true },
 197         { NULL,         NULL,           0,              0},
 198 };
 199
 200 static void __init tegra_harmony_init(void)
 201 {
 202         tegra_common_init();
 203
 204         tegra_clk_init_from_table(harmony_clk_init_table);
 205
 206         harmony_pinmux_init();
 207
 208         platform_add_devices(harmony_devices, ARRAY_SIZE(harmony_devices));
 209
 210         harmony_panel_init();
 211         harmony_sdhci_init();
 212 }
 213
 214 MACHINE_START(HARMONY, "harmony")
 215         .boot_params  = 0x00000100,
 216         .phys_io        = IO_APB_PHYS,
 217         .io_pg_offst    = ((IO_APB_VIRT) >> 18) & 0xfffc,
 218         .fixup          = tegra_harmony_fixup,
 219         .init_irq       = tegra_init_irq,
 220         .init_machine   = tegra_harmony_init,
 221         .map_io         = tegra_map_common_io,
 222         .timer          = &tegra_timer,
 223 MACHINE_END