2 * arch/arm/mach-tegra/apbio.c
4 * Copyright (C) 2010 NVIDIA Corporation.
5 * Copyright (C) 2010 Google, Inc.
7 * This software is licensed under the terms of the GNU General Public
8 * License version 2, as published by the Free Software Foundation, and
9 * may be copied, distributed, and modified under those terms.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
18 #include <linux/kernel.h>
20 #include <linux/dma-mapping.h>
21 #include <linux/spinlock.h>
22 #include <linux/completion.h>
23 #include <linux/sched.h>
24 #include <linux/mutex.h>
27 #include <mach/iomap.h>
31 static DEFINE_MUTEX(tegra_apb_dma_lock);
33 #ifdef CONFIG_TEGRA_SYSTEM_DMA
34 static struct tegra_dma_channel *tegra_apb_dma;
35 static u32 *tegra_apb_bb;
36 static dma_addr_t tegra_apb_bb_phys;
37 static DECLARE_COMPLETION(tegra_apb_wait);
39 static void apb_dma_complete(struct tegra_dma_req *req)
41 complete(&tegra_apb_wait);
44 static inline u32 apb_readl(unsigned long offset)
46 struct tegra_dma_req req;
50 return readl(IO_TO_VIRT(offset));
52 mutex_lock(&tegra_apb_dma_lock);
53 req.complete = apb_dma_complete;
55 req.dest_addr = tegra_apb_bb_phys;
56 req.dest_bus_width = 32;
58 req.source_addr = offset;
59 req.source_bus_width = 32;
64 INIT_COMPLETION(tegra_apb_wait);
66 tegra_dma_enqueue_req(tegra_apb_dma, &req);
68 ret = wait_for_completion_timeout(&tegra_apb_wait,
69 msecs_to_jiffies(50));
71 if (WARN(ret == 0, "apb read dma timed out"))
72 *(u32 *)tegra_apb_bb = 0;
74 mutex_unlock(&tegra_apb_dma_lock);
75 return *((u32 *)tegra_apb_bb);
78 static inline void apb_writel(u32 value, unsigned long offset)
80 struct tegra_dma_req req;
84 writel(value, IO_TO_VIRT(offset));
88 mutex_lock(&tegra_apb_dma_lock);
89 *((u32 *)tegra_apb_bb) = value;
90 req.complete = apb_dma_complete;
92 req.dest_addr = offset;
94 req.dest_bus_width = 32;
95 req.source_addr = tegra_apb_bb_phys;
96 req.source_bus_width = 32;
101 INIT_COMPLETION(tegra_apb_wait);
103 tegra_dma_enqueue_req(tegra_apb_dma, &req);
105 ret = wait_for_completion_timeout(&tegra_apb_wait,
106 msecs_to_jiffies(50));
108 mutex_unlock(&tegra_apb_dma_lock);
111 static inline u32 apb_readl(unsigned long offset)
113 return readl(IO_TO_VIRT(offset));
116 static inline void apb_writel(u32 value, unsigned long offset)
118 writel(value, IO_TO_VIRT(offset));
122 u32 tegra_apb_readl(unsigned long offset)
124 return apb_readl(offset);
127 void tegra_apb_writel(u32 value, unsigned long offset)
129 apb_writel(value, offset);
132 void tegra_init_apb_dma(void)
134 #ifdef CONFIG_TEGRA_SYSTEM_DMA
135 tegra_apb_dma = tegra_dma_allocate_channel(TEGRA_DMA_MODE_ONESHOT |
137 if (!tegra_apb_dma) {
138 pr_err("%s: can not allocate dma channel\n", __func__);
142 tegra_apb_bb = dma_alloc_coherent(NULL, sizeof(u32),
143 &tegra_apb_bb_phys, GFP_KERNEL);
145 pr_err("%s: can not allocate bounce buffer\n", __func__);
146 tegra_dma_free_channel(tegra_apb_dma);
147 tegra_apb_dma = NULL;