2 * TCC8000 system timer setup
4 * (C) 2009 Hans J. Koch <hjk@linutronix.de>
6 * Licensed under the terms of the GPL version 2.
10 #include <linux/clk.h>
11 #include <linux/clockchips.h>
12 #include <linux/init.h>
13 #include <linux/interrupt.h>
15 #include <linux/irq.h>
16 #include <linux/kernel.h>
17 #include <linux/spinlock.h>
19 #include <asm/mach/time.h>
21 #include <mach/tcc8k-regs.h>
22 #include <mach/irqs.h>
26 static void __iomem *timer_base;
28 static cycle_t tcc_get_cycles(struct clocksource *cs)
30 return __raw_readl(timer_base + TC32MCNT_OFFS);
33 static struct clocksource clocksource_tcc = {
36 .read = tcc_get_cycles,
37 .mask = CLOCKSOURCE_MASK(32),
38 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
41 static int tcc_set_next_event(unsigned long evt,
42 struct clock_event_device *unused)
44 unsigned long reg = __raw_readl(timer_base + TC32MCNT_OFFS);
46 __raw_writel(reg + evt, timer_base + TC32CMP0_OFFS);
50 static void tcc_set_mode(enum clock_event_mode mode,
51 struct clock_event_device *evt)
53 unsigned long tc32irq;
56 case CLOCK_EVT_MODE_ONESHOT:
57 tc32irq = __raw_readl(timer_base + TC32IRQ_OFFS);
58 tc32irq |= TC32IRQ_IRQEN0;
59 __raw_writel(tc32irq, timer_base + TC32IRQ_OFFS);
61 case CLOCK_EVT_MODE_SHUTDOWN:
62 case CLOCK_EVT_MODE_UNUSED:
63 tc32irq = __raw_readl(timer_base + TC32IRQ_OFFS);
64 tc32irq &= ~TC32IRQ_IRQEN0;
65 __raw_writel(tc32irq, timer_base + TC32IRQ_OFFS);
67 case CLOCK_EVT_MODE_PERIODIC:
68 case CLOCK_EVT_MODE_RESUME:
73 static irqreturn_t tcc8k_timer_interrupt(int irq, void *dev_id)
75 struct clock_event_device *evt = dev_id;
77 /* Acknowledge TC32 interrupt by reading TC32IRQ */
78 __raw_readl(timer_base + TC32IRQ_OFFS);
80 evt->event_handler(evt);
85 static struct clock_event_device clockevent_tcc = {
87 .features = CLOCK_EVT_FEAT_ONESHOT,
89 .set_mode = tcc_set_mode,
90 .set_next_event = tcc_set_next_event,
94 static struct irqaction tcc8k_timer_irq = {
96 .flags = IRQF_DISABLED | IRQF_TIMER,
97 .handler = tcc8k_timer_interrupt,
98 .dev_id = &clockevent_tcc,
101 static int __init tcc_clockevent_init(struct clk *clock)
103 unsigned int c = clk_get_rate(clock);
105 clocksource_register_hz(&clocksource_tcc, c);
107 clockevent_tcc.mult = div_sc(c, NSEC_PER_SEC,
108 clockevent_tcc.shift);
109 clockevent_tcc.max_delta_ns =
110 clockevent_delta2ns(0xfffffffe, &clockevent_tcc);
111 clockevent_tcc.min_delta_ns =
112 clockevent_delta2ns(0xff, &clockevent_tcc);
114 clockevent_tcc.cpumask = cpumask_of(0);
116 clockevents_register_device(&clockevent_tcc);
121 void __init tcc8k_timer_init(struct clk *clock, void __iomem *base, int irq)
126 tcc8k_timer_irq.irq = irq;
131 /* Initialize 32-bit timer */
132 reg = __raw_readl(timer_base + TC32EN_OFFS);
133 reg &= ~TC32EN_ENABLE; /* Disable timer */
134 __raw_writel(reg, timer_base + TC32EN_OFFS);
135 /* Free running timer, counting from 0 to 0xffffffff */
136 __raw_writel(0, timer_base + TC32EN_OFFS);
137 __raw_writel(0, timer_base + TC32LDV_OFFS);
138 reg = __raw_readl(timer_base + TC32IRQ_OFFS);
139 reg |= TC32IRQ_IRQEN0; /* irq at match with CMP0 */
140 __raw_writel(reg, timer_base + TC32IRQ_OFFS);
142 __raw_writel(TC32EN_ENABLE, timer_base + TC32EN_OFFS);
144 tcc_clockevent_init(clock);
145 setup_irq(irq, &tcc8k_timer_irq);