arch/arm/mach-sunxi/sunxi.c

   1 /*
   2  * Device Tree support for Allwinner A1X SoCs
   3  *
   4  * Copyright (C) 2012 Maxime Ripard
   5  *
   6  * Maxime Ripard <maxime.ripard@free-electrons.com>
   7  *
   8  * This file is licensed under the terms of the GNU General Public
   9  * License version 2.  This program is licensed "as is" without any
  10  * warranty of any kind, whether express or implied.
  11  */
  12
  13 #include <linux/clocksource.h>
  14 #include <linux/delay.h>
  15 #include <linux/kernel.h>
  16 #include <linux/init.h>
  17 #include <linux/irqchip.h>
  18 #include <linux/of_address.h>
  19 #include <linux/of_irq.h>
  20 #include <linux/of_platform.h>
  21 #include <linux/io.h>
  22
  23 #include <linux/clk/sunxi.h>
  24
  25 #include <asm/mach/arch.h>
  26 #include <asm/mach/map.h>
  27 #include <asm/system_misc.h>
  28
  29 #include "sunxi.h"
  30
  31 #define SUN4I_WATCHDOG_CTRL_REG         0x00
  32 #define SUN4I_WATCHDOG_CTRL_RESTART             (1 << 0)
  33 #define SUN4I_WATCHDOG_MODE_REG         0x04
  34 #define SUN4I_WATCHDOG_MODE_ENABLE              (1 << 0)
  35 #define SUN4I_WATCHDOG_MODE_RESET_ENABLE        (1 << 1)
  36
  37 static void __iomem *wdt_base;
  38
  39 static void sun4i_restart(char mode, const char *cmd)
  40 {
  41         if (!wdt_base)
  42                 return;
  43
  44         /* Enable timer and set reset bit in the watchdog */
  45         writel(SUN4I_WATCHDOG_MODE_ENABLE | SUN4I_WATCHDOG_MODE_RESET_ENABLE,
  46                wdt_base + SUN4I_WATCHDOG_MODE_REG);
  47
  48         /*
  49          * Restart the watchdog. The default (and lowest) interval
  50          * value for the watchdog is 0.5s.
  51          */
  52         writel(SUN4I_WATCHDOG_CTRL_RESTART, wdt_base + SUN4I_WATCHDOG_CTRL_REG);
  53
  54         while (1) {
  55                 mdelay(5);
  56                 writel(SUN4I_WATCHDOG_MODE_ENABLE | SUN4I_WATCHDOG_MODE_RESET_ENABLE,
  57                        wdt_base + SUN4I_WATCHDOG_MODE_REG);
  58         }
  59 }
  60
  61 static struct of_device_id sunxi_restart_ids[] = {
  62         { .compatible = "allwinner,sun4i-wdt", .data = sun4i_restart },
  63         { /*sentinel*/ }
  64 };
  65
  66 static void sunxi_setup_restart(void)
  67 {
  68         const struct of_device_id *of_id;
  69         struct device_node *np;
  70
  71         np = of_find_matching_node(NULL, sunxi_restart_ids);
  72         if (WARN(!np, "unable to setup watchdog restart"))
  73                 return;
  74
  75         wdt_base = of_iomap(np, 0);
  76         WARN(!wdt_base, "failed to map watchdog base address");
  77
  78         of_id = of_match_node(sunxi_restart_ids, np);
  79         WARN(!of_id, "restart function not available");
  80
  81         arm_pm_restart = of_id->data;
  82 }
  83
  84 static struct map_desc sunxi_io_desc[] __initdata = {
  85         {
  86                 .virtual        = (unsigned long) SUNXI_REGS_VIRT_BASE,
  87                 .pfn            = __phys_to_pfn(SUNXI_REGS_PHYS_BASE),
  88                 .length         = SUNXI_REGS_SIZE,
  89                 .type           = MT_DEVICE,
  90         },
  91 };
  92
  93 void __init sunxi_map_io(void)
  94 {
  95         iotable_init(sunxi_io_desc, ARRAY_SIZE(sunxi_io_desc));
  96 }
  97
  98 static void __init sunxi_timer_init(void)
  99 {
 100         sunxi_init_clocks();
 101         clocksource_of_init();
 102 }
 103
 104 static void __init sunxi_dt_init(void)
 105 {
 106         sunxi_setup_restart();
 107
 108         of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
 109 }
 110
 111 static const char * const sunxi_board_dt_compat[] = {
 112         "allwinner,sun4i-a10",
 113         "allwinner,sun5i-a13",
 114         NULL,
 115 };
 116
 117 DT_MACHINE_START(SUNXI_DT, "Allwinner A1X (Device Tree)")
 118         .init_machine   = sunxi_dt_init,
 119         .map_io         = sunxi_map_io,
 120         .init_irq       = irqchip_init,
 121         .init_time      = sunxi_timer_init,
 122         .dt_compat      = sunxi_board_dt_compat,
 123 MACHINE_END