arch/arm/mach-spear3xx/spear3xx.c

   1 /*
   2  * arch/arm/mach-spear3xx/spear3xx.c
   3  *
   4  * SPEAr3XX machines common source file
   5  *
   6  * Copyright (C) 2009-2012 ST Microelectronics
   7  * Viresh Kumar <viresh.linux@gmail.com>
   8  *
   9  * This file is licensed under the terms of the GNU General Public
  10  * License version 2. This program is licensed "as is" without any
  11  * warranty of any kind, whether express or implied.
  12  */
  13
  14 #define pr_fmt(fmt) "SPEAr3xx: " fmt
  15
  16 #include <linux/amba/pl022.h>
  17 #include <linux/amba/pl08x.h>
  18 #include <linux/io.h>
  19 #include <plat/pl080.h>
  20 #include <mach/generic.h>
  21 #include <mach/spear.h>
  22
  23 /* ssp device registration */
  24 struct pl022_ssp_controller pl022_plat_data = {
  25         .bus_id = 0,
  26         .enable_dma = 1,
  27         .dma_filter = pl08x_filter_id,
  28         .dma_tx_param = "ssp0_tx",
  29         .dma_rx_param = "ssp0_rx",
  30         /*
  31          * This is number of spi devices that can be connected to spi. There are
  32          * two type of chipselects on which slave devices can work. One is chip
  33          * select provided by spi masters other is controlled through external
  34          * gpio's. We can't use chipselect provided from spi master (because as
  35          * soon as FIFO becomes empty, CS is disabled and transfer ends). So
  36          * this number now depends on number of gpios available for spi. each
  37          * slave on each master requires a separate gpio pin.
  38          */
  39         .num_chipselect = 2,
  40 };
  41
  42 /* dmac device registration */
  43 struct pl08x_platform_data pl080_plat_data = {
  44         .memcpy_channel = {
  45                 .bus_id = "memcpy",
  46                 .cctl_memcpy =
  47                         (PL080_BSIZE_16 << PL080_CONTROL_SB_SIZE_SHIFT | \
  48                         PL080_BSIZE_16 << PL080_CONTROL_DB_SIZE_SHIFT | \
  49                         PL080_WIDTH_32BIT << PL080_CONTROL_SWIDTH_SHIFT | \
  50                         PL080_WIDTH_32BIT << PL080_CONTROL_DWIDTH_SHIFT | \
  51                         PL080_CONTROL_PROT_BUFF | PL080_CONTROL_PROT_CACHE | \
  52                         PL080_CONTROL_PROT_SYS),
  53         },
  54         .lli_buses = PL08X_AHB1,
  55         .mem_buses = PL08X_AHB1,
  56         .get_signal = pl080_get_signal,
  57         .put_signal = pl080_put_signal,
  58 };
  59
  60 /*
  61  * Following will create 16MB static virtual/physical mappings
  62  * PHYSICAL             VIRTUAL
  63  * 0xD0000000           0xFD000000
  64  * 0xFC000000           0xFC000000
  65  */
  66 struct map_desc spear3xx_io_desc[] __initdata = {
  67         {
  68                 .virtual        = VA_SPEAR3XX_ICM1_2_BASE,
  69                 .pfn            = __phys_to_pfn(SPEAR3XX_ICM1_2_BASE),
  70                 .length         = SZ_16M,
  71                 .type           = MT_DEVICE
  72         }, {
  73                 .virtual        = VA_SPEAR3XX_ICM3_SMI_CTRL_BASE,
  74                 .pfn            = __phys_to_pfn(SPEAR3XX_ICM3_SMI_CTRL_BASE),
  75                 .length         = SZ_16M,
  76                 .type           = MT_DEVICE
  77         },
  78 };
  79
  80 /* This will create static memory mapping for selected devices */
  81 void __init spear3xx_map_io(void)
  82 {
  83         iotable_init(spear3xx_io_desc, ARRAY_SIZE(spear3xx_io_desc));
  84 }
  85
  86 void __init spear3xx_timer_init(void)
  87 {
  88         char pclk_name[] = "pll3_clk";
  89         struct clk *gpt_clk, *pclk;
  90
  91         spear3xx_clk_init();
  92
  93         /* get the system timer clock */
  94         gpt_clk = clk_get_sys("gpt0", NULL);
  95         if (IS_ERR(gpt_clk)) {
  96                 pr_err("%s:couldn't get clk for gpt\n", __func__);
  97                 BUG();
  98         }
  99
 100         /* get the suitable parent clock for timer*/
 101         pclk = clk_get(NULL, pclk_name);
 102         if (IS_ERR(pclk)) {
 103                 pr_err("%s:couldn't get %s as parent for gpt\n",
 104                                 __func__, pclk_name);
 105                 BUG();
 106         }
 107
 108         clk_set_parent(gpt_clk, pclk);
 109         clk_put(gpt_clk);
 110         clk_put(pclk);
 111
 112         spear_setup_of_timer();
 113 }