2 * SMP support for R-Mobile / SH-Mobile - r8a7779 portion
4 * Copyright (C) 2011 Renesas Solutions Corp.
5 * Copyright (C) 2011 Magnus Damm
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 #include <linux/kernel.h>
21 #include <linux/init.h>
22 #include <linux/smp.h>
23 #include <linux/spinlock.h>
25 #include <linux/delay.h>
26 #include <mach/common.h>
27 #include <mach/r8a7779.h>
28 #include <asm/smp_plat.h>
29 #include <asm/smp_scu.h>
30 #include <asm/smp_twd.h>
31 #include <asm/hardware/gic.h>
33 #define AVECR 0xfe700040
35 static struct r8a7779_pm_ch r8a7779_ch_cpu1 = {
36 .chan_offs = 0x40, /* PWRSR0 .. PWRER0 */
37 .chan_bit = 1, /* ARM1 */
38 .isr_bit = 1, /* ARM1 */
41 static struct r8a7779_pm_ch r8a7779_ch_cpu2 = {
42 .chan_offs = 0x40, /* PWRSR0 .. PWRER0 */
43 .chan_bit = 2, /* ARM2 */
44 .isr_bit = 2, /* ARM2 */
47 static struct r8a7779_pm_ch r8a7779_ch_cpu3 = {
48 .chan_offs = 0x40, /* PWRSR0 .. PWRER0 */
49 .chan_bit = 3, /* ARM3 */
50 .isr_bit = 3, /* ARM3 */
53 static struct r8a7779_pm_ch *r8a7779_ch_cpu[4] = {
54 [1] = &r8a7779_ch_cpu1,
55 [2] = &r8a7779_ch_cpu2,
56 [3] = &r8a7779_ch_cpu3,
59 static void __iomem *scu_base_addr(void)
61 return (void __iomem *)0xf0000000;
64 static DEFINE_SPINLOCK(scu_lock);
65 static unsigned long tmp;
67 static DEFINE_TWD_LOCAL_TIMER(twd_local_timer, 0xf0000600, 29);
69 static void modify_scu_cpu_psr(unsigned long set, unsigned long clr)
71 void __iomem *scu_base = scu_base_addr();
74 tmp = __raw_readl(scu_base + 8);
77 spin_unlock(&scu_lock);
79 /* disable cache coherency after releasing the lock */
80 __raw_writel(tmp, scu_base + 8);
83 unsigned int __init r8a7779_get_core_count(void)
85 void __iomem *scu_base = scu_base_addr();
87 shmobile_twd_init(&twd_local_timer);
88 return scu_get_core_count(scu_base);
91 int r8a7779_platform_cpu_kill(unsigned int cpu)
93 struct r8a7779_pm_ch *ch = NULL;
96 cpu = cpu_logical_map(cpu);
98 /* disable cache coherency */
99 modify_scu_cpu_psr(3 << (cpu * 8), 0);
101 if (cpu < ARRAY_SIZE(r8a7779_ch_cpu))
102 ch = r8a7779_ch_cpu[cpu];
105 ret = r8a7779_sysc_power_down(ch);
107 return ret ? ret : 1;
110 void __cpuinit r8a7779_secondary_init(unsigned int cpu)
112 gic_secondary_init(0);
115 int __cpuinit r8a7779_boot_secondary(unsigned int cpu)
117 struct r8a7779_pm_ch *ch = NULL;
120 cpu = cpu_logical_map(cpu);
122 /* enable cache coherency */
123 modify_scu_cpu_psr(0, 3 << (cpu * 8));
125 if (cpu < ARRAY_SIZE(r8a7779_ch_cpu))
126 ch = r8a7779_ch_cpu[cpu];
129 ret = r8a7779_sysc_power_up(ch);
134 void __init r8a7779_smp_prepare_cpus(void)
136 int cpu = cpu_logical_map(0);
138 scu_enable(scu_base_addr());
140 /* Map the reset vector (in headsmp.S) */
141 __raw_writel(__pa(shmobile_secondary_vector), __io(AVECR));
143 /* enable cache coherency on CPU0 */
144 modify_scu_cpu_psr(0, 3 << (cpu * 8));
148 /* power off secondary CPUs */
149 r8a7779_platform_cpu_kill(1);
150 r8a7779_platform_cpu_kill(2);
151 r8a7779_platform_cpu_kill(3);