2 * sh73a0 processor support
4 * Copyright (C) 2010 Takashi Yoshii
5 * Copyright (C) 2010 Magnus Damm
6 * Copyright (C) 2008 Yoshihiro Shimoda
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; version 2 of the License.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 #include <linux/kernel.h>
18 #include <linux/init.h>
19 #include <linux/interrupt.h>
20 #include <linux/irq.h>
21 #include <linux/platform_device.h>
22 #include <linux/of_platform.h>
23 #include <linux/delay.h>
24 #include <linux/input.h>
25 #include <linux/i2c/i2c-sh_mobile.h>
27 #include <linux/serial_sci.h>
28 #include <linux/sh_dma.h>
29 #include <linux/sh_timer.h>
30 #include <linux/platform_data/sh_ipmmu.h>
31 #include <linux/platform_data/irq-renesas-intc-irqpin.h>
33 #include <asm/mach-types.h>
34 #include <asm/mach/map.h>
35 #include <asm/mach/arch.h>
36 #include <asm/mach/time.h>
39 #include "dma-register.h"
44 static struct map_desc sh73a0_io_desc[] __initdata = {
45 /* create a 1:1 identity mapping for 0xe6xxxxxx
46 * used by CPGA, INTC and PFC.
49 .virtual = 0xe6000000,
50 .pfn = __phys_to_pfn(0xe6000000),
52 .type = MT_DEVICE_NONSHARED
56 void __init sh73a0_map_io(void)
59 iotable_init(sh73a0_io_desc, ARRAY_SIZE(sh73a0_io_desc));
63 static struct resource pfc_resources[] __initdata = {
64 DEFINE_RES_MEM(0xe6050000, 0x8000),
65 DEFINE_RES_MEM(0xe605801c, 0x000c),
68 void __init sh73a0_pinmux_init(void)
70 platform_device_register_simple("pfc-sh73a0", -1, pfc_resources,
71 ARRAY_SIZE(pfc_resources));
75 #define SH73A0_SCIF(scif_type, index, baseaddr, irq) \
76 static struct plat_sci_port scif##index##_platform_data = { \
78 .flags = UPF_BOOT_AUTOCONF, \
79 .scscr = SCSCR_RE | SCSCR_TE, \
82 static struct resource scif##index##_resources[] = { \
83 DEFINE_RES_MEM(baseaddr, 0x100), \
84 DEFINE_RES_IRQ(irq), \
87 static struct platform_device scif##index##_device = { \
90 .resource = scif##index##_resources, \
91 .num_resources = ARRAY_SIZE(scif##index##_resources), \
93 .platform_data = &scif##index##_platform_data, \
97 SH73A0_SCIF(PORT_SCIFA, 0, 0xe6c40000, gic_spi(72));
98 SH73A0_SCIF(PORT_SCIFA, 1, 0xe6c50000, gic_spi(73));
99 SH73A0_SCIF(PORT_SCIFA, 2, 0xe6c60000, gic_spi(74));
100 SH73A0_SCIF(PORT_SCIFA, 3, 0xe6c70000, gic_spi(75));
101 SH73A0_SCIF(PORT_SCIFA, 4, 0xe6c80000, gic_spi(78));
102 SH73A0_SCIF(PORT_SCIFA, 5, 0xe6cb0000, gic_spi(79));
103 SH73A0_SCIF(PORT_SCIFA, 6, 0xe6cc0000, gic_spi(156));
104 SH73A0_SCIF(PORT_SCIFA, 7, 0xe6cd0000, gic_spi(143));
105 SH73A0_SCIF(PORT_SCIFB, 8, 0xe6c30000, gic_spi(80));
107 static struct sh_timer_config cmt1_platform_data = {
108 .channels_mask = 0x3f,
111 static struct resource cmt1_resources[] = {
112 DEFINE_RES_MEM(0xe6138000, 0x200),
113 DEFINE_RES_IRQ(gic_spi(65)),
116 static struct platform_device cmt1_device = {
120 .platform_data = &cmt1_platform_data,
122 .resource = cmt1_resources,
123 .num_resources = ARRAY_SIZE(cmt1_resources),
127 static struct sh_timer_config tmu0_platform_data = {
131 static struct resource tmu0_resources[] = {
132 DEFINE_RES_MEM(0xfff60000, 0x2c),
133 DEFINE_RES_IRQ(intcs_evt2irq(0xe80)),
134 DEFINE_RES_IRQ(intcs_evt2irq(0xea0)),
135 DEFINE_RES_IRQ(intcs_evt2irq(0xec0)),
138 static struct platform_device tmu0_device = {
142 .platform_data = &tmu0_platform_data,
144 .resource = tmu0_resources,
145 .num_resources = ARRAY_SIZE(tmu0_resources),
148 static struct resource i2c0_resources[] = {
149 [0] = DEFINE_RES_MEM(0xe6820000, 0x426),
151 .start = gic_spi(167),
153 .flags = IORESOURCE_IRQ,
157 static struct resource i2c1_resources[] = {
158 [0] = DEFINE_RES_MEM(0xe6822000, 0x426),
160 .start = gic_spi(51),
162 .flags = IORESOURCE_IRQ,
166 static struct resource i2c2_resources[] = {
167 [0] = DEFINE_RES_MEM(0xe6824000, 0x426),
169 .start = gic_spi(171),
171 .flags = IORESOURCE_IRQ,
175 static struct resource i2c3_resources[] = {
176 [0] = DEFINE_RES_MEM(0xe6826000, 0x426),
178 .start = gic_spi(183),
180 .flags = IORESOURCE_IRQ,
184 static struct resource i2c4_resources[] = {
185 [0] = DEFINE_RES_MEM(0xe6828000, 0x426),
187 .start = gic_spi(187),
189 .flags = IORESOURCE_IRQ,
193 static struct i2c_sh_mobile_platform_data i2c_platform_data = {
197 static struct platform_device i2c0_device = {
198 .name = "i2c-sh_mobile",
200 .resource = i2c0_resources,
201 .num_resources = ARRAY_SIZE(i2c0_resources),
203 .platform_data = &i2c_platform_data,
207 static struct platform_device i2c1_device = {
208 .name = "i2c-sh_mobile",
210 .resource = i2c1_resources,
211 .num_resources = ARRAY_SIZE(i2c1_resources),
213 .platform_data = &i2c_platform_data,
217 static struct platform_device i2c2_device = {
218 .name = "i2c-sh_mobile",
220 .resource = i2c2_resources,
221 .num_resources = ARRAY_SIZE(i2c2_resources),
223 .platform_data = &i2c_platform_data,
227 static struct platform_device i2c3_device = {
228 .name = "i2c-sh_mobile",
230 .resource = i2c3_resources,
231 .num_resources = ARRAY_SIZE(i2c3_resources),
233 .platform_data = &i2c_platform_data,
237 static struct platform_device i2c4_device = {
238 .name = "i2c-sh_mobile",
240 .resource = i2c4_resources,
241 .num_resources = ARRAY_SIZE(i2c4_resources),
243 .platform_data = &i2c_platform_data,
247 static const struct sh_dmae_slave_config sh73a0_dmae_slaves[] = {
249 .slave_id = SHDMA_SLAVE_SCIF0_TX,
251 .chcr = CHCR_TX(XMIT_SZ_8BIT),
254 .slave_id = SHDMA_SLAVE_SCIF0_RX,
256 .chcr = CHCR_RX(XMIT_SZ_8BIT),
259 .slave_id = SHDMA_SLAVE_SCIF1_TX,
261 .chcr = CHCR_TX(XMIT_SZ_8BIT),
264 .slave_id = SHDMA_SLAVE_SCIF1_RX,
266 .chcr = CHCR_RX(XMIT_SZ_8BIT),
269 .slave_id = SHDMA_SLAVE_SCIF2_TX,
271 .chcr = CHCR_TX(XMIT_SZ_8BIT),
274 .slave_id = SHDMA_SLAVE_SCIF2_RX,
276 .chcr = CHCR_RX(XMIT_SZ_8BIT),
279 .slave_id = SHDMA_SLAVE_SCIF3_TX,
281 .chcr = CHCR_TX(XMIT_SZ_8BIT),
284 .slave_id = SHDMA_SLAVE_SCIF3_RX,
286 .chcr = CHCR_RX(XMIT_SZ_8BIT),
289 .slave_id = SHDMA_SLAVE_SCIF4_TX,
291 .chcr = CHCR_TX(XMIT_SZ_8BIT),
294 .slave_id = SHDMA_SLAVE_SCIF4_RX,
296 .chcr = CHCR_RX(XMIT_SZ_8BIT),
299 .slave_id = SHDMA_SLAVE_SCIF5_TX,
301 .chcr = CHCR_TX(XMIT_SZ_8BIT),
304 .slave_id = SHDMA_SLAVE_SCIF5_RX,
306 .chcr = CHCR_RX(XMIT_SZ_8BIT),
309 .slave_id = SHDMA_SLAVE_SCIF6_TX,
311 .chcr = CHCR_TX(XMIT_SZ_8BIT),
314 .slave_id = SHDMA_SLAVE_SCIF6_RX,
316 .chcr = CHCR_RX(XMIT_SZ_8BIT),
319 .slave_id = SHDMA_SLAVE_SCIF7_TX,
321 .chcr = CHCR_TX(XMIT_SZ_8BIT),
324 .slave_id = SHDMA_SLAVE_SCIF7_RX,
326 .chcr = CHCR_RX(XMIT_SZ_8BIT),
329 .slave_id = SHDMA_SLAVE_SCIF8_TX,
331 .chcr = CHCR_TX(XMIT_SZ_8BIT),
334 .slave_id = SHDMA_SLAVE_SCIF8_RX,
336 .chcr = CHCR_RX(XMIT_SZ_8BIT),
339 .slave_id = SHDMA_SLAVE_SDHI0_TX,
341 .chcr = CHCR_TX(XMIT_SZ_16BIT),
344 .slave_id = SHDMA_SLAVE_SDHI0_RX,
346 .chcr = CHCR_RX(XMIT_SZ_16BIT),
349 .slave_id = SHDMA_SLAVE_SDHI1_TX,
351 .chcr = CHCR_TX(XMIT_SZ_16BIT),
354 .slave_id = SHDMA_SLAVE_SDHI1_RX,
356 .chcr = CHCR_RX(XMIT_SZ_16BIT),
359 .slave_id = SHDMA_SLAVE_SDHI2_TX,
361 .chcr = CHCR_TX(XMIT_SZ_16BIT),
364 .slave_id = SHDMA_SLAVE_SDHI2_RX,
366 .chcr = CHCR_RX(XMIT_SZ_16BIT),
369 .slave_id = SHDMA_SLAVE_MMCIF_TX,
371 .chcr = CHCR_TX(XMIT_SZ_32BIT),
374 .slave_id = SHDMA_SLAVE_MMCIF_RX,
376 .chcr = CHCR_RX(XMIT_SZ_32BIT),
381 #define DMAE_CHANNEL(_offset) \
383 .offset = _offset - 0x20, \
384 .dmars = _offset - 0x20 + 0x40, \
387 static const struct sh_dmae_channel sh73a0_dmae_channels[] = {
388 DMAE_CHANNEL(0x8000),
389 DMAE_CHANNEL(0x8080),
390 DMAE_CHANNEL(0x8100),
391 DMAE_CHANNEL(0x8180),
392 DMAE_CHANNEL(0x8200),
393 DMAE_CHANNEL(0x8280),
394 DMAE_CHANNEL(0x8300),
395 DMAE_CHANNEL(0x8380),
396 DMAE_CHANNEL(0x8400),
397 DMAE_CHANNEL(0x8480),
398 DMAE_CHANNEL(0x8500),
399 DMAE_CHANNEL(0x8580),
400 DMAE_CHANNEL(0x8600),
401 DMAE_CHANNEL(0x8680),
402 DMAE_CHANNEL(0x8700),
403 DMAE_CHANNEL(0x8780),
404 DMAE_CHANNEL(0x8800),
405 DMAE_CHANNEL(0x8880),
406 DMAE_CHANNEL(0x8900),
407 DMAE_CHANNEL(0x8980),
410 static struct sh_dmae_pdata sh73a0_dmae_platform_data = {
411 .slave = sh73a0_dmae_slaves,
412 .slave_num = ARRAY_SIZE(sh73a0_dmae_slaves),
413 .channel = sh73a0_dmae_channels,
414 .channel_num = ARRAY_SIZE(sh73a0_dmae_channels),
415 .ts_low_shift = TS_LOW_SHIFT,
416 .ts_low_mask = TS_LOW_BIT << TS_LOW_SHIFT,
417 .ts_high_shift = TS_HI_SHIFT,
418 .ts_high_mask = TS_HI_BIT << TS_HI_SHIFT,
419 .ts_shift = dma_ts_shift,
420 .ts_shift_num = ARRAY_SIZE(dma_ts_shift),
421 .dmaor_init = DMAOR_DME,
424 static struct resource sh73a0_dmae_resources[] = {
425 DEFINE_RES_MEM(0xfe000020, 0x89e0),
428 .start = gic_spi(129),
430 .flags = IORESOURCE_IRQ,
433 /* IRQ for channels 0-19 */
434 .start = gic_spi(109),
436 .flags = IORESOURCE_IRQ,
440 static struct platform_device dma0_device = {
441 .name = "sh-dma-engine",
443 .resource = sh73a0_dmae_resources,
444 .num_resources = ARRAY_SIZE(sh73a0_dmae_resources),
446 .platform_data = &sh73a0_dmae_platform_data,
451 static const struct sh_dmae_slave_config sh73a0_mpdma_slaves[] = {
453 .slave_id = SHDMA_SLAVE_FSI2A_RX,
455 .chcr = CHCR_RX(XMIT_SZ_32BIT),
456 .mid_rid = 0xd6, /* CHECK ME */
458 .slave_id = SHDMA_SLAVE_FSI2A_TX,
460 .chcr = CHCR_TX(XMIT_SZ_32BIT),
461 .mid_rid = 0xd5, /* CHECK ME */
463 .slave_id = SHDMA_SLAVE_FSI2C_RX,
465 .chcr = CHCR_RX(XMIT_SZ_32BIT),
466 .mid_rid = 0xda, /* CHECK ME */
468 .slave_id = SHDMA_SLAVE_FSI2C_TX,
470 .chcr = CHCR_TX(XMIT_SZ_32BIT),
471 .mid_rid = 0xd9, /* CHECK ME */
473 .slave_id = SHDMA_SLAVE_FSI2B_RX,
475 .chcr = CHCR_RX(XMIT_SZ_32BIT),
476 .mid_rid = 0x8e, /* CHECK ME */
478 .slave_id = SHDMA_SLAVE_FSI2B_TX,
480 .chcr = CHCR_RX(XMIT_SZ_32BIT),
481 .mid_rid = 0x8d, /* CHECK ME */
483 .slave_id = SHDMA_SLAVE_FSI2D_RX,
485 .chcr = CHCR_RX(XMIT_SZ_32BIT),
486 .mid_rid = 0x9a, /* CHECK ME */
490 #define MPDMA_CHANNEL(a, b, c) \
495 .chclr_offset = (0x220 - 0x20) + a \
498 static const struct sh_dmae_channel sh73a0_mpdma_channels[] = {
499 MPDMA_CHANNEL(0x00, 0, 0),
500 MPDMA_CHANNEL(0x10, 0, 8),
501 MPDMA_CHANNEL(0x20, 4, 0),
502 MPDMA_CHANNEL(0x30, 4, 8),
503 MPDMA_CHANNEL(0x50, 8, 0),
504 MPDMA_CHANNEL(0x70, 8, 8),
507 static struct sh_dmae_pdata sh73a0_mpdma_platform_data = {
508 .slave = sh73a0_mpdma_slaves,
509 .slave_num = ARRAY_SIZE(sh73a0_mpdma_slaves),
510 .channel = sh73a0_mpdma_channels,
511 .channel_num = ARRAY_SIZE(sh73a0_mpdma_channels),
512 .ts_low_shift = TS_LOW_SHIFT,
513 .ts_low_mask = TS_LOW_BIT << TS_LOW_SHIFT,
514 .ts_high_shift = TS_HI_SHIFT,
515 .ts_high_mask = TS_HI_BIT << TS_HI_SHIFT,
516 .ts_shift = dma_ts_shift,
517 .ts_shift_num = ARRAY_SIZE(dma_ts_shift),
518 .dmaor_init = DMAOR_DME,
522 /* Resource order important! */
523 static struct resource sh73a0_mpdma_resources[] = {
524 /* Channel registers and DMAOR */
525 DEFINE_RES_MEM(0xec618020, 0x270),
527 DEFINE_RES_MEM(0xec619000, 0xc),
530 .start = gic_spi(181),
532 .flags = IORESOURCE_IRQ,
535 /* IRQ for channels 0-5 */
536 .start = gic_spi(175),
538 .flags = IORESOURCE_IRQ,
542 static struct platform_device mpdma0_device = {
543 .name = "sh-dma-engine",
545 .resource = sh73a0_mpdma_resources,
546 .num_resources = ARRAY_SIZE(sh73a0_mpdma_resources),
548 .platform_data = &sh73a0_mpdma_platform_data,
552 static struct resource pmu_resources[] = {
554 .start = gic_spi(55),
556 .flags = IORESOURCE_IRQ,
559 .start = gic_spi(56),
561 .flags = IORESOURCE_IRQ,
565 static struct platform_device pmu_device = {
568 .num_resources = ARRAY_SIZE(pmu_resources),
569 .resource = pmu_resources,
572 /* an IPMMU module for ICB */
573 static struct resource ipmmu_resources[] = {
574 DEFINE_RES_MEM(0xfe951000, 0x100),
577 static const char * const ipmmu_dev_names[] = {
578 "sh_mobile_lcdc_fb.0",
581 static struct shmobile_ipmmu_platform_data ipmmu_platform_data = {
582 .dev_names = ipmmu_dev_names,
583 .num_dev_names = ARRAY_SIZE(ipmmu_dev_names),
586 static struct platform_device ipmmu_device = {
590 .platform_data = &ipmmu_platform_data,
592 .resource = ipmmu_resources,
593 .num_resources = ARRAY_SIZE(ipmmu_resources),
596 static struct renesas_intc_irqpin_config irqpin0_platform_data = {
597 .irq_base = irq_pin(0), /* IRQ0 -> IRQ7 */
600 static struct resource irqpin0_resources[] = {
601 DEFINE_RES_MEM(0xe6900000, 4), /* ICR1A */
602 DEFINE_RES_MEM(0xe6900010, 4), /* INTPRI00A */
603 DEFINE_RES_MEM(0xe6900020, 1), /* INTREQ00A */
604 DEFINE_RES_MEM(0xe6900040, 1), /* INTMSK00A */
605 DEFINE_RES_MEM(0xe6900060, 1), /* INTMSKCLR00A */
606 DEFINE_RES_IRQ(gic_spi(1)), /* IRQ0 */
607 DEFINE_RES_IRQ(gic_spi(2)), /* IRQ1 */
608 DEFINE_RES_IRQ(gic_spi(3)), /* IRQ2 */
609 DEFINE_RES_IRQ(gic_spi(4)), /* IRQ3 */
610 DEFINE_RES_IRQ(gic_spi(5)), /* IRQ4 */
611 DEFINE_RES_IRQ(gic_spi(6)), /* IRQ5 */
612 DEFINE_RES_IRQ(gic_spi(7)), /* IRQ6 */
613 DEFINE_RES_IRQ(gic_spi(8)), /* IRQ7 */
616 static struct platform_device irqpin0_device = {
617 .name = "renesas_intc_irqpin",
619 .resource = irqpin0_resources,
620 .num_resources = ARRAY_SIZE(irqpin0_resources),
622 .platform_data = &irqpin0_platform_data,
626 static struct renesas_intc_irqpin_config irqpin1_platform_data = {
627 .irq_base = irq_pin(8), /* IRQ8 -> IRQ15 */
628 .control_parent = true, /* Disable spurious IRQ10 */
631 static struct resource irqpin1_resources[] = {
632 DEFINE_RES_MEM(0xe6900004, 4), /* ICR2A */
633 DEFINE_RES_MEM(0xe6900014, 4), /* INTPRI10A */
634 DEFINE_RES_MEM(0xe6900024, 1), /* INTREQ10A */
635 DEFINE_RES_MEM(0xe6900044, 1), /* INTMSK10A */
636 DEFINE_RES_MEM(0xe6900064, 1), /* INTMSKCLR10A */
637 DEFINE_RES_IRQ(gic_spi(9)), /* IRQ8 */
638 DEFINE_RES_IRQ(gic_spi(10)), /* IRQ9 */
639 DEFINE_RES_IRQ(gic_spi(11)), /* IRQ10 */
640 DEFINE_RES_IRQ(gic_spi(12)), /* IRQ11 */
641 DEFINE_RES_IRQ(gic_spi(13)), /* IRQ12 */
642 DEFINE_RES_IRQ(gic_spi(14)), /* IRQ13 */
643 DEFINE_RES_IRQ(gic_spi(15)), /* IRQ14 */
644 DEFINE_RES_IRQ(gic_spi(16)), /* IRQ15 */
647 static struct platform_device irqpin1_device = {
648 .name = "renesas_intc_irqpin",
650 .resource = irqpin1_resources,
651 .num_resources = ARRAY_SIZE(irqpin1_resources),
653 .platform_data = &irqpin1_platform_data,
657 static struct renesas_intc_irqpin_config irqpin2_platform_data = {
658 .irq_base = irq_pin(16), /* IRQ16 -> IRQ23 */
661 static struct resource irqpin2_resources[] = {
662 DEFINE_RES_MEM(0xe6900008, 4), /* ICR3A */
663 DEFINE_RES_MEM(0xe6900018, 4), /* INTPRI20A */
664 DEFINE_RES_MEM(0xe6900028, 1), /* INTREQ20A */
665 DEFINE_RES_MEM(0xe6900048, 1), /* INTMSK20A */
666 DEFINE_RES_MEM(0xe6900068, 1), /* INTMSKCLR20A */
667 DEFINE_RES_IRQ(gic_spi(17)), /* IRQ16 */
668 DEFINE_RES_IRQ(gic_spi(18)), /* IRQ17 */
669 DEFINE_RES_IRQ(gic_spi(19)), /* IRQ18 */
670 DEFINE_RES_IRQ(gic_spi(20)), /* IRQ19 */
671 DEFINE_RES_IRQ(gic_spi(21)), /* IRQ20 */
672 DEFINE_RES_IRQ(gic_spi(22)), /* IRQ21 */
673 DEFINE_RES_IRQ(gic_spi(23)), /* IRQ22 */
674 DEFINE_RES_IRQ(gic_spi(24)), /* IRQ23 */
677 static struct platform_device irqpin2_device = {
678 .name = "renesas_intc_irqpin",
680 .resource = irqpin2_resources,
681 .num_resources = ARRAY_SIZE(irqpin2_resources),
683 .platform_data = &irqpin2_platform_data,
687 static struct renesas_intc_irqpin_config irqpin3_platform_data = {
688 .irq_base = irq_pin(24), /* IRQ24 -> IRQ31 */
691 static struct resource irqpin3_resources[] = {
692 DEFINE_RES_MEM(0xe690000c, 4), /* ICR4A */
693 DEFINE_RES_MEM(0xe690001c, 4), /* INTPRI30A */
694 DEFINE_RES_MEM(0xe690002c, 1), /* INTREQ30A */
695 DEFINE_RES_MEM(0xe690004c, 1), /* INTMSK30A */
696 DEFINE_RES_MEM(0xe690006c, 1), /* INTMSKCLR30A */
697 DEFINE_RES_IRQ(gic_spi(25)), /* IRQ24 */
698 DEFINE_RES_IRQ(gic_spi(26)), /* IRQ25 */
699 DEFINE_RES_IRQ(gic_spi(27)), /* IRQ26 */
700 DEFINE_RES_IRQ(gic_spi(28)), /* IRQ27 */
701 DEFINE_RES_IRQ(gic_spi(29)), /* IRQ28 */
702 DEFINE_RES_IRQ(gic_spi(30)), /* IRQ29 */
703 DEFINE_RES_IRQ(gic_spi(31)), /* IRQ30 */
704 DEFINE_RES_IRQ(gic_spi(32)), /* IRQ31 */
707 static struct platform_device irqpin3_device = {
708 .name = "renesas_intc_irqpin",
710 .resource = irqpin3_resources,
711 .num_resources = ARRAY_SIZE(irqpin3_resources),
713 .platform_data = &irqpin3_platform_data,
717 static struct platform_device *sh73a0_early_devices[] __initdata = {
732 static struct platform_device *sh73a0_late_devices[] __initdata = {
747 #define SRCR2 IOMEM(0xe61580b0)
749 void __init sh73a0_add_standard_devices(void)
751 /* Clear software reset bit on SY-DMAC module */
752 __raw_writel(__raw_readl(SRCR2) & ~(1 << 18), SRCR2);
754 platform_add_devices(sh73a0_early_devices,
755 ARRAY_SIZE(sh73a0_early_devices));
756 platform_add_devices(sh73a0_late_devices,
757 ARRAY_SIZE(sh73a0_late_devices));
760 /* do nothing for !CONFIG_SMP or !CONFIG_HAVE_TWD */
761 void __init __weak sh73a0_register_twd(void) { }
763 void __init sh73a0_earlytimer_init(void)
765 shmobile_init_delay();
767 shmobile_earlytimer_init();
768 sh73a0_register_twd();
771 void __init sh73a0_add_early_devices(void)
773 early_platform_add_devices(sh73a0_early_devices,
774 ARRAY_SIZE(sh73a0_early_devices));
776 /* setup early console here as well */
777 shmobile_setup_console();
782 void __init sh73a0_add_standard_devices_dt(void)
784 /* clocks are setup late during boot in the case of DT */
787 of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
790 #define RESCNT2 IOMEM(0xe6188020)
791 static void sh73a0_restart(enum reboot_mode mode, const char *cmd)
793 /* Do soft power on reset */
794 writel((1 << 31), RESCNT2);
797 static const char *sh73a0_boards_compat_dt[] __initdata = {
802 DT_MACHINE_START(SH73A0_DT, "Generic SH73A0 (Flattened Device Tree)")
803 .smp = smp_ops(sh73a0_smp_ops),
804 .map_io = sh73a0_map_io,
805 .init_early = shmobile_init_delay,
806 .init_machine = sh73a0_add_standard_devices_dt,
807 .init_late = shmobile_init_late,
808 .restart = sh73a0_restart,
809 .dt_compat = sh73a0_boards_compat_dt,
811 #endif /* CONFIG_USE_OF */