2 * sh73a0 processor support
4 * Copyright (C) 2010 Takashi Yoshii
5 * Copyright (C) 2010 Magnus Damm
6 * Copyright (C) 2008 Yoshihiro Shimoda
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; version 2 of the License.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
21 #include <linux/kernel.h>
22 #include <linux/init.h>
23 #include <linux/interrupt.h>
24 #include <linux/irq.h>
25 #include <linux/platform_device.h>
26 #include <linux/of_platform.h>
27 #include <linux/delay.h>
28 #include <linux/input.h>
30 #include <linux/serial_sci.h>
31 #include <linux/sh_dma.h>
32 #include <linux/sh_intc.h>
33 #include <linux/sh_timer.h>
34 #include <linux/platform_data/sh_ipmmu.h>
35 #include <mach/dma-register.h>
36 #include <mach/hardware.h>
37 #include <mach/irqs.h>
38 #include <mach/sh73a0.h>
39 #include <mach/common.h>
40 #include <asm/mach-types.h>
41 #include <asm/mach/map.h>
42 #include <asm/mach/arch.h>
43 #include <asm/mach/time.h>
45 static struct map_desc sh73a0_io_desc[] __initdata = {
46 /* create a 1:1 entity map for 0xe6xxxxxx
47 * used by CPGA, INTC and PFC.
50 .virtual = 0xe6000000,
51 .pfn = __phys_to_pfn(0xe6000000),
53 .type = MT_DEVICE_NONSHARED
57 void __init sh73a0_map_io(void)
59 iotable_init(sh73a0_io_desc, ARRAY_SIZE(sh73a0_io_desc));
62 static struct resource sh73a0_pfc_resources[] = {
66 .flags = IORESOURCE_MEM,
71 .flags = IORESOURCE_MEM,
75 static struct platform_device sh73a0_pfc_device = {
78 .resource = sh73a0_pfc_resources,
79 .num_resources = ARRAY_SIZE(sh73a0_pfc_resources),
82 void __init sh73a0_pinmux_init(void)
84 platform_device_register(&sh73a0_pfc_device);
87 static struct plat_sci_port scif0_platform_data = {
88 .mapbase = 0xe6c40000,
89 .flags = UPF_BOOT_AUTOCONF,
90 .scscr = SCSCR_RE | SCSCR_TE,
91 .scbrr_algo_id = SCBRR_ALGO_4,
93 .irqs = { gic_spi(72), gic_spi(72),
94 gic_spi(72), gic_spi(72) },
97 static struct platform_device scif0_device = {
101 .platform_data = &scif0_platform_data,
105 static struct plat_sci_port scif1_platform_data = {
106 .mapbase = 0xe6c50000,
107 .flags = UPF_BOOT_AUTOCONF,
108 .scscr = SCSCR_RE | SCSCR_TE,
109 .scbrr_algo_id = SCBRR_ALGO_4,
111 .irqs = { gic_spi(73), gic_spi(73),
112 gic_spi(73), gic_spi(73) },
115 static struct platform_device scif1_device = {
119 .platform_data = &scif1_platform_data,
123 static struct plat_sci_port scif2_platform_data = {
124 .mapbase = 0xe6c60000,
125 .flags = UPF_BOOT_AUTOCONF,
126 .scscr = SCSCR_RE | SCSCR_TE,
127 .scbrr_algo_id = SCBRR_ALGO_4,
129 .irqs = { gic_spi(74), gic_spi(74),
130 gic_spi(74), gic_spi(74) },
133 static struct platform_device scif2_device = {
137 .platform_data = &scif2_platform_data,
141 static struct plat_sci_port scif3_platform_data = {
142 .mapbase = 0xe6c70000,
143 .flags = UPF_BOOT_AUTOCONF,
144 .scscr = SCSCR_RE | SCSCR_TE,
145 .scbrr_algo_id = SCBRR_ALGO_4,
147 .irqs = { gic_spi(75), gic_spi(75),
148 gic_spi(75), gic_spi(75) },
151 static struct platform_device scif3_device = {
155 .platform_data = &scif3_platform_data,
159 static struct plat_sci_port scif4_platform_data = {
160 .mapbase = 0xe6c80000,
161 .flags = UPF_BOOT_AUTOCONF,
162 .scscr = SCSCR_RE | SCSCR_TE,
163 .scbrr_algo_id = SCBRR_ALGO_4,
165 .irqs = { gic_spi(78), gic_spi(78),
166 gic_spi(78), gic_spi(78) },
169 static struct platform_device scif4_device = {
173 .platform_data = &scif4_platform_data,
177 static struct plat_sci_port scif5_platform_data = {
178 .mapbase = 0xe6cb0000,
179 .flags = UPF_BOOT_AUTOCONF,
180 .scscr = SCSCR_RE | SCSCR_TE,
181 .scbrr_algo_id = SCBRR_ALGO_4,
183 .irqs = { gic_spi(79), gic_spi(79),
184 gic_spi(79), gic_spi(79) },
187 static struct platform_device scif5_device = {
191 .platform_data = &scif5_platform_data,
195 static struct plat_sci_port scif6_platform_data = {
196 .mapbase = 0xe6cc0000,
197 .flags = UPF_BOOT_AUTOCONF,
198 .scscr = SCSCR_RE | SCSCR_TE,
199 .scbrr_algo_id = SCBRR_ALGO_4,
201 .irqs = { gic_spi(156), gic_spi(156),
202 gic_spi(156), gic_spi(156) },
205 static struct platform_device scif6_device = {
209 .platform_data = &scif6_platform_data,
213 static struct plat_sci_port scif7_platform_data = {
214 .mapbase = 0xe6cd0000,
215 .flags = UPF_BOOT_AUTOCONF,
216 .scscr = SCSCR_RE | SCSCR_TE,
217 .scbrr_algo_id = SCBRR_ALGO_4,
219 .irqs = { gic_spi(143), gic_spi(143),
220 gic_spi(143), gic_spi(143) },
223 static struct platform_device scif7_device = {
227 .platform_data = &scif7_platform_data,
231 static struct plat_sci_port scif8_platform_data = {
232 .mapbase = 0xe6c30000,
233 .flags = UPF_BOOT_AUTOCONF,
234 .scscr = SCSCR_RE | SCSCR_TE,
235 .scbrr_algo_id = SCBRR_ALGO_4,
237 .irqs = { gic_spi(80), gic_spi(80),
238 gic_spi(80), gic_spi(80) },
241 static struct platform_device scif8_device = {
245 .platform_data = &scif8_platform_data,
249 static struct sh_timer_config cmt10_platform_data = {
251 .channel_offset = 0x10,
253 .clockevent_rating = 125,
254 .clocksource_rating = 125,
257 static struct resource cmt10_resources[] = {
262 .flags = IORESOURCE_MEM,
265 .start = gic_spi(65),
266 .flags = IORESOURCE_IRQ,
270 static struct platform_device cmt10_device = {
274 .platform_data = &cmt10_platform_data,
276 .resource = cmt10_resources,
277 .num_resources = ARRAY_SIZE(cmt10_resources),
281 static struct sh_timer_config tmu00_platform_data = {
283 .channel_offset = 0x4,
285 .clockevent_rating = 200,
288 static struct resource tmu00_resources[] = {
293 .flags = IORESOURCE_MEM,
296 .start = intcs_evt2irq(0x0e80), /* TMU0_TUNI00 */
297 .flags = IORESOURCE_IRQ,
301 static struct platform_device tmu00_device = {
305 .platform_data = &tmu00_platform_data,
307 .resource = tmu00_resources,
308 .num_resources = ARRAY_SIZE(tmu00_resources),
311 static struct sh_timer_config tmu01_platform_data = {
313 .channel_offset = 0x10,
315 .clocksource_rating = 200,
318 static struct resource tmu01_resources[] = {
323 .flags = IORESOURCE_MEM,
326 .start = intcs_evt2irq(0x0ea0), /* TMU0_TUNI01 */
327 .flags = IORESOURCE_IRQ,
331 static struct platform_device tmu01_device = {
335 .platform_data = &tmu01_platform_data,
337 .resource = tmu01_resources,
338 .num_resources = ARRAY_SIZE(tmu01_resources),
341 static struct resource i2c0_resources[] = {
345 .end = 0xe6820425 - 1,
346 .flags = IORESOURCE_MEM,
349 .start = gic_spi(167),
351 .flags = IORESOURCE_IRQ,
355 static struct resource i2c1_resources[] = {
359 .end = 0xe6822425 - 1,
360 .flags = IORESOURCE_MEM,
363 .start = gic_spi(51),
365 .flags = IORESOURCE_IRQ,
369 static struct resource i2c2_resources[] = {
373 .end = 0xe6824425 - 1,
374 .flags = IORESOURCE_MEM,
377 .start = gic_spi(171),
379 .flags = IORESOURCE_IRQ,
383 static struct resource i2c3_resources[] = {
387 .end = 0xe6826425 - 1,
388 .flags = IORESOURCE_MEM,
391 .start = gic_spi(183),
393 .flags = IORESOURCE_IRQ,
397 static struct resource i2c4_resources[] = {
401 .end = 0xe6828425 - 1,
402 .flags = IORESOURCE_MEM,
405 .start = gic_spi(187),
407 .flags = IORESOURCE_IRQ,
411 static struct platform_device i2c0_device = {
412 .name = "i2c-sh_mobile",
414 .resource = i2c0_resources,
415 .num_resources = ARRAY_SIZE(i2c0_resources),
418 static struct platform_device i2c1_device = {
419 .name = "i2c-sh_mobile",
421 .resource = i2c1_resources,
422 .num_resources = ARRAY_SIZE(i2c1_resources),
425 static struct platform_device i2c2_device = {
426 .name = "i2c-sh_mobile",
428 .resource = i2c2_resources,
429 .num_resources = ARRAY_SIZE(i2c2_resources),
432 static struct platform_device i2c3_device = {
433 .name = "i2c-sh_mobile",
435 .resource = i2c3_resources,
436 .num_resources = ARRAY_SIZE(i2c3_resources),
439 static struct platform_device i2c4_device = {
440 .name = "i2c-sh_mobile",
442 .resource = i2c4_resources,
443 .num_resources = ARRAY_SIZE(i2c4_resources),
446 static const struct sh_dmae_slave_config sh73a0_dmae_slaves[] = {
448 .slave_id = SHDMA_SLAVE_SCIF0_TX,
450 .chcr = CHCR_TX(XMIT_SZ_8BIT),
453 .slave_id = SHDMA_SLAVE_SCIF0_RX,
455 .chcr = CHCR_RX(XMIT_SZ_8BIT),
458 .slave_id = SHDMA_SLAVE_SCIF1_TX,
460 .chcr = CHCR_TX(XMIT_SZ_8BIT),
463 .slave_id = SHDMA_SLAVE_SCIF1_RX,
465 .chcr = CHCR_RX(XMIT_SZ_8BIT),
468 .slave_id = SHDMA_SLAVE_SCIF2_TX,
470 .chcr = CHCR_TX(XMIT_SZ_8BIT),
473 .slave_id = SHDMA_SLAVE_SCIF2_RX,
475 .chcr = CHCR_RX(XMIT_SZ_8BIT),
478 .slave_id = SHDMA_SLAVE_SCIF3_TX,
480 .chcr = CHCR_TX(XMIT_SZ_8BIT),
483 .slave_id = SHDMA_SLAVE_SCIF3_RX,
485 .chcr = CHCR_RX(XMIT_SZ_8BIT),
488 .slave_id = SHDMA_SLAVE_SCIF4_TX,
490 .chcr = CHCR_TX(XMIT_SZ_8BIT),
493 .slave_id = SHDMA_SLAVE_SCIF4_RX,
495 .chcr = CHCR_RX(XMIT_SZ_8BIT),
498 .slave_id = SHDMA_SLAVE_SCIF5_TX,
500 .chcr = CHCR_TX(XMIT_SZ_8BIT),
503 .slave_id = SHDMA_SLAVE_SCIF5_RX,
505 .chcr = CHCR_RX(XMIT_SZ_8BIT),
508 .slave_id = SHDMA_SLAVE_SCIF6_TX,
510 .chcr = CHCR_TX(XMIT_SZ_8BIT),
513 .slave_id = SHDMA_SLAVE_SCIF6_RX,
515 .chcr = CHCR_RX(XMIT_SZ_8BIT),
518 .slave_id = SHDMA_SLAVE_SCIF7_TX,
520 .chcr = CHCR_TX(XMIT_SZ_8BIT),
523 .slave_id = SHDMA_SLAVE_SCIF7_RX,
525 .chcr = CHCR_RX(XMIT_SZ_8BIT),
528 .slave_id = SHDMA_SLAVE_SCIF8_TX,
530 .chcr = CHCR_TX(XMIT_SZ_8BIT),
533 .slave_id = SHDMA_SLAVE_SCIF8_RX,
535 .chcr = CHCR_RX(XMIT_SZ_8BIT),
538 .slave_id = SHDMA_SLAVE_SDHI0_TX,
540 .chcr = CHCR_TX(XMIT_SZ_16BIT),
543 .slave_id = SHDMA_SLAVE_SDHI0_RX,
545 .chcr = CHCR_RX(XMIT_SZ_16BIT),
548 .slave_id = SHDMA_SLAVE_SDHI1_TX,
550 .chcr = CHCR_TX(XMIT_SZ_16BIT),
553 .slave_id = SHDMA_SLAVE_SDHI1_RX,
555 .chcr = CHCR_RX(XMIT_SZ_16BIT),
558 .slave_id = SHDMA_SLAVE_SDHI2_TX,
560 .chcr = CHCR_TX(XMIT_SZ_16BIT),
563 .slave_id = SHDMA_SLAVE_SDHI2_RX,
565 .chcr = CHCR_RX(XMIT_SZ_16BIT),
568 .slave_id = SHDMA_SLAVE_MMCIF_TX,
570 .chcr = CHCR_TX(XMIT_SZ_32BIT),
573 .slave_id = SHDMA_SLAVE_MMCIF_RX,
575 .chcr = CHCR_RX(XMIT_SZ_32BIT),
580 #define DMAE_CHANNEL(_offset) \
582 .offset = _offset - 0x20, \
583 .dmars = _offset - 0x20 + 0x40, \
586 static const struct sh_dmae_channel sh73a0_dmae_channels[] = {
587 DMAE_CHANNEL(0x8000),
588 DMAE_CHANNEL(0x8080),
589 DMAE_CHANNEL(0x8100),
590 DMAE_CHANNEL(0x8180),
591 DMAE_CHANNEL(0x8200),
592 DMAE_CHANNEL(0x8280),
593 DMAE_CHANNEL(0x8300),
594 DMAE_CHANNEL(0x8380),
595 DMAE_CHANNEL(0x8400),
596 DMAE_CHANNEL(0x8480),
597 DMAE_CHANNEL(0x8500),
598 DMAE_CHANNEL(0x8580),
599 DMAE_CHANNEL(0x8600),
600 DMAE_CHANNEL(0x8680),
601 DMAE_CHANNEL(0x8700),
602 DMAE_CHANNEL(0x8780),
603 DMAE_CHANNEL(0x8800),
604 DMAE_CHANNEL(0x8880),
605 DMAE_CHANNEL(0x8900),
606 DMAE_CHANNEL(0x8980),
609 static struct sh_dmae_pdata sh73a0_dmae_platform_data = {
610 .slave = sh73a0_dmae_slaves,
611 .slave_num = ARRAY_SIZE(sh73a0_dmae_slaves),
612 .channel = sh73a0_dmae_channels,
613 .channel_num = ARRAY_SIZE(sh73a0_dmae_channels),
614 .ts_low_shift = TS_LOW_SHIFT,
615 .ts_low_mask = TS_LOW_BIT << TS_LOW_SHIFT,
616 .ts_high_shift = TS_HI_SHIFT,
617 .ts_high_mask = TS_HI_BIT << TS_HI_SHIFT,
618 .ts_shift = dma_ts_shift,
619 .ts_shift_num = ARRAY_SIZE(dma_ts_shift),
620 .dmaor_init = DMAOR_DME,
623 static struct resource sh73a0_dmae_resources[] = {
625 /* Registers including DMAOR and channels including DMARSx */
627 .end = 0xfe008a00 - 1,
628 .flags = IORESOURCE_MEM,
632 .start = gic_spi(129),
634 .flags = IORESOURCE_IRQ,
637 /* IRQ for channels 0-19 */
638 .start = gic_spi(109),
640 .flags = IORESOURCE_IRQ,
644 static struct platform_device dma0_device = {
645 .name = "sh-dma-engine",
647 .resource = sh73a0_dmae_resources,
648 .num_resources = ARRAY_SIZE(sh73a0_dmae_resources),
650 .platform_data = &sh73a0_dmae_platform_data,
655 static const struct sh_dmae_slave_config sh73a0_mpdma_slaves[] = {
657 .slave_id = SHDMA_SLAVE_FSI2A_RX,
659 .chcr = CHCR_RX(XMIT_SZ_32BIT),
660 .mid_rid = 0xd6, /* CHECK ME */
662 .slave_id = SHDMA_SLAVE_FSI2A_TX,
664 .chcr = CHCR_TX(XMIT_SZ_32BIT),
665 .mid_rid = 0xd5, /* CHECK ME */
667 .slave_id = SHDMA_SLAVE_FSI2C_RX,
669 .chcr = CHCR_RX(XMIT_SZ_32BIT),
670 .mid_rid = 0xda, /* CHECK ME */
672 .slave_id = SHDMA_SLAVE_FSI2C_TX,
674 .chcr = CHCR_TX(XMIT_SZ_32BIT),
675 .mid_rid = 0xd9, /* CHECK ME */
677 .slave_id = SHDMA_SLAVE_FSI2B_RX,
679 .chcr = CHCR_RX(XMIT_SZ_32BIT),
680 .mid_rid = 0x8e, /* CHECK ME */
682 .slave_id = SHDMA_SLAVE_FSI2B_TX,
684 .chcr = CHCR_RX(XMIT_SZ_32BIT),
685 .mid_rid = 0x8d, /* CHECK ME */
687 .slave_id = SHDMA_SLAVE_FSI2D_RX,
689 .chcr = CHCR_RX(XMIT_SZ_32BIT),
690 .mid_rid = 0x9a, /* CHECK ME */
694 #define MPDMA_CHANNEL(a, b, c) \
699 .chclr_offset = (0x220 - 0x20) + a \
702 static const struct sh_dmae_channel sh73a0_mpdma_channels[] = {
703 MPDMA_CHANNEL(0x00, 0, 0),
704 MPDMA_CHANNEL(0x10, 0, 8),
705 MPDMA_CHANNEL(0x20, 4, 0),
706 MPDMA_CHANNEL(0x30, 4, 8),
707 MPDMA_CHANNEL(0x50, 8, 0),
708 MPDMA_CHANNEL(0x70, 8, 8),
711 static struct sh_dmae_pdata sh73a0_mpdma_platform_data = {
712 .slave = sh73a0_mpdma_slaves,
713 .slave_num = ARRAY_SIZE(sh73a0_mpdma_slaves),
714 .channel = sh73a0_mpdma_channels,
715 .channel_num = ARRAY_SIZE(sh73a0_mpdma_channels),
716 .ts_low_shift = TS_LOW_SHIFT,
717 .ts_low_mask = TS_LOW_BIT << TS_LOW_SHIFT,
718 .ts_high_shift = TS_HI_SHIFT,
719 .ts_high_mask = TS_HI_BIT << TS_HI_SHIFT,
720 .ts_shift = dma_ts_shift,
721 .ts_shift_num = ARRAY_SIZE(dma_ts_shift),
722 .dmaor_init = DMAOR_DME,
726 /* Resource order important! */
727 static struct resource sh73a0_mpdma_resources[] = {
729 /* Channel registers and DMAOR */
732 .flags = IORESOURCE_MEM,
738 .flags = IORESOURCE_MEM,
742 .start = gic_spi(181),
744 .flags = IORESOURCE_IRQ,
747 /* IRQ for channels 0-5 */
748 .start = gic_spi(175),
750 .flags = IORESOURCE_IRQ,
754 static struct platform_device mpdma0_device = {
755 .name = "sh-dma-engine",
757 .resource = sh73a0_mpdma_resources,
758 .num_resources = ARRAY_SIZE(sh73a0_mpdma_resources),
760 .platform_data = &sh73a0_mpdma_platform_data,
764 static struct resource pmu_resources[] = {
766 .start = gic_spi(55),
768 .flags = IORESOURCE_IRQ,
771 .start = gic_spi(56),
773 .flags = IORESOURCE_IRQ,
777 static struct platform_device pmu_device = {
780 .num_resources = ARRAY_SIZE(pmu_resources),
781 .resource = pmu_resources,
784 /* an IPMMU module for ICB */
785 static struct resource ipmmu_resources[] = {
790 .flags = IORESOURCE_MEM,
794 static const char * const ipmmu_dev_names[] = {
795 "sh_mobile_lcdc_fb.0",
798 static struct shmobile_ipmmu_platform_data ipmmu_platform_data = {
799 .dev_names = ipmmu_dev_names,
800 .num_dev_names = ARRAY_SIZE(ipmmu_dev_names),
803 static struct platform_device ipmmu_device = {
807 .platform_data = &ipmmu_platform_data,
809 .resource = ipmmu_resources,
810 .num_resources = ARRAY_SIZE(ipmmu_resources),
813 static struct platform_device *sh73a0_early_devices_dt[] __initdata = {
826 static struct platform_device *sh73a0_early_devices[] __initdata = {
832 static struct platform_device *sh73a0_late_devices[] __initdata = {
843 #define SRCR2 IOMEM(0xe61580b0)
845 void __init sh73a0_add_standard_devices(void)
847 /* Clear software reset bit on SY-DMAC module */
848 __raw_writel(__raw_readl(SRCR2) & ~(1 << 18), SRCR2);
850 platform_add_devices(sh73a0_early_devices_dt,
851 ARRAY_SIZE(sh73a0_early_devices_dt));
852 platform_add_devices(sh73a0_early_devices,
853 ARRAY_SIZE(sh73a0_early_devices));
854 platform_add_devices(sh73a0_late_devices,
855 ARRAY_SIZE(sh73a0_late_devices));
858 /* do nothing for !CONFIG_SMP or !CONFIG_HAVE_TWD */
859 void __init __weak sh73a0_register_twd(void) { }
861 void __init sh73a0_earlytimer_init(void)
864 shmobile_earlytimer_init();
865 sh73a0_register_twd();
868 void __init sh73a0_add_early_devices(void)
870 early_platform_add_devices(sh73a0_early_devices_dt,
871 ARRAY_SIZE(sh73a0_early_devices_dt));
872 early_platform_add_devices(sh73a0_early_devices,
873 ARRAY_SIZE(sh73a0_early_devices));
875 /* setup early console here as well */
876 shmobile_setup_console();
881 /* Please note that the clock initialisation shcheme used in
882 * sh73a0_add_early_devices_dt() and sh73a0_add_standard_devices_dt()
883 * does not work with SMP as there is a yet to be resolved lock-up in
884 * workqueue initialisation.
886 * CONFIG_SMP should be disabled when using this code.
889 void __init sh73a0_add_early_devices_dt(void)
891 shmobile_setup_delay(1196, 44, 46); /* Cortex-A9 @ 1196MHz */
893 early_platform_add_devices(sh73a0_early_devices_dt,
894 ARRAY_SIZE(sh73a0_early_devices_dt));
896 /* setup early console here as well */
897 shmobile_setup_console();
900 static const struct of_dev_auxdata sh73a0_auxdata_lookup[] __initconst = {
904 void __init sh73a0_add_standard_devices_dt(void)
906 /* clocks are setup late during boot in the case of DT */
909 platform_add_devices(sh73a0_early_devices_dt,
910 ARRAY_SIZE(sh73a0_early_devices_dt));
911 of_platform_populate(NULL, of_default_bus_match_table,
912 sh73a0_auxdata_lookup, NULL);
915 static const char *sh73a0_boards_compat_dt[] __initdata = {
920 DT_MACHINE_START(SH73A0_DT, "Generic SH73A0 (Flattened Device Tree)")
921 .map_io = sh73a0_map_io,
922 .init_early = sh73a0_add_early_devices_dt,
923 .nr_irqs = NR_IRQS_LEGACY,
924 .init_irq = sh73a0_init_irq_dt,
925 .init_machine = sh73a0_add_standard_devices_dt,
926 .init_time = shmobile_timer_init,
927 .dt_compat = sh73a0_boards_compat_dt,
929 #endif /* CONFIG_USE_OF */