2 * sh7372 processor support
4 * Copyright (C) 2010 Magnus Damm
5 * Copyright (C) 2008 Yoshihiro Shimoda
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 #include <linux/kernel.h>
21 #include <linux/init.h>
22 #include <linux/interrupt.h>
23 #include <linux/irq.h>
24 #include <linux/platform_device.h>
25 #include <linux/delay.h>
26 #include <linux/input.h>
28 #include <linux/serial_sci.h>
29 #include <linux/sh_dma.h>
30 #include <linux/sh_intc.h>
31 #include <linux/sh_timer.h>
32 #include <mach/hardware.h>
33 #include <mach/sh7372.h>
34 #include <asm/mach-types.h>
35 #include <asm/mach/arch.h>
38 static struct plat_sci_port scif0_platform_data = {
39 .mapbase = 0xe6c40000,
40 .flags = UPF_BOOT_AUTOCONF,
41 .scscr = SCSCR_RE | SCSCR_TE,
42 .scbrr_algo_id = SCBRR_ALGO_4,
44 .irqs = { evt2irq(0x0c00), evt2irq(0x0c00),
45 evt2irq(0x0c00), evt2irq(0x0c00) },
48 static struct platform_device scif0_device = {
52 .platform_data = &scif0_platform_data,
57 static struct plat_sci_port scif1_platform_data = {
58 .mapbase = 0xe6c50000,
59 .flags = UPF_BOOT_AUTOCONF,
60 .scscr = SCSCR_RE | SCSCR_TE,
61 .scbrr_algo_id = SCBRR_ALGO_4,
63 .irqs = { evt2irq(0x0c20), evt2irq(0x0c20),
64 evt2irq(0x0c20), evt2irq(0x0c20) },
67 static struct platform_device scif1_device = {
71 .platform_data = &scif1_platform_data,
76 static struct plat_sci_port scif2_platform_data = {
77 .mapbase = 0xe6c60000,
78 .flags = UPF_BOOT_AUTOCONF,
79 .scscr = SCSCR_RE | SCSCR_TE,
80 .scbrr_algo_id = SCBRR_ALGO_4,
82 .irqs = { evt2irq(0x0c40), evt2irq(0x0c40),
83 evt2irq(0x0c40), evt2irq(0x0c40) },
86 static struct platform_device scif2_device = {
90 .platform_data = &scif2_platform_data,
95 static struct plat_sci_port scif3_platform_data = {
96 .mapbase = 0xe6c70000,
97 .flags = UPF_BOOT_AUTOCONF,
98 .scscr = SCSCR_RE | SCSCR_TE,
99 .scbrr_algo_id = SCBRR_ALGO_4,
101 .irqs = { evt2irq(0x0c60), evt2irq(0x0c60),
102 evt2irq(0x0c60), evt2irq(0x0c60) },
105 static struct platform_device scif3_device = {
109 .platform_data = &scif3_platform_data,
114 static struct plat_sci_port scif4_platform_data = {
115 .mapbase = 0xe6c80000,
116 .flags = UPF_BOOT_AUTOCONF,
117 .scscr = SCSCR_RE | SCSCR_TE,
118 .scbrr_algo_id = SCBRR_ALGO_4,
120 .irqs = { evt2irq(0x0d20), evt2irq(0x0d20),
121 evt2irq(0x0d20), evt2irq(0x0d20) },
124 static struct platform_device scif4_device = {
128 .platform_data = &scif4_platform_data,
133 static struct plat_sci_port scif5_platform_data = {
134 .mapbase = 0xe6cb0000,
135 .flags = UPF_BOOT_AUTOCONF,
136 .scscr = SCSCR_RE | SCSCR_TE,
137 .scbrr_algo_id = SCBRR_ALGO_4,
139 .irqs = { evt2irq(0x0d40), evt2irq(0x0d40),
140 evt2irq(0x0d40), evt2irq(0x0d40) },
143 static struct platform_device scif5_device = {
147 .platform_data = &scif5_platform_data,
152 static struct plat_sci_port scif6_platform_data = {
153 .mapbase = 0xe6c30000,
154 .flags = UPF_BOOT_AUTOCONF,
155 .scscr = SCSCR_RE | SCSCR_TE,
156 .scbrr_algo_id = SCBRR_ALGO_4,
158 .irqs = { evt2irq(0x0d60), evt2irq(0x0d60),
159 evt2irq(0x0d60), evt2irq(0x0d60) },
162 static struct platform_device scif6_device = {
166 .platform_data = &scif6_platform_data,
171 static struct sh_timer_config cmt10_platform_data = {
173 .channel_offset = 0x10,
175 .clockevent_rating = 125,
176 .clocksource_rating = 125,
179 static struct resource cmt10_resources[] = {
184 .flags = IORESOURCE_MEM,
187 .start = evt2irq(0x0b00), /* CMT1_CMT10 */
188 .flags = IORESOURCE_IRQ,
192 static struct platform_device cmt10_device = {
196 .platform_data = &cmt10_platform_data,
198 .resource = cmt10_resources,
199 .num_resources = ARRAY_SIZE(cmt10_resources),
203 static struct sh_timer_config tmu00_platform_data = {
205 .channel_offset = 0x4,
207 .clockevent_rating = 200,
210 static struct resource tmu00_resources[] = {
215 .flags = IORESOURCE_MEM,
218 .start = intcs_evt2irq(0xe80), /* TMU_TUNI0 */
219 .flags = IORESOURCE_IRQ,
223 static struct platform_device tmu00_device = {
227 .platform_data = &tmu00_platform_data,
229 .resource = tmu00_resources,
230 .num_resources = ARRAY_SIZE(tmu00_resources),
233 static struct sh_timer_config tmu01_platform_data = {
235 .channel_offset = 0x10,
237 .clocksource_rating = 200,
240 static struct resource tmu01_resources[] = {
245 .flags = IORESOURCE_MEM,
248 .start = intcs_evt2irq(0xea0), /* TMU_TUNI1 */
249 .flags = IORESOURCE_IRQ,
253 static struct platform_device tmu01_device = {
257 .platform_data = &tmu01_platform_data,
259 .resource = tmu01_resources,
260 .num_resources = ARRAY_SIZE(tmu01_resources),
264 static struct resource iic0_resources[] = {
268 .end = 0xFFF20425 - 1,
269 .flags = IORESOURCE_MEM,
272 .start = intcs_evt2irq(0xe00), /* IIC0_ALI0 */
273 .end = intcs_evt2irq(0xe60), /* IIC0_DTEI0 */
274 .flags = IORESOURCE_IRQ,
278 static struct platform_device iic0_device = {
279 .name = "i2c-sh_mobile",
280 .id = 0, /* "i2c0" clock */
281 .num_resources = ARRAY_SIZE(iic0_resources),
282 .resource = iic0_resources,
285 static struct resource iic1_resources[] = {
289 .end = 0xE6C20425 - 1,
290 .flags = IORESOURCE_MEM,
293 .start = evt2irq(0x780), /* IIC1_ALI1 */
294 .end = evt2irq(0x7e0), /* IIC1_DTEI1 */
295 .flags = IORESOURCE_IRQ,
299 static struct platform_device iic1_device = {
300 .name = "i2c-sh_mobile",
301 .id = 1, /* "i2c1" clock */
302 .num_resources = ARRAY_SIZE(iic1_resources),
303 .resource = iic1_resources,
307 /* Transmit sizes and respective CHCR register values */
318 /* log2(size / 8) - used to calculate number of transfers */
320 [XMIT_SZ_8BIT] = 0, \
321 [XMIT_SZ_16BIT] = 1, \
322 [XMIT_SZ_32BIT] = 2, \
323 [XMIT_SZ_64BIT] = 3, \
324 [XMIT_SZ_128BIT] = 4, \
325 [XMIT_SZ_256BIT] = 5, \
326 [XMIT_SZ_512BIT] = 6, \
329 #define TS_INDEX2VAL(i) ((((i) & 3) << 3) | \
330 (((i) & 0xc) << (20 - 2)))
332 static const struct sh_dmae_slave_config sh7372_dmae_slaves[] = {
334 .slave_id = SHDMA_SLAVE_SCIF0_TX,
336 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
339 .slave_id = SHDMA_SLAVE_SCIF0_RX,
341 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
344 .slave_id = SHDMA_SLAVE_SCIF1_TX,
346 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
349 .slave_id = SHDMA_SLAVE_SCIF1_RX,
351 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
354 .slave_id = SHDMA_SLAVE_SCIF2_TX,
356 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
359 .slave_id = SHDMA_SLAVE_SCIF2_RX,
361 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
364 .slave_id = SHDMA_SLAVE_SCIF3_TX,
366 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
369 .slave_id = SHDMA_SLAVE_SCIF3_RX,
371 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
374 .slave_id = SHDMA_SLAVE_SCIF4_TX,
376 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
379 .slave_id = SHDMA_SLAVE_SCIF4_RX,
381 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
384 .slave_id = SHDMA_SLAVE_SCIF5_TX,
386 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
389 .slave_id = SHDMA_SLAVE_SCIF5_RX,
391 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
394 .slave_id = SHDMA_SLAVE_SCIF6_TX,
396 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
399 .slave_id = SHDMA_SLAVE_SCIF6_RX,
401 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
404 .slave_id = SHDMA_SLAVE_SDHI0_TX,
406 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_16BIT),
409 .slave_id = SHDMA_SLAVE_SDHI0_RX,
411 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_16BIT),
414 .slave_id = SHDMA_SLAVE_SDHI1_TX,
416 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_16BIT),
419 .slave_id = SHDMA_SLAVE_SDHI1_RX,
421 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_16BIT),
424 .slave_id = SHDMA_SLAVE_SDHI2_TX,
426 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_16BIT),
429 .slave_id = SHDMA_SLAVE_SDHI2_RX,
431 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_16BIT),
434 .slave_id = SHDMA_SLAVE_MMCIF_TX,
436 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_32BIT),
439 .slave_id = SHDMA_SLAVE_MMCIF_RX,
441 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_32BIT),
446 static const struct sh_dmae_channel sh7372_dmae_channels[] = {
474 static const unsigned int ts_shift[] = TS_SHIFT;
476 static struct sh_dmae_pdata dma_platform_data = {
477 .slave = sh7372_dmae_slaves,
478 .slave_num = ARRAY_SIZE(sh7372_dmae_slaves),
479 .channel = sh7372_dmae_channels,
480 .channel_num = ARRAY_SIZE(sh7372_dmae_channels),
483 .ts_high_shift = (20 - 2), /* 2 bits for shifted low TS */
484 .ts_high_mask = 0x00300000,
485 .ts_shift = ts_shift,
486 .ts_shift_num = ARRAY_SIZE(ts_shift),
487 .dmaor_init = DMAOR_DME,
490 /* Resource order important! */
491 static struct resource sh7372_dmae0_resources[] = {
493 /* Channel registers and DMAOR */
496 .flags = IORESOURCE_MEM,
502 .flags = IORESOURCE_MEM,
506 .start = evt2irq(0x20c0),
507 .end = evt2irq(0x20c0),
508 .flags = IORESOURCE_IRQ,
511 /* IRQ for channels 0-5 */
512 .start = evt2irq(0x2000),
513 .end = evt2irq(0x20a0),
514 .flags = IORESOURCE_IRQ,
518 /* Resource order important! */
519 static struct resource sh7372_dmae1_resources[] = {
521 /* Channel registers and DMAOR */
524 .flags = IORESOURCE_MEM,
530 .flags = IORESOURCE_MEM,
534 .start = evt2irq(0x21c0),
535 .end = evt2irq(0x21c0),
536 .flags = IORESOURCE_IRQ,
539 /* IRQ for channels 0-5 */
540 .start = evt2irq(0x2100),
541 .end = evt2irq(0x21a0),
542 .flags = IORESOURCE_IRQ,
546 /* Resource order important! */
547 static struct resource sh7372_dmae2_resources[] = {
549 /* Channel registers and DMAOR */
552 .flags = IORESOURCE_MEM,
558 .flags = IORESOURCE_MEM,
562 .start = evt2irq(0x22c0),
563 .end = evt2irq(0x22c0),
564 .flags = IORESOURCE_IRQ,
567 /* IRQ for channels 0-5 */
568 .start = evt2irq(0x2200),
569 .end = evt2irq(0x22a0),
570 .flags = IORESOURCE_IRQ,
574 static struct platform_device dma0_device = {
575 .name = "sh-dma-engine",
577 .resource = sh7372_dmae0_resources,
578 .num_resources = ARRAY_SIZE(sh7372_dmae0_resources),
580 .platform_data = &dma_platform_data,
584 static struct platform_device dma1_device = {
585 .name = "sh-dma-engine",
587 .resource = sh7372_dmae1_resources,
588 .num_resources = ARRAY_SIZE(sh7372_dmae1_resources),
590 .platform_data = &dma_platform_data,
594 static struct platform_device dma2_device = {
595 .name = "sh-dma-engine",
597 .resource = sh7372_dmae2_resources,
598 .num_resources = ARRAY_SIZE(sh7372_dmae2_resources),
600 .platform_data = &dma_platform_data,
604 static struct platform_device *sh7372_early_devices[] __initdata = {
617 static struct platform_device *sh7372_late_devices[] __initdata = {
625 void __init sh7372_add_standard_devices(void)
627 platform_add_devices(sh7372_early_devices,
628 ARRAY_SIZE(sh7372_early_devices));
630 platform_add_devices(sh7372_late_devices,
631 ARRAY_SIZE(sh7372_late_devices));
634 void __init sh7372_add_early_devices(void)
636 early_platform_add_devices(sh7372_early_devices,
637 ARRAY_SIZE(sh7372_early_devices));