2 * sh7372 processor support
4 * Copyright (C) 2010 Magnus Damm
5 * Copyright (C) 2008 Yoshihiro Shimoda
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 #include <linux/kernel.h>
21 #include <linux/init.h>
22 #include <linux/interrupt.h>
23 #include <linux/irq.h>
24 #include <linux/platform_device.h>
25 #include <linux/uio_driver.h>
26 #include <linux/delay.h>
27 #include <linux/input.h>
29 #include <linux/serial_sci.h>
30 #include <linux/sh_dma.h>
31 #include <linux/sh_intc.h>
32 #include <linux/sh_timer.h>
33 #include <linux/pm_domain.h>
34 #include <mach/hardware.h>
35 #include <mach/sh7372.h>
36 #include <asm/mach-types.h>
37 #include <asm/mach/arch.h>
40 static struct plat_sci_port scif0_platform_data = {
41 .mapbase = 0xe6c40000,
42 .flags = UPF_BOOT_AUTOCONF,
43 .scscr = SCSCR_RE | SCSCR_TE,
44 .scbrr_algo_id = SCBRR_ALGO_4,
46 .irqs = { evt2irq(0x0c00), evt2irq(0x0c00),
47 evt2irq(0x0c00), evt2irq(0x0c00) },
50 static struct platform_device scif0_device = {
54 .platform_data = &scif0_platform_data,
59 static struct plat_sci_port scif1_platform_data = {
60 .mapbase = 0xe6c50000,
61 .flags = UPF_BOOT_AUTOCONF,
62 .scscr = SCSCR_RE | SCSCR_TE,
63 .scbrr_algo_id = SCBRR_ALGO_4,
65 .irqs = { evt2irq(0x0c20), evt2irq(0x0c20),
66 evt2irq(0x0c20), evt2irq(0x0c20) },
69 static struct platform_device scif1_device = {
73 .platform_data = &scif1_platform_data,
78 static struct plat_sci_port scif2_platform_data = {
79 .mapbase = 0xe6c60000,
80 .flags = UPF_BOOT_AUTOCONF,
81 .scscr = SCSCR_RE | SCSCR_TE,
82 .scbrr_algo_id = SCBRR_ALGO_4,
84 .irqs = { evt2irq(0x0c40), evt2irq(0x0c40),
85 evt2irq(0x0c40), evt2irq(0x0c40) },
88 static struct platform_device scif2_device = {
92 .platform_data = &scif2_platform_data,
97 static struct plat_sci_port scif3_platform_data = {
98 .mapbase = 0xe6c70000,
99 .flags = UPF_BOOT_AUTOCONF,
100 .scscr = SCSCR_RE | SCSCR_TE,
101 .scbrr_algo_id = SCBRR_ALGO_4,
103 .irqs = { evt2irq(0x0c60), evt2irq(0x0c60),
104 evt2irq(0x0c60), evt2irq(0x0c60) },
107 static struct platform_device scif3_device = {
111 .platform_data = &scif3_platform_data,
116 static struct plat_sci_port scif4_platform_data = {
117 .mapbase = 0xe6c80000,
118 .flags = UPF_BOOT_AUTOCONF,
119 .scscr = SCSCR_RE | SCSCR_TE,
120 .scbrr_algo_id = SCBRR_ALGO_4,
122 .irqs = { evt2irq(0x0d20), evt2irq(0x0d20),
123 evt2irq(0x0d20), evt2irq(0x0d20) },
126 static struct platform_device scif4_device = {
130 .platform_data = &scif4_platform_data,
135 static struct plat_sci_port scif5_platform_data = {
136 .mapbase = 0xe6cb0000,
137 .flags = UPF_BOOT_AUTOCONF,
138 .scscr = SCSCR_RE | SCSCR_TE,
139 .scbrr_algo_id = SCBRR_ALGO_4,
141 .irqs = { evt2irq(0x0d40), evt2irq(0x0d40),
142 evt2irq(0x0d40), evt2irq(0x0d40) },
145 static struct platform_device scif5_device = {
149 .platform_data = &scif5_platform_data,
154 static struct plat_sci_port scif6_platform_data = {
155 .mapbase = 0xe6c30000,
156 .flags = UPF_BOOT_AUTOCONF,
157 .scscr = SCSCR_RE | SCSCR_TE,
158 .scbrr_algo_id = SCBRR_ALGO_4,
160 .irqs = { evt2irq(0x0d60), evt2irq(0x0d60),
161 evt2irq(0x0d60), evt2irq(0x0d60) },
164 static struct platform_device scif6_device = {
168 .platform_data = &scif6_platform_data,
173 static struct sh_timer_config cmt2_platform_data = {
175 .channel_offset = 0x40,
177 .clockevent_rating = 125,
178 .clocksource_rating = 125,
181 static struct resource cmt2_resources[] = {
186 .flags = IORESOURCE_MEM,
189 .start = evt2irq(0x0b80), /* CMT2 */
190 .flags = IORESOURCE_IRQ,
194 static struct platform_device cmt2_device = {
198 .platform_data = &cmt2_platform_data,
200 .resource = cmt2_resources,
201 .num_resources = ARRAY_SIZE(cmt2_resources),
205 static struct sh_timer_config tmu00_platform_data = {
207 .channel_offset = 0x4,
209 .clockevent_rating = 200,
212 static struct resource tmu00_resources[] = {
217 .flags = IORESOURCE_MEM,
220 .start = intcs_evt2irq(0xe80), /* TMU_TUNI0 */
221 .flags = IORESOURCE_IRQ,
225 static struct platform_device tmu00_device = {
229 .platform_data = &tmu00_platform_data,
231 .resource = tmu00_resources,
232 .num_resources = ARRAY_SIZE(tmu00_resources),
235 static struct sh_timer_config tmu01_platform_data = {
237 .channel_offset = 0x10,
239 .clocksource_rating = 200,
242 static struct resource tmu01_resources[] = {
247 .flags = IORESOURCE_MEM,
250 .start = intcs_evt2irq(0xea0), /* TMU_TUNI1 */
251 .flags = IORESOURCE_IRQ,
255 static struct platform_device tmu01_device = {
259 .platform_data = &tmu01_platform_data,
261 .resource = tmu01_resources,
262 .num_resources = ARRAY_SIZE(tmu01_resources),
266 static struct resource iic0_resources[] = {
270 .end = 0xFFF20425 - 1,
271 .flags = IORESOURCE_MEM,
274 .start = intcs_evt2irq(0xe00), /* IIC0_ALI0 */
275 .end = intcs_evt2irq(0xe60), /* IIC0_DTEI0 */
276 .flags = IORESOURCE_IRQ,
280 static struct platform_device iic0_device = {
281 .name = "i2c-sh_mobile",
282 .id = 0, /* "i2c0" clock */
283 .num_resources = ARRAY_SIZE(iic0_resources),
284 .resource = iic0_resources,
287 static struct resource iic1_resources[] = {
291 .end = 0xE6C20425 - 1,
292 .flags = IORESOURCE_MEM,
295 .start = evt2irq(0x780), /* IIC1_ALI1 */
296 .end = evt2irq(0x7e0), /* IIC1_DTEI1 */
297 .flags = IORESOURCE_IRQ,
301 static struct platform_device iic1_device = {
302 .name = "i2c-sh_mobile",
303 .id = 1, /* "i2c1" clock */
304 .num_resources = ARRAY_SIZE(iic1_resources),
305 .resource = iic1_resources,
309 /* Transmit sizes and respective CHCR register values */
320 /* log2(size / 8) - used to calculate number of transfers */
322 [XMIT_SZ_8BIT] = 0, \
323 [XMIT_SZ_16BIT] = 1, \
324 [XMIT_SZ_32BIT] = 2, \
325 [XMIT_SZ_64BIT] = 3, \
326 [XMIT_SZ_128BIT] = 4, \
327 [XMIT_SZ_256BIT] = 5, \
328 [XMIT_SZ_512BIT] = 6, \
331 #define TS_INDEX2VAL(i) ((((i) & 3) << 3) | \
332 (((i) & 0xc) << (20 - 2)))
334 static const struct sh_dmae_slave_config sh7372_dmae_slaves[] = {
336 .slave_id = SHDMA_SLAVE_SCIF0_TX,
338 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
341 .slave_id = SHDMA_SLAVE_SCIF0_RX,
343 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
346 .slave_id = SHDMA_SLAVE_SCIF1_TX,
348 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
351 .slave_id = SHDMA_SLAVE_SCIF1_RX,
353 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
356 .slave_id = SHDMA_SLAVE_SCIF2_TX,
358 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
361 .slave_id = SHDMA_SLAVE_SCIF2_RX,
363 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
366 .slave_id = SHDMA_SLAVE_SCIF3_TX,
368 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
371 .slave_id = SHDMA_SLAVE_SCIF3_RX,
373 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
376 .slave_id = SHDMA_SLAVE_SCIF4_TX,
378 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
381 .slave_id = SHDMA_SLAVE_SCIF4_RX,
383 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
386 .slave_id = SHDMA_SLAVE_SCIF5_TX,
388 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
391 .slave_id = SHDMA_SLAVE_SCIF5_RX,
393 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
396 .slave_id = SHDMA_SLAVE_SCIF6_TX,
398 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
401 .slave_id = SHDMA_SLAVE_SCIF6_RX,
403 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
406 .slave_id = SHDMA_SLAVE_SDHI0_TX,
408 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_16BIT),
411 .slave_id = SHDMA_SLAVE_SDHI0_RX,
413 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_16BIT),
416 .slave_id = SHDMA_SLAVE_SDHI1_TX,
418 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_16BIT),
421 .slave_id = SHDMA_SLAVE_SDHI1_RX,
423 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_16BIT),
426 .slave_id = SHDMA_SLAVE_SDHI2_TX,
428 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_16BIT),
431 .slave_id = SHDMA_SLAVE_SDHI2_RX,
433 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_16BIT),
436 .slave_id = SHDMA_SLAVE_MMCIF_TX,
438 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_32BIT),
441 .slave_id = SHDMA_SLAVE_MMCIF_RX,
443 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_32BIT),
448 #define SH7372_CHCLR 0x220
450 static const struct sh_dmae_channel sh7372_dmae_channels[] = {
455 .chclr_offset = SH7372_CHCLR + 0,
460 .chclr_offset = SH7372_CHCLR + 0x10,
465 .chclr_offset = SH7372_CHCLR + 0x20,
470 .chclr_offset = SH7372_CHCLR + 0x30,
475 .chclr_offset = SH7372_CHCLR + 0x50,
480 .chclr_offset = SH7372_CHCLR + 0x60,
484 static const unsigned int ts_shift[] = TS_SHIFT;
486 static struct sh_dmae_pdata dma_platform_data = {
487 .slave = sh7372_dmae_slaves,
488 .slave_num = ARRAY_SIZE(sh7372_dmae_slaves),
489 .channel = sh7372_dmae_channels,
490 .channel_num = ARRAY_SIZE(sh7372_dmae_channels),
493 .ts_high_shift = (20 - 2), /* 2 bits for shifted low TS */
494 .ts_high_mask = 0x00300000,
495 .ts_shift = ts_shift,
496 .ts_shift_num = ARRAY_SIZE(ts_shift),
497 .dmaor_init = DMAOR_DME,
501 /* Resource order important! */
502 static struct resource sh7372_dmae0_resources[] = {
504 /* Channel registers and DMAOR */
507 .flags = IORESOURCE_MEM,
513 .flags = IORESOURCE_MEM,
517 .start = evt2irq(0x20c0),
518 .end = evt2irq(0x20c0),
519 .flags = IORESOURCE_IRQ,
522 /* IRQ for channels 0-5 */
523 .start = evt2irq(0x2000),
524 .end = evt2irq(0x20a0),
525 .flags = IORESOURCE_IRQ,
529 /* Resource order important! */
530 static struct resource sh7372_dmae1_resources[] = {
532 /* Channel registers and DMAOR */
535 .flags = IORESOURCE_MEM,
541 .flags = IORESOURCE_MEM,
545 .start = evt2irq(0x21c0),
546 .end = evt2irq(0x21c0),
547 .flags = IORESOURCE_IRQ,
550 /* IRQ for channels 0-5 */
551 .start = evt2irq(0x2100),
552 .end = evt2irq(0x21a0),
553 .flags = IORESOURCE_IRQ,
557 /* Resource order important! */
558 static struct resource sh7372_dmae2_resources[] = {
560 /* Channel registers and DMAOR */
563 .flags = IORESOURCE_MEM,
569 .flags = IORESOURCE_MEM,
573 .start = evt2irq(0x22c0),
574 .end = evt2irq(0x22c0),
575 .flags = IORESOURCE_IRQ,
578 /* IRQ for channels 0-5 */
579 .start = evt2irq(0x2200),
580 .end = evt2irq(0x22a0),
581 .flags = IORESOURCE_IRQ,
585 static struct platform_device dma0_device = {
586 .name = "sh-dma-engine",
588 .resource = sh7372_dmae0_resources,
589 .num_resources = ARRAY_SIZE(sh7372_dmae0_resources),
591 .platform_data = &dma_platform_data,
595 static struct platform_device dma1_device = {
596 .name = "sh-dma-engine",
598 .resource = sh7372_dmae1_resources,
599 .num_resources = ARRAY_SIZE(sh7372_dmae1_resources),
601 .platform_data = &dma_platform_data,
605 static struct platform_device dma2_device = {
606 .name = "sh-dma-engine",
608 .resource = sh7372_dmae2_resources,
609 .num_resources = ARRAY_SIZE(sh7372_dmae2_resources),
611 .platform_data = &dma_platform_data,
619 unsigned int usbts_shift[] = {3, 4, 5};
627 #define USBTS_INDEX2VAL(i) (((i) & 3) << 6)
629 static const struct sh_dmae_channel sh7372_usb_dmae_channels[] = {
638 static const struct sh_dmae_slave_config sh7372_usb_dmae0_slaves[] = {
640 .slave_id = SHDMA_SLAVE_USB0_TX,
641 .chcr = USBTS_INDEX2VAL(XMIT_SZ_8BYTE),
643 .slave_id = SHDMA_SLAVE_USB0_RX,
644 .chcr = USBTS_INDEX2VAL(XMIT_SZ_8BYTE),
648 static struct sh_dmae_pdata usb_dma0_platform_data = {
649 .slave = sh7372_usb_dmae0_slaves,
650 .slave_num = ARRAY_SIZE(sh7372_usb_dmae0_slaves),
651 .channel = sh7372_usb_dmae_channels,
652 .channel_num = ARRAY_SIZE(sh7372_usb_dmae_channels),
657 .ts_shift = usbts_shift,
658 .ts_shift_num = ARRAY_SIZE(usbts_shift),
659 .dmaor_init = DMAOR_DME,
661 .chcr_ie_bit = 1 << 5,
668 static struct resource sh7372_usb_dmae0_resources[] = {
670 /* Channel registers and DMAOR */
672 .end = 0xe68a0064 - 1,
673 .flags = IORESOURCE_MEM,
678 .end = 0xe68a0014 - 1,
679 .flags = IORESOURCE_MEM,
682 /* IRQ for channels */
683 .start = evt2irq(0x0a00),
684 .end = evt2irq(0x0a00),
685 .flags = IORESOURCE_IRQ,
689 static struct platform_device usb_dma0_device = {
690 .name = "sh-dma-engine",
692 .resource = sh7372_usb_dmae0_resources,
693 .num_resources = ARRAY_SIZE(sh7372_usb_dmae0_resources),
695 .platform_data = &usb_dma0_platform_data,
700 static const struct sh_dmae_slave_config sh7372_usb_dmae1_slaves[] = {
702 .slave_id = SHDMA_SLAVE_USB1_TX,
703 .chcr = USBTS_INDEX2VAL(XMIT_SZ_8BYTE),
705 .slave_id = SHDMA_SLAVE_USB1_RX,
706 .chcr = USBTS_INDEX2VAL(XMIT_SZ_8BYTE),
710 static struct sh_dmae_pdata usb_dma1_platform_data = {
711 .slave = sh7372_usb_dmae1_slaves,
712 .slave_num = ARRAY_SIZE(sh7372_usb_dmae1_slaves),
713 .channel = sh7372_usb_dmae_channels,
714 .channel_num = ARRAY_SIZE(sh7372_usb_dmae_channels),
719 .ts_shift = usbts_shift,
720 .ts_shift_num = ARRAY_SIZE(usbts_shift),
721 .dmaor_init = DMAOR_DME,
723 .chcr_ie_bit = 1 << 5,
730 static struct resource sh7372_usb_dmae1_resources[] = {
732 /* Channel registers and DMAOR */
734 .end = 0xe68c0064 - 1,
735 .flags = IORESOURCE_MEM,
740 .end = 0xe68c0014 - 1,
741 .flags = IORESOURCE_MEM,
744 /* IRQ for channels */
745 .start = evt2irq(0x1d00),
746 .end = evt2irq(0x1d00),
747 .flags = IORESOURCE_IRQ,
751 static struct platform_device usb_dma1_device = {
752 .name = "sh-dma-engine",
754 .resource = sh7372_usb_dmae1_resources,
755 .num_resources = ARRAY_SIZE(sh7372_usb_dmae1_resources),
757 .platform_data = &usb_dma1_platform_data,
762 static struct uio_info vpu_platform_data = {
765 .irq = intcs_evt2irq(0x980),
768 static struct resource vpu_resources[] = {
773 .flags = IORESOURCE_MEM,
777 static struct platform_device vpu_device = {
778 .name = "uio_pdrv_genirq",
781 .platform_data = &vpu_platform_data,
783 .resource = vpu_resources,
784 .num_resources = ARRAY_SIZE(vpu_resources),
788 static struct uio_info veu0_platform_data = {
791 .irq = intcs_evt2irq(0x700),
794 static struct resource veu0_resources[] = {
799 .flags = IORESOURCE_MEM,
803 static struct platform_device veu0_device = {
804 .name = "uio_pdrv_genirq",
807 .platform_data = &veu0_platform_data,
809 .resource = veu0_resources,
810 .num_resources = ARRAY_SIZE(veu0_resources),
814 static struct uio_info veu1_platform_data = {
817 .irq = intcs_evt2irq(0x720),
820 static struct resource veu1_resources[] = {
825 .flags = IORESOURCE_MEM,
829 static struct platform_device veu1_device = {
830 .name = "uio_pdrv_genirq",
833 .platform_data = &veu1_platform_data,
835 .resource = veu1_resources,
836 .num_resources = ARRAY_SIZE(veu1_resources),
840 static struct uio_info veu2_platform_data = {
843 .irq = intcs_evt2irq(0x740),
846 static struct resource veu2_resources[] = {
851 .flags = IORESOURCE_MEM,
855 static struct platform_device veu2_device = {
856 .name = "uio_pdrv_genirq",
859 .platform_data = &veu2_platform_data,
861 .resource = veu2_resources,
862 .num_resources = ARRAY_SIZE(veu2_resources),
866 static struct uio_info veu3_platform_data = {
869 .irq = intcs_evt2irq(0x760),
872 static struct resource veu3_resources[] = {
877 .flags = IORESOURCE_MEM,
881 static struct platform_device veu3_device = {
882 .name = "uio_pdrv_genirq",
885 .platform_data = &veu3_platform_data,
887 .resource = veu3_resources,
888 .num_resources = ARRAY_SIZE(veu3_resources),
892 static struct uio_info jpu_platform_data = {
895 .irq = intcs_evt2irq(0x560),
898 static struct resource jpu_resources[] = {
903 .flags = IORESOURCE_MEM,
907 static struct platform_device jpu_device = {
908 .name = "uio_pdrv_genirq",
911 .platform_data = &jpu_platform_data,
913 .resource = jpu_resources,
914 .num_resources = ARRAY_SIZE(jpu_resources),
918 static struct uio_info spu0_platform_data = {
921 .irq = evt2irq(0x1800),
924 static struct resource spu0_resources[] = {
929 .flags = IORESOURCE_MEM,
933 static struct platform_device spu0_device = {
934 .name = "uio_pdrv_genirq",
937 .platform_data = &spu0_platform_data,
939 .resource = spu0_resources,
940 .num_resources = ARRAY_SIZE(spu0_resources),
944 static struct uio_info spu1_platform_data = {
947 .irq = evt2irq(0x1820),
950 static struct resource spu1_resources[] = {
955 .flags = IORESOURCE_MEM,
959 static struct platform_device spu1_device = {
960 .name = "uio_pdrv_genirq",
963 .platform_data = &spu1_platform_data,
965 .resource = spu1_resources,
966 .num_resources = ARRAY_SIZE(spu1_resources),
969 static struct platform_device *sh7372_early_devices[] __initdata = {
982 static struct platform_device *sh7372_late_devices[] __initdata = {
1000 void __init sh7372_add_standard_devices(void)
1002 sh7372_init_pm_domain(&sh7372_a4lc);
1003 sh7372_init_pm_domain(&sh7372_a4mp);
1004 sh7372_init_pm_domain(&sh7372_d4);
1005 sh7372_init_pm_domain(&sh7372_a4r);
1006 sh7372_init_pm_domain(&sh7372_a3rv);
1007 sh7372_init_pm_domain(&sh7372_a3ri);
1008 sh7372_init_pm_domain(&sh7372_a4s);
1009 sh7372_init_pm_domain(&sh7372_a3sp);
1010 sh7372_init_pm_domain(&sh7372_a3sg);
1012 sh7372_pm_add_subdomain(&sh7372_a4lc, &sh7372_a3rv);
1013 sh7372_pm_add_subdomain(&sh7372_a4r, &sh7372_a4lc);
1015 sh7372_pm_add_subdomain(&sh7372_a4s, &sh7372_a3sg);
1016 sh7372_pm_add_subdomain(&sh7372_a4s, &sh7372_a3sp);
1018 platform_add_devices(sh7372_early_devices,
1019 ARRAY_SIZE(sh7372_early_devices));
1021 platform_add_devices(sh7372_late_devices,
1022 ARRAY_SIZE(sh7372_late_devices));
1024 sh7372_add_device_to_domain(&sh7372_a3rv, &vpu_device);
1025 sh7372_add_device_to_domain(&sh7372_a4mp, &spu0_device);
1026 sh7372_add_device_to_domain(&sh7372_a4mp, &spu1_device);
1027 sh7372_add_device_to_domain(&sh7372_a3sp, &scif0_device);
1028 sh7372_add_device_to_domain(&sh7372_a3sp, &scif1_device);
1029 sh7372_add_device_to_domain(&sh7372_a3sp, &scif2_device);
1030 sh7372_add_device_to_domain(&sh7372_a3sp, &scif3_device);
1031 sh7372_add_device_to_domain(&sh7372_a3sp, &scif4_device);
1032 sh7372_add_device_to_domain(&sh7372_a3sp, &scif5_device);
1033 sh7372_add_device_to_domain(&sh7372_a3sp, &scif6_device);
1034 sh7372_add_device_to_domain(&sh7372_a3sp, &iic1_device);
1035 sh7372_add_device_to_domain(&sh7372_a3sp, &dma0_device);
1036 sh7372_add_device_to_domain(&sh7372_a3sp, &dma1_device);
1037 sh7372_add_device_to_domain(&sh7372_a3sp, &dma2_device);
1038 sh7372_add_device_to_domain(&sh7372_a3sp, &usb_dma0_device);
1039 sh7372_add_device_to_domain(&sh7372_a3sp, &usb_dma1_device);
1040 sh7372_add_device_to_domain(&sh7372_a4r, &iic0_device);
1041 sh7372_add_device_to_domain(&sh7372_a4r, &veu0_device);
1042 sh7372_add_device_to_domain(&sh7372_a4r, &veu1_device);
1043 sh7372_add_device_to_domain(&sh7372_a4r, &veu2_device);
1044 sh7372_add_device_to_domain(&sh7372_a4r, &veu3_device);
1045 sh7372_add_device_to_domain(&sh7372_a4r, &jpu_device);
1046 sh7372_add_device_to_domain(&sh7372_a4r, &tmu00_device);
1047 sh7372_add_device_to_domain(&sh7372_a4r, &tmu01_device);
1050 void __init sh7372_add_early_devices(void)
1052 early_platform_add_devices(sh7372_early_devices,
1053 ARRAY_SIZE(sh7372_early_devices));