2 * sh7372 processor support
4 * Copyright (C) 2010 Magnus Damm
5 * Copyright (C) 2008 Yoshihiro Shimoda
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 #include <linux/kernel.h>
21 #include <linux/init.h>
22 #include <linux/interrupt.h>
23 #include <linux/irq.h>
24 #include <linux/platform_device.h>
25 #include <linux/of_platform.h>
26 #include <linux/uio_driver.h>
27 #include <linux/delay.h>
28 #include <linux/input.h>
30 #include <linux/serial_sci.h>
31 #include <linux/sh_dma.h>
32 #include <linux/sh_intc.h>
33 #include <linux/sh_timer.h>
34 #include <linux/pm_domain.h>
35 #include <linux/dma-mapping.h>
36 #include <mach/dma-register.h>
37 #include <mach/hardware.h>
38 #include <mach/irqs.h>
39 #include <mach/sh7372.h>
40 #include <mach/common.h>
41 #include <asm/mach/map.h>
42 #include <asm/mach-types.h>
43 #include <asm/mach/arch.h>
44 #include <asm/mach/time.h>
46 static struct map_desc sh7372_io_desc[] __initdata = {
47 /* create a 1:1 entity map for 0xe6xxxxxx
48 * used by CPGA, INTC and PFC.
51 .virtual = 0xe6000000,
52 .pfn = __phys_to_pfn(0xe6000000),
54 .type = MT_DEVICE_NONSHARED
58 void __init sh7372_map_io(void)
60 iotable_init(sh7372_io_desc, ARRAY_SIZE(sh7372_io_desc));
64 static struct plat_sci_port scif0_platform_data = {
65 .mapbase = 0xe6c40000,
66 .flags = UPF_BOOT_AUTOCONF,
67 .scscr = SCSCR_RE | SCSCR_TE,
68 .scbrr_algo_id = SCBRR_ALGO_4,
70 .irqs = { evt2irq(0x0c00), evt2irq(0x0c00),
71 evt2irq(0x0c00), evt2irq(0x0c00) },
74 static struct platform_device scif0_device = {
78 .platform_data = &scif0_platform_data,
83 static struct plat_sci_port scif1_platform_data = {
84 .mapbase = 0xe6c50000,
85 .flags = UPF_BOOT_AUTOCONF,
86 .scscr = SCSCR_RE | SCSCR_TE,
87 .scbrr_algo_id = SCBRR_ALGO_4,
89 .irqs = { evt2irq(0x0c20), evt2irq(0x0c20),
90 evt2irq(0x0c20), evt2irq(0x0c20) },
93 static struct platform_device scif1_device = {
97 .platform_data = &scif1_platform_data,
102 static struct plat_sci_port scif2_platform_data = {
103 .mapbase = 0xe6c60000,
104 .flags = UPF_BOOT_AUTOCONF,
105 .scscr = SCSCR_RE | SCSCR_TE,
106 .scbrr_algo_id = SCBRR_ALGO_4,
108 .irqs = { evt2irq(0x0c40), evt2irq(0x0c40),
109 evt2irq(0x0c40), evt2irq(0x0c40) },
112 static struct platform_device scif2_device = {
116 .platform_data = &scif2_platform_data,
121 static struct plat_sci_port scif3_platform_data = {
122 .mapbase = 0xe6c70000,
123 .flags = UPF_BOOT_AUTOCONF,
124 .scscr = SCSCR_RE | SCSCR_TE,
125 .scbrr_algo_id = SCBRR_ALGO_4,
127 .irqs = { evt2irq(0x0c60), evt2irq(0x0c60),
128 evt2irq(0x0c60), evt2irq(0x0c60) },
131 static struct platform_device scif3_device = {
135 .platform_data = &scif3_platform_data,
140 static struct plat_sci_port scif4_platform_data = {
141 .mapbase = 0xe6c80000,
142 .flags = UPF_BOOT_AUTOCONF,
143 .scscr = SCSCR_RE | SCSCR_TE,
144 .scbrr_algo_id = SCBRR_ALGO_4,
146 .irqs = { evt2irq(0x0d20), evt2irq(0x0d20),
147 evt2irq(0x0d20), evt2irq(0x0d20) },
150 static struct platform_device scif4_device = {
154 .platform_data = &scif4_platform_data,
159 static struct plat_sci_port scif5_platform_data = {
160 .mapbase = 0xe6cb0000,
161 .flags = UPF_BOOT_AUTOCONF,
162 .scscr = SCSCR_RE | SCSCR_TE,
163 .scbrr_algo_id = SCBRR_ALGO_4,
165 .irqs = { evt2irq(0x0d40), evt2irq(0x0d40),
166 evt2irq(0x0d40), evt2irq(0x0d40) },
169 static struct platform_device scif5_device = {
173 .platform_data = &scif5_platform_data,
178 static struct plat_sci_port scif6_platform_data = {
179 .mapbase = 0xe6c30000,
180 .flags = UPF_BOOT_AUTOCONF,
181 .scscr = SCSCR_RE | SCSCR_TE,
182 .scbrr_algo_id = SCBRR_ALGO_4,
184 .irqs = { evt2irq(0x0d60), evt2irq(0x0d60),
185 evt2irq(0x0d60), evt2irq(0x0d60) },
188 static struct platform_device scif6_device = {
192 .platform_data = &scif6_platform_data,
197 static struct sh_timer_config cmt2_platform_data = {
199 .channel_offset = 0x40,
201 .clockevent_rating = 125,
202 .clocksource_rating = 125,
205 static struct resource cmt2_resources[] = {
210 .flags = IORESOURCE_MEM,
213 .start = evt2irq(0x0b80), /* CMT2 */
214 .flags = IORESOURCE_IRQ,
218 static struct platform_device cmt2_device = {
222 .platform_data = &cmt2_platform_data,
224 .resource = cmt2_resources,
225 .num_resources = ARRAY_SIZE(cmt2_resources),
229 static struct sh_timer_config tmu00_platform_data = {
231 .channel_offset = 0x4,
233 .clockevent_rating = 200,
236 static struct resource tmu00_resources[] = {
241 .flags = IORESOURCE_MEM,
244 .start = intcs_evt2irq(0xe80), /* TMU_TUNI0 */
245 .flags = IORESOURCE_IRQ,
249 static struct platform_device tmu00_device = {
253 .platform_data = &tmu00_platform_data,
255 .resource = tmu00_resources,
256 .num_resources = ARRAY_SIZE(tmu00_resources),
259 static struct sh_timer_config tmu01_platform_data = {
261 .channel_offset = 0x10,
263 .clocksource_rating = 200,
266 static struct resource tmu01_resources[] = {
271 .flags = IORESOURCE_MEM,
274 .start = intcs_evt2irq(0xea0), /* TMU_TUNI1 */
275 .flags = IORESOURCE_IRQ,
279 static struct platform_device tmu01_device = {
283 .platform_data = &tmu01_platform_data,
285 .resource = tmu01_resources,
286 .num_resources = ARRAY_SIZE(tmu01_resources),
290 static struct resource iic0_resources[] = {
294 .end = 0xFFF20425 - 1,
295 .flags = IORESOURCE_MEM,
298 .start = intcs_evt2irq(0xe00), /* IIC0_ALI0 */
299 .end = intcs_evt2irq(0xe60), /* IIC0_DTEI0 */
300 .flags = IORESOURCE_IRQ,
304 static struct platform_device iic0_device = {
305 .name = "i2c-sh_mobile",
306 .id = 0, /* "i2c0" clock */
307 .num_resources = ARRAY_SIZE(iic0_resources),
308 .resource = iic0_resources,
311 static struct resource iic1_resources[] = {
315 .end = 0xE6C20425 - 1,
316 .flags = IORESOURCE_MEM,
319 .start = evt2irq(0x780), /* IIC1_ALI1 */
320 .end = evt2irq(0x7e0), /* IIC1_DTEI1 */
321 .flags = IORESOURCE_IRQ,
325 static struct platform_device iic1_device = {
326 .name = "i2c-sh_mobile",
327 .id = 1, /* "i2c1" clock */
328 .num_resources = ARRAY_SIZE(iic1_resources),
329 .resource = iic1_resources,
333 static const struct sh_dmae_slave_config sh7372_dmae_slaves[] = {
335 .slave_id = SHDMA_SLAVE_SCIF0_TX,
337 .chcr = CHCR_TX(XMIT_SZ_8BIT),
340 .slave_id = SHDMA_SLAVE_SCIF0_RX,
342 .chcr = CHCR_RX(XMIT_SZ_8BIT),
345 .slave_id = SHDMA_SLAVE_SCIF1_TX,
347 .chcr = CHCR_TX(XMIT_SZ_8BIT),
350 .slave_id = SHDMA_SLAVE_SCIF1_RX,
352 .chcr = CHCR_RX(XMIT_SZ_8BIT),
355 .slave_id = SHDMA_SLAVE_SCIF2_TX,
357 .chcr = CHCR_TX(XMIT_SZ_8BIT),
360 .slave_id = SHDMA_SLAVE_SCIF2_RX,
362 .chcr = CHCR_RX(XMIT_SZ_8BIT),
365 .slave_id = SHDMA_SLAVE_SCIF3_TX,
367 .chcr = CHCR_TX(XMIT_SZ_8BIT),
370 .slave_id = SHDMA_SLAVE_SCIF3_RX,
372 .chcr = CHCR_RX(XMIT_SZ_8BIT),
375 .slave_id = SHDMA_SLAVE_SCIF4_TX,
377 .chcr = CHCR_TX(XMIT_SZ_8BIT),
380 .slave_id = SHDMA_SLAVE_SCIF4_RX,
382 .chcr = CHCR_RX(XMIT_SZ_8BIT),
385 .slave_id = SHDMA_SLAVE_SCIF5_TX,
387 .chcr = CHCR_TX(XMIT_SZ_8BIT),
390 .slave_id = SHDMA_SLAVE_SCIF5_RX,
392 .chcr = CHCR_RX(XMIT_SZ_8BIT),
395 .slave_id = SHDMA_SLAVE_SCIF6_TX,
397 .chcr = CHCR_TX(XMIT_SZ_8BIT),
400 .slave_id = SHDMA_SLAVE_SCIF6_RX,
402 .chcr = CHCR_RX(XMIT_SZ_8BIT),
405 .slave_id = SHDMA_SLAVE_FLCTL0_TX,
407 .chcr = CHCR_TX(XMIT_SZ_32BIT),
410 .slave_id = SHDMA_SLAVE_FLCTL0_RX,
412 .chcr = CHCR_RX(XMIT_SZ_32BIT),
415 .slave_id = SHDMA_SLAVE_FLCTL1_TX,
417 .chcr = CHCR_TX(XMIT_SZ_32BIT),
420 .slave_id = SHDMA_SLAVE_FLCTL1_RX,
422 .chcr = CHCR_RX(XMIT_SZ_32BIT),
425 .slave_id = SHDMA_SLAVE_SDHI0_TX,
427 .chcr = CHCR_TX(XMIT_SZ_16BIT),
430 .slave_id = SHDMA_SLAVE_SDHI0_RX,
432 .chcr = CHCR_RX(XMIT_SZ_16BIT),
435 .slave_id = SHDMA_SLAVE_SDHI1_TX,
437 .chcr = CHCR_TX(XMIT_SZ_16BIT),
440 .slave_id = SHDMA_SLAVE_SDHI1_RX,
442 .chcr = CHCR_RX(XMIT_SZ_16BIT),
445 .slave_id = SHDMA_SLAVE_SDHI2_TX,
447 .chcr = CHCR_TX(XMIT_SZ_16BIT),
450 .slave_id = SHDMA_SLAVE_SDHI2_RX,
452 .chcr = CHCR_RX(XMIT_SZ_16BIT),
455 .slave_id = SHDMA_SLAVE_FSIA_TX,
457 .chcr = CHCR_TX(XMIT_SZ_32BIT),
460 .slave_id = SHDMA_SLAVE_FSIA_RX,
462 .chcr = CHCR_RX(XMIT_SZ_32BIT),
465 .slave_id = SHDMA_SLAVE_MMCIF_TX,
467 .chcr = CHCR_TX(XMIT_SZ_32BIT),
470 .slave_id = SHDMA_SLAVE_MMCIF_RX,
472 .chcr = CHCR_RX(XMIT_SZ_32BIT),
477 #define SH7372_CHCLR (0x220 - 0x20)
479 static const struct sh_dmae_channel sh7372_dmae_channels[] = {
484 .chclr_offset = SH7372_CHCLR + 0,
489 .chclr_offset = SH7372_CHCLR + 0x10,
494 .chclr_offset = SH7372_CHCLR + 0x20,
499 .chclr_offset = SH7372_CHCLR + 0x30,
504 .chclr_offset = SH7372_CHCLR + 0x50,
509 .chclr_offset = SH7372_CHCLR + 0x60,
513 static struct sh_dmae_pdata dma_platform_data = {
514 .slave = sh7372_dmae_slaves,
515 .slave_num = ARRAY_SIZE(sh7372_dmae_slaves),
516 .channel = sh7372_dmae_channels,
517 .channel_num = ARRAY_SIZE(sh7372_dmae_channels),
518 .ts_low_shift = TS_LOW_SHIFT,
519 .ts_low_mask = TS_LOW_BIT << TS_LOW_SHIFT,
520 .ts_high_shift = TS_HI_SHIFT,
521 .ts_high_mask = TS_HI_BIT << TS_HI_SHIFT,
522 .ts_shift = dma_ts_shift,
523 .ts_shift_num = ARRAY_SIZE(dma_ts_shift),
524 .dmaor_init = DMAOR_DME,
528 /* Resource order important! */
529 static struct resource sh7372_dmae0_resources[] = {
531 /* Channel registers and DMAOR */
534 .flags = IORESOURCE_MEM,
540 .flags = IORESOURCE_MEM,
544 .start = evt2irq(0x20c0),
545 .end = evt2irq(0x20c0),
546 .flags = IORESOURCE_IRQ,
549 /* IRQ for channels 0-5 */
550 .start = evt2irq(0x2000),
551 .end = evt2irq(0x20a0),
552 .flags = IORESOURCE_IRQ,
556 /* Resource order important! */
557 static struct resource sh7372_dmae1_resources[] = {
559 /* Channel registers and DMAOR */
562 .flags = IORESOURCE_MEM,
568 .flags = IORESOURCE_MEM,
572 .start = evt2irq(0x21c0),
573 .end = evt2irq(0x21c0),
574 .flags = IORESOURCE_IRQ,
577 /* IRQ for channels 0-5 */
578 .start = evt2irq(0x2100),
579 .end = evt2irq(0x21a0),
580 .flags = IORESOURCE_IRQ,
584 /* Resource order important! */
585 static struct resource sh7372_dmae2_resources[] = {
587 /* Channel registers and DMAOR */
590 .flags = IORESOURCE_MEM,
596 .flags = IORESOURCE_MEM,
600 .start = evt2irq(0x22c0),
601 .end = evt2irq(0x22c0),
602 .flags = IORESOURCE_IRQ,
605 /* IRQ for channels 0-5 */
606 .start = evt2irq(0x2200),
607 .end = evt2irq(0x22a0),
608 .flags = IORESOURCE_IRQ,
612 static struct platform_device dma0_device = {
613 .name = "sh-dma-engine",
615 .resource = sh7372_dmae0_resources,
616 .num_resources = ARRAY_SIZE(sh7372_dmae0_resources),
618 .platform_data = &dma_platform_data,
622 static struct platform_device dma1_device = {
623 .name = "sh-dma-engine",
625 .resource = sh7372_dmae1_resources,
626 .num_resources = ARRAY_SIZE(sh7372_dmae1_resources),
628 .platform_data = &dma_platform_data,
632 static struct platform_device dma2_device = {
633 .name = "sh-dma-engine",
635 .resource = sh7372_dmae2_resources,
636 .num_resources = ARRAY_SIZE(sh7372_dmae2_resources),
638 .platform_data = &dma_platform_data,
645 static const struct sh_dmae_channel sh7372_usb_dmae_channels[] = {
654 static const struct sh_dmae_slave_config sh7372_usb_dmae0_slaves[] = {
656 .slave_id = SHDMA_SLAVE_USB0_TX,
657 .chcr = USBTS_INDEX2VAL(USBTS_XMIT_SZ_8BYTE),
659 .slave_id = SHDMA_SLAVE_USB0_RX,
660 .chcr = USBTS_INDEX2VAL(USBTS_XMIT_SZ_8BYTE),
664 static struct sh_dmae_pdata usb_dma0_platform_data = {
665 .slave = sh7372_usb_dmae0_slaves,
666 .slave_num = ARRAY_SIZE(sh7372_usb_dmae0_slaves),
667 .channel = sh7372_usb_dmae_channels,
668 .channel_num = ARRAY_SIZE(sh7372_usb_dmae_channels),
669 .ts_low_shift = USBTS_LOW_SHIFT,
670 .ts_low_mask = USBTS_LOW_BIT << USBTS_LOW_SHIFT,
671 .ts_high_shift = USBTS_HI_SHIFT,
672 .ts_high_mask = USBTS_HI_BIT << USBTS_HI_SHIFT,
673 .ts_shift = dma_usbts_shift,
674 .ts_shift_num = ARRAY_SIZE(dma_usbts_shift),
675 .dmaor_init = DMAOR_DME,
677 .chcr_ie_bit = 1 << 5,
684 static struct resource sh7372_usb_dmae0_resources[] = {
686 /* Channel registers and DMAOR */
688 .end = 0xe68a0064 - 1,
689 .flags = IORESOURCE_MEM,
694 .end = 0xe68a0014 - 1,
695 .flags = IORESOURCE_MEM,
698 /* IRQ for channels */
699 .start = evt2irq(0x0a00),
700 .end = evt2irq(0x0a00),
701 .flags = IORESOURCE_IRQ,
705 static struct platform_device usb_dma0_device = {
706 .name = "sh-dma-engine",
708 .resource = sh7372_usb_dmae0_resources,
709 .num_resources = ARRAY_SIZE(sh7372_usb_dmae0_resources),
711 .platform_data = &usb_dma0_platform_data,
716 static const struct sh_dmae_slave_config sh7372_usb_dmae1_slaves[] = {
718 .slave_id = SHDMA_SLAVE_USB1_TX,
719 .chcr = USBTS_INDEX2VAL(USBTS_XMIT_SZ_8BYTE),
721 .slave_id = SHDMA_SLAVE_USB1_RX,
722 .chcr = USBTS_INDEX2VAL(USBTS_XMIT_SZ_8BYTE),
726 static struct sh_dmae_pdata usb_dma1_platform_data = {
727 .slave = sh7372_usb_dmae1_slaves,
728 .slave_num = ARRAY_SIZE(sh7372_usb_dmae1_slaves),
729 .channel = sh7372_usb_dmae_channels,
730 .channel_num = ARRAY_SIZE(sh7372_usb_dmae_channels),
731 .ts_low_shift = USBTS_LOW_SHIFT,
732 .ts_low_mask = USBTS_LOW_BIT << USBTS_LOW_SHIFT,
733 .ts_high_shift = USBTS_HI_SHIFT,
734 .ts_high_mask = USBTS_HI_BIT << USBTS_HI_SHIFT,
735 .ts_shift = dma_usbts_shift,
736 .ts_shift_num = ARRAY_SIZE(dma_usbts_shift),
737 .dmaor_init = DMAOR_DME,
739 .chcr_ie_bit = 1 << 5,
746 static struct resource sh7372_usb_dmae1_resources[] = {
748 /* Channel registers and DMAOR */
750 .end = 0xe68c0064 - 1,
751 .flags = IORESOURCE_MEM,
756 .end = 0xe68c0014 - 1,
757 .flags = IORESOURCE_MEM,
760 /* IRQ for channels */
761 .start = evt2irq(0x1d00),
762 .end = evt2irq(0x1d00),
763 .flags = IORESOURCE_IRQ,
767 static struct platform_device usb_dma1_device = {
768 .name = "sh-dma-engine",
770 .resource = sh7372_usb_dmae1_resources,
771 .num_resources = ARRAY_SIZE(sh7372_usb_dmae1_resources),
773 .platform_data = &usb_dma1_platform_data,
778 static struct uio_info vpu_platform_data = {
781 .irq = intcs_evt2irq(0x980),
784 static struct resource vpu_resources[] = {
789 .flags = IORESOURCE_MEM,
793 static struct platform_device vpu_device = {
794 .name = "uio_pdrv_genirq",
797 .platform_data = &vpu_platform_data,
799 .resource = vpu_resources,
800 .num_resources = ARRAY_SIZE(vpu_resources),
804 static struct uio_info veu0_platform_data = {
807 .irq = intcs_evt2irq(0x700),
810 static struct resource veu0_resources[] = {
815 .flags = IORESOURCE_MEM,
819 static struct platform_device veu0_device = {
820 .name = "uio_pdrv_genirq",
823 .platform_data = &veu0_platform_data,
825 .resource = veu0_resources,
826 .num_resources = ARRAY_SIZE(veu0_resources),
830 static struct uio_info veu1_platform_data = {
833 .irq = intcs_evt2irq(0x720),
836 static struct resource veu1_resources[] = {
841 .flags = IORESOURCE_MEM,
845 static struct platform_device veu1_device = {
846 .name = "uio_pdrv_genirq",
849 .platform_data = &veu1_platform_data,
851 .resource = veu1_resources,
852 .num_resources = ARRAY_SIZE(veu1_resources),
856 static struct uio_info veu2_platform_data = {
859 .irq = intcs_evt2irq(0x740),
862 static struct resource veu2_resources[] = {
867 .flags = IORESOURCE_MEM,
871 static struct platform_device veu2_device = {
872 .name = "uio_pdrv_genirq",
875 .platform_data = &veu2_platform_data,
877 .resource = veu2_resources,
878 .num_resources = ARRAY_SIZE(veu2_resources),
882 static struct uio_info veu3_platform_data = {
885 .irq = intcs_evt2irq(0x760),
888 static struct resource veu3_resources[] = {
893 .flags = IORESOURCE_MEM,
897 static struct platform_device veu3_device = {
898 .name = "uio_pdrv_genirq",
901 .platform_data = &veu3_platform_data,
903 .resource = veu3_resources,
904 .num_resources = ARRAY_SIZE(veu3_resources),
908 static struct uio_info jpu_platform_data = {
911 .irq = intcs_evt2irq(0x560),
914 static struct resource jpu_resources[] = {
919 .flags = IORESOURCE_MEM,
923 static struct platform_device jpu_device = {
924 .name = "uio_pdrv_genirq",
927 .platform_data = &jpu_platform_data,
929 .resource = jpu_resources,
930 .num_resources = ARRAY_SIZE(jpu_resources),
934 static struct uio_info spu0_platform_data = {
937 .irq = evt2irq(0x1800),
940 static struct resource spu0_resources[] = {
945 .flags = IORESOURCE_MEM,
949 static struct platform_device spu0_device = {
950 .name = "uio_pdrv_genirq",
953 .platform_data = &spu0_platform_data,
955 .resource = spu0_resources,
956 .num_resources = ARRAY_SIZE(spu0_resources),
960 static struct uio_info spu1_platform_data = {
963 .irq = evt2irq(0x1820),
966 static struct resource spu1_resources[] = {
971 .flags = IORESOURCE_MEM,
975 static struct platform_device spu1_device = {
976 .name = "uio_pdrv_genirq",
979 .platform_data = &spu1_platform_data,
981 .resource = spu1_resources,
982 .num_resources = ARRAY_SIZE(spu1_resources),
985 static struct platform_device *sh7372_early_devices[] __initdata = {
998 static struct platform_device *sh7372_late_devices[] __initdata = {
1016 void __init sh7372_add_standard_devices(void)
1018 struct pm_domain_device domain_devices[] = {
1019 { "A3RV", &vpu_device, },
1020 { "A4MP", &spu0_device, },
1021 { "A4MP", &spu1_device, },
1022 { "A3SP", &scif0_device, },
1023 { "A3SP", &scif1_device, },
1024 { "A3SP", &scif2_device, },
1025 { "A3SP", &scif3_device, },
1026 { "A3SP", &scif4_device, },
1027 { "A3SP", &scif5_device, },
1028 { "A3SP", &scif6_device, },
1029 { "A3SP", &iic1_device, },
1030 { "A3SP", &dma0_device, },
1031 { "A3SP", &dma1_device, },
1032 { "A3SP", &dma2_device, },
1033 { "A3SP", &usb_dma0_device, },
1034 { "A3SP", &usb_dma1_device, },
1035 { "A4R", &iic0_device, },
1036 { "A4R", &veu0_device, },
1037 { "A4R", &veu1_device, },
1038 { "A4R", &veu2_device, },
1039 { "A4R", &veu3_device, },
1040 { "A4R", &jpu_device, },
1041 { "A4R", &tmu00_device, },
1042 { "A4R", &tmu01_device, },
1045 sh7372_init_pm_domains();
1047 platform_add_devices(sh7372_early_devices,
1048 ARRAY_SIZE(sh7372_early_devices));
1050 platform_add_devices(sh7372_late_devices,
1051 ARRAY_SIZE(sh7372_late_devices));
1053 rmobile_add_devices_to_domains(domain_devices,
1054 ARRAY_SIZE(domain_devices));
1057 static void __init sh7372_earlytimer_init(void)
1059 sh7372_clock_init();
1060 shmobile_earlytimer_init();
1063 void __init sh7372_add_early_devices(void)
1065 early_platform_add_devices(sh7372_early_devices,
1066 ARRAY_SIZE(sh7372_early_devices));
1068 /* setup early console here as well */
1069 shmobile_setup_console();
1071 /* override timer setup with soc-specific code */
1072 shmobile_timer.init = sh7372_earlytimer_init;
1075 #ifdef CONFIG_USE_OF
1077 void __init sh7372_add_early_devices_dt(void)
1079 shmobile_setup_delay(800, 1, 3); /* Cortex-A8 @ 800MHz */
1081 early_platform_add_devices(sh7372_early_devices,
1082 ARRAY_SIZE(sh7372_early_devices));
1084 /* setup early console here as well */
1085 shmobile_setup_console();
1088 static const struct of_dev_auxdata sh7372_auxdata_lookup[] __initconst = {
1092 void __init sh7372_add_standard_devices_dt(void)
1094 /* clocks are setup late during boot in the case of DT */
1095 sh7372_clock_init();
1097 platform_add_devices(sh7372_early_devices,
1098 ARRAY_SIZE(sh7372_early_devices));
1100 of_platform_populate(NULL, of_default_bus_match_table,
1101 sh7372_auxdata_lookup, NULL);
1104 static const char *sh7372_boards_compat_dt[] __initdata = {
1109 DT_MACHINE_START(SH7372_DT, "Generic SH7372 (Flattened Device Tree)")
1110 .map_io = sh7372_map_io,
1111 .init_early = sh7372_add_early_devices_dt,
1112 .nr_irqs = NR_IRQS_LEGACY,
1113 .init_irq = sh7372_init_irq,
1114 .handle_irq = shmobile_handle_irq_intc,
1115 .init_machine = sh7372_add_standard_devices_dt,
1116 .timer = &shmobile_timer,
1117 .dt_compat = sh7372_boards_compat_dt,
1120 #endif /* CONFIG_USE_OF */