arch/arm/mach-shmobile/setup-sh7372.c

   1 /*
   2  * sh7372 processor support
   3  *
   4  * Copyright (C) 2010  Magnus Damm
   5  * Copyright (C) 2008  Yoshihiro Shimoda
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; version 2 of the License.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software
  18  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
  19  */
  20 #include <linux/kernel.h>
  21 #include <linux/init.h>
  22 #include <linux/interrupt.h>
  23 #include <linux/irq.h>
  24 #include <linux/platform_device.h>
  25 #include <linux/of_platform.h>
  26 #include <linux/uio_driver.h>
  27 #include <linux/delay.h>
  28 #include <linux/input.h>
  29 #include <linux/io.h>
  30 #include <linux/serial_sci.h>
  31 #include <linux/sh_dma.h>
  32 #include <linux/sh_intc.h>
  33 #include <linux/sh_timer.h>
  34 #include <linux/pm_domain.h>
  35 #include <linux/dma-mapping.h>
  36 #include <linux/platform_data/sh_ipmmu.h>
  37 #include <mach/dma-register.h>
  38 #include <mach/hardware.h>
  39 #include <mach/irqs.h>
  40 #include <mach/sh7372.h>
  41 #include <mach/common.h>
  42 #include <asm/mach/map.h>
  43 #include <asm/mach-types.h>
  44 #include <asm/mach/arch.h>
  45 #include <asm/mach/time.h>
  46
  47 static struct map_desc sh7372_io_desc[] __initdata = {
  48         /* create a 1:1 entity map for 0xe6xxxxxx
  49          * used by CPGA, INTC and PFC.
  50          */
  51         {
  52                 .virtual        = 0xe6000000,
  53                 .pfn            = __phys_to_pfn(0xe6000000),
  54                 .length         = 256 << 20,
  55                 .type           = MT_DEVICE_NONSHARED
  56         },
  57 };
  58
  59 void __init sh7372_map_io(void)
  60 {
  61         iotable_init(sh7372_io_desc, ARRAY_SIZE(sh7372_io_desc));
  62 }
  63
  64 /* SCIFA0 */
  65 static struct plat_sci_port scif0_platform_data = {
  66         .mapbase        = 0xe6c40000,
  67         .flags          = UPF_BOOT_AUTOCONF,
  68         .scscr          = SCSCR_RE | SCSCR_TE,
  69         .scbrr_algo_id  = SCBRR_ALGO_4,
  70         .type           = PORT_SCIFA,
  71         .irqs           = { evt2irq(0x0c00), evt2irq(0x0c00),
  72                             evt2irq(0x0c00), evt2irq(0x0c00) },
  73 };
  74
  75 static struct platform_device scif0_device = {
  76         .name           = "sh-sci",
  77         .id             = 0,
  78         .dev            = {
  79                 .platform_data  = &scif0_platform_data,
  80         },
  81 };
  82
  83 /* SCIFA1 */
  84 static struct plat_sci_port scif1_platform_data = {
  85         .mapbase        = 0xe6c50000,
  86         .flags          = UPF_BOOT_AUTOCONF,
  87         .scscr          = SCSCR_RE | SCSCR_TE,
  88         .scbrr_algo_id  = SCBRR_ALGO_4,
  89         .type           = PORT_SCIFA,
  90         .irqs           = { evt2irq(0x0c20), evt2irq(0x0c20),
  91                             evt2irq(0x0c20), evt2irq(0x0c20) },
  92 };
  93
  94 static struct platform_device scif1_device = {
  95         .name           = "sh-sci",
  96         .id             = 1,
  97         .dev            = {
  98                 .platform_data  = &scif1_platform_data,
  99         },
 100 };
 101
 102 /* SCIFA2 */
 103 static struct plat_sci_port scif2_platform_data = {
 104         .mapbase        = 0xe6c60000,
 105         .flags          = UPF_BOOT_AUTOCONF,
 106         .scscr          = SCSCR_RE | SCSCR_TE,
 107         .scbrr_algo_id  = SCBRR_ALGO_4,
 108         .type           = PORT_SCIFA,
 109         .irqs           = { evt2irq(0x0c40), evt2irq(0x0c40),
 110                             evt2irq(0x0c40), evt2irq(0x0c40) },
 111 };
 112
 113 static struct platform_device scif2_device = {
 114         .name           = "sh-sci",
 115         .id             = 2,
 116         .dev            = {
 117                 .platform_data  = &scif2_platform_data,
 118         },
 119 };
 120
 121 /* SCIFA3 */
 122 static struct plat_sci_port scif3_platform_data = {
 123         .mapbase        = 0xe6c70000,
 124         .flags          = UPF_BOOT_AUTOCONF,
 125         .scscr          = SCSCR_RE | SCSCR_TE,
 126         .scbrr_algo_id  = SCBRR_ALGO_4,
 127         .type           = PORT_SCIFA,
 128         .irqs           = { evt2irq(0x0c60), evt2irq(0x0c60),
 129                             evt2irq(0x0c60), evt2irq(0x0c60) },
 130 };
 131
 132 static struct platform_device scif3_device = {
 133         .name           = "sh-sci",
 134         .id             = 3,
 135         .dev            = {
 136                 .platform_data  = &scif3_platform_data,
 137         },
 138 };
 139
 140 /* SCIFA4 */
 141 static struct plat_sci_port scif4_platform_data = {
 142         .mapbase        = 0xe6c80000,
 143         .flags          = UPF_BOOT_AUTOCONF,
 144         .scscr          = SCSCR_RE | SCSCR_TE,
 145         .scbrr_algo_id  = SCBRR_ALGO_4,
 146         .type           = PORT_SCIFA,
 147         .irqs           = { evt2irq(0x0d20), evt2irq(0x0d20),
 148                             evt2irq(0x0d20), evt2irq(0x0d20) },
 149 };
 150
 151 static struct platform_device scif4_device = {
 152         .name           = "sh-sci",
 153         .id             = 4,
 154         .dev            = {
 155                 .platform_data  = &scif4_platform_data,
 156         },
 157 };
 158
 159 /* SCIFA5 */
 160 static struct plat_sci_port scif5_platform_data = {
 161         .mapbase        = 0xe6cb0000,
 162         .flags          = UPF_BOOT_AUTOCONF,
 163         .scscr          = SCSCR_RE | SCSCR_TE,
 164         .scbrr_algo_id  = SCBRR_ALGO_4,
 165         .type           = PORT_SCIFA,
 166         .irqs           = { evt2irq(0x0d40), evt2irq(0x0d40),
 167                             evt2irq(0x0d40), evt2irq(0x0d40) },
 168 };
 169
 170 static struct platform_device scif5_device = {
 171         .name           = "sh-sci",
 172         .id             = 5,
 173         .dev            = {
 174                 .platform_data  = &scif5_platform_data,
 175         },
 176 };
 177
 178 /* SCIFB */
 179 static struct plat_sci_port scif6_platform_data = {
 180         .mapbase        = 0xe6c30000,
 181         .flags          = UPF_BOOT_AUTOCONF,
 182         .scscr          = SCSCR_RE | SCSCR_TE,
 183         .scbrr_algo_id  = SCBRR_ALGO_4,
 184         .type           = PORT_SCIFB,
 185         .irqs           = { evt2irq(0x0d60), evt2irq(0x0d60),
 186                             evt2irq(0x0d60), evt2irq(0x0d60) },
 187 };
 188
 189 static struct platform_device scif6_device = {
 190         .name           = "sh-sci",
 191         .id             = 6,
 192         .dev            = {
 193                 .platform_data  = &scif6_platform_data,
 194         },
 195 };
 196
 197 /* CMT */
 198 static struct sh_timer_config cmt2_platform_data = {
 199         .name = "CMT2",
 200         .channel_offset = 0x40,
 201         .timer_bit = 5,
 202         .clockevent_rating = 125,
 203         .clocksource_rating = 125,
 204 };
 205
 206 static struct resource cmt2_resources[] = {
 207         [0] = {
 208                 .name   = "CMT2",
 209                 .start  = 0xe6130040,
 210                 .end    = 0xe613004b,
 211                 .flags  = IORESOURCE_MEM,
 212         },
 213         [1] = {
 214                 .start  = evt2irq(0x0b80), /* CMT2 */
 215                 .flags  = IORESOURCE_IRQ,
 216         },
 217 };
 218
 219 static struct platform_device cmt2_device = {
 220         .name           = "sh_cmt",
 221         .id             = 2,
 222         .dev = {
 223                 .platform_data  = &cmt2_platform_data,
 224         },
 225         .resource       = cmt2_resources,
 226         .num_resources  = ARRAY_SIZE(cmt2_resources),
 227 };
 228
 229 /* TMU */
 230 static struct sh_timer_config tmu00_platform_data = {
 231         .name = "TMU00",
 232         .channel_offset = 0x4,
 233         .timer_bit = 0,
 234         .clockevent_rating = 200,
 235 };
 236
 237 static struct resource tmu00_resources[] = {
 238         [0] = {
 239                 .name   = "TMU00",
 240                 .start  = 0xfff60008,
 241                 .end    = 0xfff60013,
 242                 .flags  = IORESOURCE_MEM,
 243         },
 244         [1] = {
 245                 .start  = intcs_evt2irq(0xe80), /* TMU_TUNI0 */
 246                 .flags  = IORESOURCE_IRQ,
 247         },
 248 };
 249
 250 static struct platform_device tmu00_device = {
 251         .name           = "sh_tmu",
 252         .id             = 0,
 253         .dev = {
 254                 .platform_data  = &tmu00_platform_data,
 255         },
 256         .resource       = tmu00_resources,
 257         .num_resources  = ARRAY_SIZE(tmu00_resources),
 258 };
 259
 260 static struct sh_timer_config tmu01_platform_data = {
 261         .name = "TMU01",
 262         .channel_offset = 0x10,
 263         .timer_bit = 1,
 264         .clocksource_rating = 200,
 265 };
 266
 267 static struct resource tmu01_resources[] = {
 268         [0] = {
 269                 .name   = "TMU01",
 270                 .start  = 0xfff60014,
 271                 .end    = 0xfff6001f,
 272                 .flags  = IORESOURCE_MEM,
 273         },
 274         [1] = {
 275                 .start  = intcs_evt2irq(0xea0), /* TMU_TUNI1 */
 276                 .flags  = IORESOURCE_IRQ,
 277         },
 278 };
 279
 280 static struct platform_device tmu01_device = {
 281         .name           = "sh_tmu",
 282         .id             = 1,
 283         .dev = {
 284                 .platform_data  = &tmu01_platform_data,
 285         },
 286         .resource       = tmu01_resources,
 287         .num_resources  = ARRAY_SIZE(tmu01_resources),
 288 };
 289
 290 /* I2C */
 291 static struct resource iic0_resources[] = {
 292         [0] = {
 293                 .name   = "IIC0",
 294                 .start  = 0xFFF20000,
 295                 .end    = 0xFFF20425 - 1,
 296                 .flags  = IORESOURCE_MEM,
 297         },
 298         [1] = {
 299                 .start  = intcs_evt2irq(0xe00), /* IIC0_ALI0 */
 300                 .end    = intcs_evt2irq(0xe60), /* IIC0_DTEI0 */
 301                 .flags  = IORESOURCE_IRQ,
 302         },
 303 };
 304
 305 static struct platform_device iic0_device = {
 306         .name           = "i2c-sh_mobile",
 307         .id             = 0, /* "i2c0" clock */
 308         .num_resources  = ARRAY_SIZE(iic0_resources),
 309         .resource       = iic0_resources,
 310 };
 311
 312 static struct resource iic1_resources[] = {
 313         [0] = {
 314                 .name   = "IIC1",
 315                 .start  = 0xE6C20000,
 316                 .end    = 0xE6C20425 - 1,
 317                 .flags  = IORESOURCE_MEM,
 318         },
 319         [1] = {
 320                 .start  = evt2irq(0x780), /* IIC1_ALI1 */
 321                 .end    = evt2irq(0x7e0), /* IIC1_DTEI1 */
 322                 .flags  = IORESOURCE_IRQ,
 323         },
 324 };
 325
 326 static struct platform_device iic1_device = {
 327         .name           = "i2c-sh_mobile",
 328         .id             = 1, /* "i2c1" clock */
 329         .num_resources  = ARRAY_SIZE(iic1_resources),
 330         .resource       = iic1_resources,
 331 };
 332
 333 /* DMA */
 334 static const struct sh_dmae_slave_config sh7372_dmae_slaves[] = {
 335         {
 336                 .slave_id       = SHDMA_SLAVE_SCIF0_TX,
 337                 .addr           = 0xe6c40020,
 338                 .chcr           = CHCR_TX(XMIT_SZ_8BIT),
 339                 .mid_rid        = 0x21,
 340         }, {
 341                 .slave_id       = SHDMA_SLAVE_SCIF0_RX,
 342                 .addr           = 0xe6c40024,
 343                 .chcr           = CHCR_RX(XMIT_SZ_8BIT),
 344                 .mid_rid        = 0x22,
 345         }, {
 346                 .slave_id       = SHDMA_SLAVE_SCIF1_TX,
 347                 .addr           = 0xe6c50020,
 348                 .chcr           = CHCR_TX(XMIT_SZ_8BIT),
 349                 .mid_rid        = 0x25,
 350         }, {
 351                 .slave_id       = SHDMA_SLAVE_SCIF1_RX,
 352                 .addr           = 0xe6c50024,
 353                 .chcr           = CHCR_RX(XMIT_SZ_8BIT),
 354                 .mid_rid        = 0x26,
 355         }, {
 356                 .slave_id       = SHDMA_SLAVE_SCIF2_TX,
 357                 .addr           = 0xe6c60020,
 358                 .chcr           = CHCR_TX(XMIT_SZ_8BIT),
 359                 .mid_rid        = 0x29,
 360         }, {
 361                 .slave_id       = SHDMA_SLAVE_SCIF2_RX,
 362                 .addr           = 0xe6c60024,
 363                 .chcr           = CHCR_RX(XMIT_SZ_8BIT),
 364                 .mid_rid        = 0x2a,
 365         }, {
 366                 .slave_id       = SHDMA_SLAVE_SCIF3_TX,
 367                 .addr           = 0xe6c70020,
 368                 .chcr           = CHCR_TX(XMIT_SZ_8BIT),
 369                 .mid_rid        = 0x2d,
 370         }, {
 371                 .slave_id       = SHDMA_SLAVE_SCIF3_RX,
 372                 .addr           = 0xe6c70024,
 373                 .chcr           = CHCR_RX(XMIT_SZ_8BIT),
 374                 .mid_rid        = 0x2e,
 375         }, {
 376                 .slave_id       = SHDMA_SLAVE_SCIF4_TX,
 377                 .addr           = 0xe6c80020,
 378                 .chcr           = CHCR_TX(XMIT_SZ_8BIT),
 379                 .mid_rid        = 0x39,
 380         }, {
 381                 .slave_id       = SHDMA_SLAVE_SCIF4_RX,
 382                 .addr           = 0xe6c80024,
 383                 .chcr           = CHCR_RX(XMIT_SZ_8BIT),
 384                 .mid_rid        = 0x3a,
 385         }, {
 386                 .slave_id       = SHDMA_SLAVE_SCIF5_TX,
 387                 .addr           = 0xe6cb0020,
 388                 .chcr           = CHCR_TX(XMIT_SZ_8BIT),
 389                 .mid_rid        = 0x35,
 390         }, {
 391                 .slave_id       = SHDMA_SLAVE_SCIF5_RX,
 392                 .addr           = 0xe6cb0024,
 393                 .chcr           = CHCR_RX(XMIT_SZ_8BIT),
 394                 .mid_rid        = 0x36,
 395         }, {
 396                 .slave_id       = SHDMA_SLAVE_SCIF6_TX,
 397                 .addr           = 0xe6c30040,
 398                 .chcr           = CHCR_TX(XMIT_SZ_8BIT),
 399                 .mid_rid        = 0x3d,
 400         }, {
 401                 .slave_id       = SHDMA_SLAVE_SCIF6_RX,
 402                 .addr           = 0xe6c30060,
 403                 .chcr           = CHCR_RX(XMIT_SZ_8BIT),
 404                 .mid_rid        = 0x3e,
 405         }, {
 406                 .slave_id       = SHDMA_SLAVE_FLCTL0_TX,
 407                 .addr           = 0xe6a30050,
 408                 .chcr           = CHCR_TX(XMIT_SZ_32BIT),
 409                 .mid_rid        = 0x83,
 410         }, {
 411                 .slave_id       = SHDMA_SLAVE_FLCTL0_RX,
 412                 .addr           = 0xe6a30050,
 413                 .chcr           = CHCR_RX(XMIT_SZ_32BIT),
 414                 .mid_rid        = 0x83,
 415         }, {
 416                 .slave_id       = SHDMA_SLAVE_FLCTL1_TX,
 417                 .addr           = 0xe6a30060,
 418                 .chcr           = CHCR_TX(XMIT_SZ_32BIT),
 419                 .mid_rid        = 0x87,
 420         }, {
 421                 .slave_id       = SHDMA_SLAVE_FLCTL1_RX,
 422                 .addr           = 0xe6a30060,
 423                 .chcr           = CHCR_RX(XMIT_SZ_32BIT),
 424                 .mid_rid        = 0x87,
 425         }, {
 426                 .slave_id       = SHDMA_SLAVE_SDHI0_TX,
 427                 .addr           = 0xe6850030,
 428                 .chcr           = CHCR_TX(XMIT_SZ_16BIT),
 429                 .mid_rid        = 0xc1,
 430         }, {
 431                 .slave_id       = SHDMA_SLAVE_SDHI0_RX,
 432                 .addr           = 0xe6850030,
 433                 .chcr           = CHCR_RX(XMIT_SZ_16BIT),
 434                 .mid_rid        = 0xc2,
 435         }, {
 436                 .slave_id       = SHDMA_SLAVE_SDHI1_TX,
 437                 .addr           = 0xe6860030,
 438                 .chcr           = CHCR_TX(XMIT_SZ_16BIT),
 439                 .mid_rid        = 0xc9,
 440         }, {
 441                 .slave_id       = SHDMA_SLAVE_SDHI1_RX,
 442                 .addr           = 0xe6860030,
 443                 .chcr           = CHCR_RX(XMIT_SZ_16BIT),
 444                 .mid_rid        = 0xca,
 445         }, {
 446                 .slave_id       = SHDMA_SLAVE_SDHI2_TX,
 447                 .addr           = 0xe6870030,
 448                 .chcr           = CHCR_TX(XMIT_SZ_16BIT),
 449                 .mid_rid        = 0xcd,
 450         }, {
 451                 .slave_id       = SHDMA_SLAVE_SDHI2_RX,
 452                 .addr           = 0xe6870030,
 453                 .chcr           = CHCR_RX(XMIT_SZ_16BIT),
 454                 .mid_rid        = 0xce,
 455         }, {
 456                 .slave_id       = SHDMA_SLAVE_FSIA_TX,
 457                 .addr           = 0xfe1f0024,
 458                 .chcr           = CHCR_TX(XMIT_SZ_32BIT),
 459                 .mid_rid        = 0xb1,
 460         }, {
 461                 .slave_id       = SHDMA_SLAVE_FSIA_RX,
 462                 .addr           = 0xfe1f0020,
 463                 .chcr           = CHCR_RX(XMIT_SZ_32BIT),
 464                 .mid_rid        = 0xb2,
 465         }, {
 466                 .slave_id       = SHDMA_SLAVE_MMCIF_TX,
 467                 .addr           = 0xe6bd0034,
 468                 .chcr           = CHCR_TX(XMIT_SZ_32BIT),
 469                 .mid_rid        = 0xd1,
 470         }, {
 471                 .slave_id       = SHDMA_SLAVE_MMCIF_RX,
 472                 .addr           = 0xe6bd0034,
 473                 .chcr           = CHCR_RX(XMIT_SZ_32BIT),
 474                 .mid_rid        = 0xd2,
 475         },
 476 };
 477
 478 #define SH7372_CHCLR (0x220 - 0x20)
 479
 480 static const struct sh_dmae_channel sh7372_dmae_channels[] = {
 481         {
 482                 .offset = 0,
 483                 .dmars = 0,
 484                 .dmars_bit = 0,
 485                 .chclr_offset = SH7372_CHCLR + 0,
 486         }, {
 487                 .offset = 0x10,
 488                 .dmars = 0,
 489                 .dmars_bit = 8,
 490                 .chclr_offset = SH7372_CHCLR + 0x10,
 491         }, {
 492                 .offset = 0x20,
 493                 .dmars = 4,
 494                 .dmars_bit = 0,
 495                 .chclr_offset = SH7372_CHCLR + 0x20,
 496         }, {
 497                 .offset = 0x30,
 498                 .dmars = 4,
 499                 .dmars_bit = 8,
 500                 .chclr_offset = SH7372_CHCLR + 0x30,
 501         }, {
 502                 .offset = 0x50,
 503                 .dmars = 8,
 504                 .dmars_bit = 0,
 505                 .chclr_offset = SH7372_CHCLR + 0x50,
 506         }, {
 507                 .offset = 0x60,
 508                 .dmars = 8,
 509                 .dmars_bit = 8,
 510                 .chclr_offset = SH7372_CHCLR + 0x60,
 511         }
 512 };
 513
 514 static struct sh_dmae_pdata dma_platform_data = {
 515         .slave          = sh7372_dmae_slaves,
 516         .slave_num      = ARRAY_SIZE(sh7372_dmae_slaves),
 517         .channel        = sh7372_dmae_channels,
 518         .channel_num    = ARRAY_SIZE(sh7372_dmae_channels),
 519         .ts_low_shift   = TS_LOW_SHIFT,
 520         .ts_low_mask    = TS_LOW_BIT << TS_LOW_SHIFT,
 521         .ts_high_shift  = TS_HI_SHIFT,
 522         .ts_high_mask   = TS_HI_BIT << TS_HI_SHIFT,
 523         .ts_shift       = dma_ts_shift,
 524         .ts_shift_num   = ARRAY_SIZE(dma_ts_shift),
 525         .dmaor_init     = DMAOR_DME,
 526         .chclr_present  = 1,
 527 };
 528
 529 /* Resource order important! */
 530 static struct resource sh7372_dmae0_resources[] = {
 531         {
 532                 /* Channel registers and DMAOR */
 533                 .start  = 0xfe008020,
 534                 .end    = 0xfe00828f,
 535                 .flags  = IORESOURCE_MEM,
 536         },
 537         {
 538                 /* DMARSx */
 539                 .start  = 0xfe009000,
 540                 .end    = 0xfe00900b,
 541                 .flags  = IORESOURCE_MEM,
 542         },
 543         {
 544                 .name   = "error_irq",
 545                 .start  = evt2irq(0x20c0),
 546                 .end    = evt2irq(0x20c0),
 547                 .flags  = IORESOURCE_IRQ,
 548         },
 549         {
 550                 /* IRQ for channels 0-5 */
 551                 .start  = evt2irq(0x2000),
 552                 .end    = evt2irq(0x20a0),
 553                 .flags  = IORESOURCE_IRQ,
 554         },
 555 };
 556
 557 /* Resource order important! */
 558 static struct resource sh7372_dmae1_resources[] = {
 559         {
 560                 /* Channel registers and DMAOR */
 561                 .start  = 0xfe018020,
 562                 .end    = 0xfe01828f,
 563                 .flags  = IORESOURCE_MEM,
 564         },
 565         {
 566                 /* DMARSx */
 567                 .start  = 0xfe019000,
 568                 .end    = 0xfe01900b,
 569                 .flags  = IORESOURCE_MEM,
 570         },
 571         {
 572                 .name   = "error_irq",
 573                 .start  = evt2irq(0x21c0),
 574                 .end    = evt2irq(0x21c0),
 575                 .flags  = IORESOURCE_IRQ,
 576         },
 577         {
 578                 /* IRQ for channels 0-5 */
 579                 .start  = evt2irq(0x2100),
 580                 .end    = evt2irq(0x21a0),
 581                 .flags  = IORESOURCE_IRQ,
 582         },
 583 };
 584
 585 /* Resource order important! */
 586 static struct resource sh7372_dmae2_resources[] = {
 587         {
 588                 /* Channel registers and DMAOR */
 589                 .start  = 0xfe028020,
 590                 .end    = 0xfe02828f,
 591                 .flags  = IORESOURCE_MEM,
 592         },
 593         {
 594                 /* DMARSx */
 595                 .start  = 0xfe029000,
 596                 .end    = 0xfe02900b,
 597                 .flags  = IORESOURCE_MEM,
 598         },
 599         {
 600                 .name   = "error_irq",
 601                 .start  = evt2irq(0x22c0),
 602                 .end    = evt2irq(0x22c0),
 603                 .flags  = IORESOURCE_IRQ,
 604         },
 605         {
 606                 /* IRQ for channels 0-5 */
 607                 .start  = evt2irq(0x2200),
 608                 .end    = evt2irq(0x22a0),
 609                 .flags  = IORESOURCE_IRQ,
 610         },
 611 };
 612
 613 static struct platform_device dma0_device = {
 614         .name           = "sh-dma-engine",
 615         .id             = 0,
 616         .resource       = sh7372_dmae0_resources,
 617         .num_resources  = ARRAY_SIZE(sh7372_dmae0_resources),
 618         .dev            = {
 619                 .platform_data  = &dma_platform_data,
 620         },
 621 };
 622
 623 static struct platform_device dma1_device = {
 624         .name           = "sh-dma-engine",
 625         .id             = 1,
 626         .resource       = sh7372_dmae1_resources,
 627         .num_resources  = ARRAY_SIZE(sh7372_dmae1_resources),
 628         .dev            = {
 629                 .platform_data  = &dma_platform_data,
 630         },
 631 };
 632
 633 static struct platform_device dma2_device = {
 634         .name           = "sh-dma-engine",
 635         .id             = 2,
 636         .resource       = sh7372_dmae2_resources,
 637         .num_resources  = ARRAY_SIZE(sh7372_dmae2_resources),
 638         .dev            = {
 639                 .platform_data  = &dma_platform_data,
 640         },
 641 };
 642
 643 /*
 644  * USB-DMAC
 645  */
 646 static const struct sh_dmae_channel sh7372_usb_dmae_channels[] = {
 647         {
 648                 .offset = 0,
 649         }, {
 650                 .offset = 0x20,
 651         },
 652 };
 653
 654 /* USB DMAC0 */
 655 static const struct sh_dmae_slave_config sh7372_usb_dmae0_slaves[] = {
 656         {
 657                 .slave_id       = SHDMA_SLAVE_USB0_TX,
 658                 .chcr           = USBTS_INDEX2VAL(USBTS_XMIT_SZ_8BYTE),
 659         }, {
 660                 .slave_id       = SHDMA_SLAVE_USB0_RX,
 661                 .chcr           = USBTS_INDEX2VAL(USBTS_XMIT_SZ_8BYTE),
 662         },
 663 };
 664
 665 static struct sh_dmae_pdata usb_dma0_platform_data = {
 666         .slave          = sh7372_usb_dmae0_slaves,
 667         .slave_num      = ARRAY_SIZE(sh7372_usb_dmae0_slaves),
 668         .channel        = sh7372_usb_dmae_channels,
 669         .channel_num    = ARRAY_SIZE(sh7372_usb_dmae_channels),
 670         .ts_low_shift   = USBTS_LOW_SHIFT,
 671         .ts_low_mask    = USBTS_LOW_BIT << USBTS_LOW_SHIFT,
 672         .ts_high_shift  = USBTS_HI_SHIFT,
 673         .ts_high_mask   = USBTS_HI_BIT << USBTS_HI_SHIFT,
 674         .ts_shift       = dma_usbts_shift,
 675         .ts_shift_num   = ARRAY_SIZE(dma_usbts_shift),
 676         .dmaor_init     = DMAOR_DME,
 677         .chcr_offset    = 0x14,
 678         .chcr_ie_bit    = 1 << 5,
 679         .dmaor_is_32bit = 1,
 680         .needs_tend_set = 1,
 681         .no_dmars       = 1,
 682         .slave_only     = 1,
 683 };
 684
 685 static struct resource sh7372_usb_dmae0_resources[] = {
 686         {
 687                 /* Channel registers and DMAOR */
 688                 .start  = 0xe68a0020,
 689                 .end    = 0xe68a0064 - 1,
 690                 .flags  = IORESOURCE_MEM,
 691         },
 692         {
 693                 /* VCR/SWR/DMICR */
 694                 .start  = 0xe68a0000,
 695                 .end    = 0xe68a0014 - 1,
 696                 .flags  = IORESOURCE_MEM,
 697         },
 698         {
 699                 /* IRQ for channels */
 700                 .start  = evt2irq(0x0a00),
 701                 .end    = evt2irq(0x0a00),
 702                 .flags  = IORESOURCE_IRQ,
 703         },
 704 };
 705
 706 static struct platform_device usb_dma0_device = {
 707         .name           = "sh-dma-engine",
 708         .id             = 3,
 709         .resource       = sh7372_usb_dmae0_resources,
 710         .num_resources  = ARRAY_SIZE(sh7372_usb_dmae0_resources),
 711         .dev            = {
 712                 .platform_data  = &usb_dma0_platform_data,
 713         },
 714 };
 715
 716 /* USB DMAC1 */
 717 static const struct sh_dmae_slave_config sh7372_usb_dmae1_slaves[] = {
 718         {
 719                 .slave_id       = SHDMA_SLAVE_USB1_TX,
 720                 .chcr           = USBTS_INDEX2VAL(USBTS_XMIT_SZ_8BYTE),
 721         }, {
 722                 .slave_id       = SHDMA_SLAVE_USB1_RX,
 723                 .chcr           = USBTS_INDEX2VAL(USBTS_XMIT_SZ_8BYTE),
 724         },
 725 };
 726
 727 static struct sh_dmae_pdata usb_dma1_platform_data = {
 728         .slave          = sh7372_usb_dmae1_slaves,
 729         .slave_num      = ARRAY_SIZE(sh7372_usb_dmae1_slaves),
 730         .channel        = sh7372_usb_dmae_channels,
 731         .channel_num    = ARRAY_SIZE(sh7372_usb_dmae_channels),
 732         .ts_low_shift   = USBTS_LOW_SHIFT,
 733         .ts_low_mask    = USBTS_LOW_BIT << USBTS_LOW_SHIFT,
 734         .ts_high_shift  = USBTS_HI_SHIFT,
 735         .ts_high_mask   = USBTS_HI_BIT << USBTS_HI_SHIFT,
 736         .ts_shift       = dma_usbts_shift,
 737         .ts_shift_num   = ARRAY_SIZE(dma_usbts_shift),
 738         .dmaor_init     = DMAOR_DME,
 739         .chcr_offset    = 0x14,
 740         .chcr_ie_bit    = 1 << 5,
 741         .dmaor_is_32bit = 1,
 742         .needs_tend_set = 1,
 743         .no_dmars       = 1,
 744         .slave_only     = 1,
 745 };
 746
 747 static struct resource sh7372_usb_dmae1_resources[] = {
 748         {
 749                 /* Channel registers and DMAOR */
 750                 .start  = 0xe68c0020,
 751                 .end    = 0xe68c0064 - 1,
 752                 .flags  = IORESOURCE_MEM,
 753         },
 754         {
 755                 /* VCR/SWR/DMICR */
 756                 .start  = 0xe68c0000,
 757                 .end    = 0xe68c0014 - 1,
 758                 .flags  = IORESOURCE_MEM,
 759         },
 760         {
 761                 /* IRQ for channels */
 762                 .start  = evt2irq(0x1d00),
 763                 .end    = evt2irq(0x1d00),
 764                 .flags  = IORESOURCE_IRQ,
 765         },
 766 };
 767
 768 static struct platform_device usb_dma1_device = {
 769         .name           = "sh-dma-engine",
 770         .id             = 4,
 771         .resource       = sh7372_usb_dmae1_resources,
 772         .num_resources  = ARRAY_SIZE(sh7372_usb_dmae1_resources),
 773         .dev            = {
 774                 .platform_data  = &usb_dma1_platform_data,
 775         },
 776 };
 777
 778 /* VPU */
 779 static struct uio_info vpu_platform_data = {
 780         .name = "VPU5HG",
 781         .version = "0",
 782         .irq = intcs_evt2irq(0x980),
 783 };
 784
 785 static struct resource vpu_resources[] = {
 786         [0] = {
 787                 .name   = "VPU",
 788                 .start  = 0xfe900000,
 789                 .end    = 0xfe900157,
 790                 .flags  = IORESOURCE_MEM,
 791         },
 792 };
 793
 794 static struct platform_device vpu_device = {
 795         .name           = "uio_pdrv_genirq",
 796         .id             = 0,
 797         .dev = {
 798                 .platform_data  = &vpu_platform_data,
 799         },
 800         .resource       = vpu_resources,
 801         .num_resources  = ARRAY_SIZE(vpu_resources),
 802 };
 803
 804 /* VEU0 */
 805 static struct uio_info veu0_platform_data = {
 806         .name = "VEU0",
 807         .version = "0",
 808         .irq = intcs_evt2irq(0x700),
 809 };
 810
 811 static struct resource veu0_resources[] = {
 812         [0] = {
 813                 .name   = "VEU0",
 814                 .start  = 0xfe920000,
 815                 .end    = 0xfe9200cb,
 816                 .flags  = IORESOURCE_MEM,
 817         },
 818 };
 819
 820 static struct platform_device veu0_device = {
 821         .name           = "uio_pdrv_genirq",
 822         .id             = 1,
 823         .dev = {
 824                 .platform_data  = &veu0_platform_data,
 825         },
 826         .resource       = veu0_resources,
 827         .num_resources  = ARRAY_SIZE(veu0_resources),
 828 };
 829
 830 /* VEU1 */
 831 static struct uio_info veu1_platform_data = {
 832         .name = "VEU1",
 833         .version = "0",
 834         .irq = intcs_evt2irq(0x720),
 835 };
 836
 837 static struct resource veu1_resources[] = {
 838         [0] = {
 839                 .name   = "VEU1",
 840                 .start  = 0xfe924000,
 841                 .end    = 0xfe9240cb,
 842                 .flags  = IORESOURCE_MEM,
 843         },
 844 };
 845
 846 static struct platform_device veu1_device = {
 847         .name           = "uio_pdrv_genirq",
 848         .id             = 2,
 849         .dev = {
 850                 .platform_data  = &veu1_platform_data,
 851         },
 852         .resource       = veu1_resources,
 853         .num_resources  = ARRAY_SIZE(veu1_resources),
 854 };
 855
 856 /* VEU2 */
 857 static struct uio_info veu2_platform_data = {
 858         .name = "VEU2",
 859         .version = "0",
 860         .irq = intcs_evt2irq(0x740),
 861 };
 862
 863 static struct resource veu2_resources[] = {
 864         [0] = {
 865                 .name   = "VEU2",
 866                 .start  = 0xfe928000,
 867                 .end    = 0xfe928307,
 868                 .flags  = IORESOURCE_MEM,
 869         },
 870 };
 871
 872 static struct platform_device veu2_device = {
 873         .name           = "uio_pdrv_genirq",
 874         .id             = 3,
 875         .dev = {
 876                 .platform_data  = &veu2_platform_data,
 877         },
 878         .resource       = veu2_resources,
 879         .num_resources  = ARRAY_SIZE(veu2_resources),
 880 };
 881
 882 /* VEU3 */
 883 static struct uio_info veu3_platform_data = {
 884         .name = "VEU3",
 885         .version = "0",
 886         .irq = intcs_evt2irq(0x760),
 887 };
 888
 889 static struct resource veu3_resources[] = {
 890         [0] = {
 891                 .name   = "VEU3",
 892                 .start  = 0xfe92c000,
 893                 .end    = 0xfe92c307,
 894                 .flags  = IORESOURCE_MEM,
 895         },
 896 };
 897
 898 static struct platform_device veu3_device = {
 899         .name           = "uio_pdrv_genirq",
 900         .id             = 4,
 901         .dev = {
 902                 .platform_data  = &veu3_platform_data,
 903         },
 904         .resource       = veu3_resources,
 905         .num_resources  = ARRAY_SIZE(veu3_resources),
 906 };
 907
 908 /* JPU */
 909 static struct uio_info jpu_platform_data = {
 910         .name = "JPU",
 911         .version = "0",
 912         .irq = intcs_evt2irq(0x560),
 913 };
 914
 915 static struct resource jpu_resources[] = {
 916         [0] = {
 917                 .name   = "JPU",
 918                 .start  = 0xfe980000,
 919                 .end    = 0xfe9902d3,
 920                 .flags  = IORESOURCE_MEM,
 921         },
 922 };
 923
 924 static struct platform_device jpu_device = {
 925         .name           = "uio_pdrv_genirq",
 926         .id             = 5,
 927         .dev = {
 928                 .platform_data  = &jpu_platform_data,
 929         },
 930         .resource       = jpu_resources,
 931         .num_resources  = ARRAY_SIZE(jpu_resources),
 932 };
 933
 934 /* SPU2DSP0 */
 935 static struct uio_info spu0_platform_data = {
 936         .name = "SPU2DSP0",
 937         .version = "0",
 938         .irq = evt2irq(0x1800),
 939 };
 940
 941 static struct resource spu0_resources[] = {
 942         [0] = {
 943                 .name   = "SPU2DSP0",
 944                 .start  = 0xfe200000,
 945                 .end    = 0xfe2fffff,
 946                 .flags  = IORESOURCE_MEM,
 947         },
 948 };
 949
 950 static struct platform_device spu0_device = {
 951         .name           = "uio_pdrv_genirq",
 952         .id             = 6,
 953         .dev = {
 954                 .platform_data  = &spu0_platform_data,
 955         },
 956         .resource       = spu0_resources,
 957         .num_resources  = ARRAY_SIZE(spu0_resources),
 958 };
 959
 960 /* SPU2DSP1 */
 961 static struct uio_info spu1_platform_data = {
 962         .name = "SPU2DSP1",
 963         .version = "0",
 964         .irq = evt2irq(0x1820),
 965 };
 966
 967 static struct resource spu1_resources[] = {
 968         [0] = {
 969                 .name   = "SPU2DSP1",
 970                 .start  = 0xfe300000,
 971                 .end    = 0xfe3fffff,
 972                 .flags  = IORESOURCE_MEM,
 973         },
 974 };
 975
 976 static struct platform_device spu1_device = {
 977         .name           = "uio_pdrv_genirq",
 978         .id             = 7,
 979         .dev = {
 980                 .platform_data  = &spu1_platform_data,
 981         },
 982         .resource       = spu1_resources,
 983         .num_resources  = ARRAY_SIZE(spu1_resources),
 984 };
 985
 986 /* IPMMUI (an IPMMU module for ICB/LMB) */
 987 static struct resource ipmmu_resources[] = {
 988         [0] = {
 989                 .name   = "IPMMUI",
 990                 .start  = 0xfe951000,
 991                 .end    = 0xfe9510ff,
 992                 .flags  = IORESOURCE_MEM,
 993         },
 994 };
 995
 996 static const char * const ipmmu_dev_names[] = {
 997         "sh_mobile_lcdc_fb.0",
 998         "sh_mobile_lcdc_fb.1",
 999         "sh_mobile_ceu.0",
1000         "uio_pdrv_genirq.0",
1001         "uio_pdrv_genirq.1",
1002         "uio_pdrv_genirq.2",
1003         "uio_pdrv_genirq.3",
1004         "uio_pdrv_genirq.4",
1005         "uio_pdrv_genirq.5",
1006 };
1007
1008 static struct shmobile_ipmmu_platform_data ipmmu_platform_data = {
1009         .dev_names = ipmmu_dev_names,
1010         .num_dev_names = ARRAY_SIZE(ipmmu_dev_names),
1011 };
1012
1013 static struct platform_device ipmmu_device = {
1014         .name           = "ipmmu",
1015         .id             = -1,
1016         .dev = {
1017                 .platform_data = &ipmmu_platform_data,
1018         },
1019         .resource       = ipmmu_resources,
1020         .num_resources  = ARRAY_SIZE(ipmmu_resources),
1021 };
1022
1023 static struct platform_device *sh7372_early_devices[] __initdata = {
1024         &scif0_device,
1025         &scif1_device,
1026         &scif2_device,
1027         &scif3_device,
1028         &scif4_device,
1029         &scif5_device,
1030         &scif6_device,
1031         &cmt2_device,
1032         &tmu00_device,
1033         &tmu01_device,
1034         &ipmmu_device,
1035 };
1036
1037 static struct platform_device *sh7372_late_devices[] __initdata = {
1038         &iic0_device,
1039         &iic1_device,
1040         &dma0_device,
1041         &dma1_device,
1042         &dma2_device,
1043         &usb_dma0_device,
1044         &usb_dma1_device,
1045         &vpu_device,
1046         &veu0_device,
1047         &veu1_device,
1048         &veu2_device,
1049         &veu3_device,
1050         &jpu_device,
1051         &spu0_device,
1052         &spu1_device,
1053 };
1054
1055 void __init sh7372_add_standard_devices(void)
1056 {
1057         struct pm_domain_device domain_devices[] = {
1058                 { "A3RV", &vpu_device, },
1059                 { "A4MP", &spu0_device, },
1060                 { "A4MP", &spu1_device, },
1061                 { "A3SP", &scif0_device, },
1062                 { "A3SP", &scif1_device, },
1063                 { "A3SP", &scif2_device, },
1064                 { "A3SP", &scif3_device, },
1065                 { "A3SP", &scif4_device, },
1066                 { "A3SP", &scif5_device, },
1067                 { "A3SP", &scif6_device, },
1068                 { "A3SP", &iic1_device, },
1069                 { "A3SP", &dma0_device, },
1070                 { "A3SP", &dma1_device, },
1071                 { "A3SP", &dma2_device, },
1072                 { "A3SP", &usb_dma0_device, },
1073                 { "A3SP", &usb_dma1_device, },
1074                 { "A4R", &iic0_device, },
1075                 { "A4R", &veu0_device, },
1076                 { "A4R", &veu1_device, },
1077                 { "A4R", &veu2_device, },
1078                 { "A4R", &veu3_device, },
1079                 { "A4R", &jpu_device, },
1080                 { "A4R", &tmu00_device, },
1081                 { "A4R", &tmu01_device, },
1082         };
1083
1084         sh7372_init_pm_domains();
1085
1086         platform_add_devices(sh7372_early_devices,
1087                             ARRAY_SIZE(sh7372_early_devices));
1088
1089         platform_add_devices(sh7372_late_devices,
1090                             ARRAY_SIZE(sh7372_late_devices));
1091
1092         rmobile_add_devices_to_domains(domain_devices,
1093                                        ARRAY_SIZE(domain_devices));
1094 }
1095
1096 static void __init sh7372_earlytimer_init(void)
1097 {
1098         sh7372_clock_init();
1099         shmobile_earlytimer_init();
1100 }
1101
1102 void __init sh7372_add_early_devices(void)
1103 {
1104         early_platform_add_devices(sh7372_early_devices,
1105                                    ARRAY_SIZE(sh7372_early_devices));
1106
1107         /* setup early console here as well */
1108         shmobile_setup_console();
1109
1110         /* override timer setup with soc-specific code */
1111         shmobile_timer.init = sh7372_earlytimer_init;
1112 }
1113
1114 #ifdef CONFIG_USE_OF
1115
1116 void __init sh7372_add_early_devices_dt(void)
1117 {
1118         shmobile_setup_delay(800, 1, 3); /* Cortex-A8 @ 800MHz */
1119
1120         early_platform_add_devices(sh7372_early_devices,
1121                                    ARRAY_SIZE(sh7372_early_devices));
1122
1123         /* setup early console here as well */
1124         shmobile_setup_console();
1125 }
1126
1127 static const struct of_dev_auxdata sh7372_auxdata_lookup[] __initconst = {
1128         { }
1129 };
1130
1131 void __init sh7372_add_standard_devices_dt(void)
1132 {
1133         /* clocks are setup late during boot in the case of DT */
1134         sh7372_clock_init();
1135
1136         platform_add_devices(sh7372_early_devices,
1137                             ARRAY_SIZE(sh7372_early_devices));
1138
1139         of_platform_populate(NULL, of_default_bus_match_table,
1140                              sh7372_auxdata_lookup, NULL);
1141 }
1142
1143 static const char *sh7372_boards_compat_dt[] __initdata = {
1144         "renesas,sh7372",
1145         NULL,
1146 };
1147
1148 DT_MACHINE_START(SH7372_DT, "Generic SH7372 (Flattened Device Tree)")
1149         .map_io         = sh7372_map_io,
1150         .init_early     = sh7372_add_early_devices_dt,
1151         .nr_irqs        = NR_IRQS_LEGACY,
1152         .init_irq       = sh7372_init_irq,
1153         .handle_irq     = shmobile_handle_irq_intc,
1154         .init_machine   = sh7372_add_standard_devices_dt,
1155         .timer          = &shmobile_timer,
1156         .dt_compat      = sh7372_boards_compat_dt,
1157 MACHINE_END
1158
1159 #endif /* CONFIG_USE_OF */