ARM: shmobile: r8a7779: Remove legacy SoC code
[firefly-linux-kernel-4.4.55.git] / arch / arm / mach-shmobile / setup-r8a7779.c
1 /*
2  * r8a7779 processor support
3  *
4  * Copyright (C) 2011, 2013  Renesas Solutions Corp.
5  * Copyright (C) 2011  Magnus Damm
6  * Copyright (C) 2013  Cogent Embedded, Inc.
7  *
8  * This program is free software; you can redistribute it and/or modify
9  * it under the terms of the GNU General Public License as published by
10  * the Free Software Foundation; version 2 of the License.
11  *
12  * This program is distributed in the hope that it will be useful,
13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
15  * GNU General Public License for more details.
16  */
17 #include <linux/clk/shmobile.h>
18 #include <linux/clocksource.h>
19 #include <linux/init.h>
20 #include <linux/irq.h>
21 #include <linux/irqchip.h>
22 #include <linux/irqchip/arm-gic.h>
23
24 #include <asm/mach/arch.h>
25 #include <asm/mach/map.h>
26
27 #include "common.h"
28 #include "r8a7779.h"
29
30 static struct map_desc r8a7779_io_desc[] __initdata = {
31         /* 2M identity mapping for 0xf0000000 (MPCORE) */
32         {
33                 .virtual        = 0xf0000000,
34                 .pfn            = __phys_to_pfn(0xf0000000),
35                 .length         = SZ_2M,
36                 .type           = MT_DEVICE_NONSHARED
37         },
38         /* 16M identity mapping for 0xfexxxxxx (DMAC-S/HPBREG/INTC2/LRAM/DBSC) */
39         {
40                 .virtual        = 0xfe000000,
41                 .pfn            = __phys_to_pfn(0xfe000000),
42                 .length         = SZ_16M,
43                 .type           = MT_DEVICE_NONSHARED
44         },
45 };
46
47 static void __init r8a7779_map_io(void)
48 {
49         debug_ll_io_init();
50         iotable_init(r8a7779_io_desc, ARRAY_SIZE(r8a7779_io_desc));
51 }
52
53 /* IRQ */
54 #define INT2SMSKCR0 IOMEM(0xfe7822a0)
55 #define INT2SMSKCR1 IOMEM(0xfe7822a4)
56 #define INT2SMSKCR2 IOMEM(0xfe7822a8)
57 #define INT2SMSKCR3 IOMEM(0xfe7822ac)
58 #define INT2SMSKCR4 IOMEM(0xfe7822b0)
59
60 #define INT2NTSR0 IOMEM(0xfe700060)
61 #define INT2NTSR1 IOMEM(0xfe700064)
62
63 static void __init r8a7779_init_irq_dt(void)
64 {
65         gic_set_irqchip_flags(IRQCHIP_SKIP_SET_WAKE);
66
67         irqchip_init();
68
69         /* route all interrupts to ARM */
70         __raw_writel(0xffffffff, INT2NTSR0);
71         __raw_writel(0x3fffffff, INT2NTSR1);
72
73         /* unmask all known interrupts in INTCS2 */
74         __raw_writel(0xfffffff0, INT2SMSKCR0);
75         __raw_writel(0xfff7ffff, INT2SMSKCR1);
76         __raw_writel(0xfffbffdf, INT2SMSKCR2);
77         __raw_writel(0xbffffffc, INT2SMSKCR3);
78         __raw_writel(0x003fee3f, INT2SMSKCR4);
79 }
80
81 #define MODEMR          0xffcc0020
82
83 static u32 __init r8a7779_read_mode_pins(void)
84 {
85         static u32 mode;
86         static bool mode_valid;
87
88         if (!mode_valid) {
89                 void __iomem *modemr = ioremap_nocache(MODEMR, PAGE_SIZE);
90                 BUG_ON(!modemr);
91                 mode = ioread32(modemr);
92                 iounmap(modemr);
93                 mode_valid = true;
94         }
95
96         return mode;
97 }
98
99 static void __init r8a7779_init_time(void)
100 {
101         r8a7779_clocks_init(r8a7779_read_mode_pins());
102         clocksource_of_init();
103 }
104
105 static const char *r8a7779_compat_dt[] __initdata = {
106         "renesas,r8a7779",
107         NULL,
108 };
109
110 DT_MACHINE_START(R8A7779_DT, "Generic R8A7779 (Flattened Device Tree)")
111         .smp            = smp_ops(r8a7779_smp_ops),
112         .map_io         = r8a7779_map_io,
113         .init_early     = shmobile_init_delay,
114         .init_time      = r8a7779_init_time,
115         .init_irq       = r8a7779_init_irq_dt,
116         .init_late      = shmobile_init_late,
117         .dt_compat      = r8a7779_compat_dt,
118 MACHINE_END