2 * R8A7740 processor support
4 * Copyright (C) 2011 Renesas Solutions Corp.
5 * Copyright (C) 2011 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 #include <linux/delay.h>
21 #include <linux/dma-mapping.h>
22 #include <linux/kernel.h>
23 #include <linux/init.h>
25 #include <linux/platform_device.h>
26 #include <linux/serial_sci.h>
27 #include <linux/sh_timer.h>
28 #include <mach/r8a7740.h>
29 #include <mach/common.h>
30 #include <mach/irqs.h>
31 #include <asm/mach-types.h>
32 #include <asm/mach/map.h>
33 #include <asm/mach/arch.h>
34 #include <asm/mach/time.h>
36 static struct map_desc r8a7740_io_desc[] __initdata = {
39 * 0xe6000000-0xefffffff -> 0xe6000000-0xefffffff
42 .virtual = 0xe6000000,
43 .pfn = __phys_to_pfn(0xe6000000),
45 .type = MT_DEVICE_NONSHARED
47 #ifdef CONFIG_CACHE_L2X0
50 * 0xf0100000-0xf0101000 -> 0xf0002000-0xf0003000
53 .virtual = 0xf0002000,
54 .pfn = __phys_to_pfn(0xf0100000),
56 .type = MT_DEVICE_NONSHARED
61 void __init r8a7740_map_io(void)
63 iotable_init(r8a7740_io_desc, ARRAY_SIZE(r8a7740_io_desc));
66 * DMA memory at 0xff200000 - 0xffdfffff. The default 2MB size isn't
67 * enough to allocate the frame buffer memory.
69 init_consistent_dma_size(12 << 20);
73 static struct plat_sci_port scif0_platform_data = {
74 .mapbase = 0xe6c40000,
75 .flags = UPF_BOOT_AUTOCONF,
76 .scscr = SCSCR_RE | SCSCR_TE,
77 .scbrr_algo_id = SCBRR_ALGO_4,
79 .irqs = SCIx_IRQ_MUXED(evt2irq(0x0c00)),
82 static struct platform_device scif0_device = {
86 .platform_data = &scif0_platform_data,
91 static struct plat_sci_port scif1_platform_data = {
92 .mapbase = 0xe6c50000,
93 .flags = UPF_BOOT_AUTOCONF,
94 .scscr = SCSCR_RE | SCSCR_TE,
95 .scbrr_algo_id = SCBRR_ALGO_4,
97 .irqs = SCIx_IRQ_MUXED(evt2irq(0x0c20)),
100 static struct platform_device scif1_device = {
104 .platform_data = &scif1_platform_data,
109 static struct plat_sci_port scif2_platform_data = {
110 .mapbase = 0xe6c60000,
111 .flags = UPF_BOOT_AUTOCONF,
112 .scscr = SCSCR_RE | SCSCR_TE,
113 .scbrr_algo_id = SCBRR_ALGO_4,
115 .irqs = SCIx_IRQ_MUXED(evt2irq(0x0c40)),
118 static struct platform_device scif2_device = {
122 .platform_data = &scif2_platform_data,
127 static struct plat_sci_port scif3_platform_data = {
128 .mapbase = 0xe6c70000,
129 .flags = UPF_BOOT_AUTOCONF,
130 .scscr = SCSCR_RE | SCSCR_TE,
131 .scbrr_algo_id = SCBRR_ALGO_4,
133 .irqs = SCIx_IRQ_MUXED(evt2irq(0x0c60)),
136 static struct platform_device scif3_device = {
140 .platform_data = &scif3_platform_data,
145 static struct plat_sci_port scif4_platform_data = {
146 .mapbase = 0xe6c80000,
147 .flags = UPF_BOOT_AUTOCONF,
148 .scscr = SCSCR_RE | SCSCR_TE,
149 .scbrr_algo_id = SCBRR_ALGO_4,
151 .irqs = SCIx_IRQ_MUXED(evt2irq(0x0d20)),
154 static struct platform_device scif4_device = {
158 .platform_data = &scif4_platform_data,
163 static struct plat_sci_port scif5_platform_data = {
164 .mapbase = 0xe6cb0000,
165 .flags = UPF_BOOT_AUTOCONF,
166 .scscr = SCSCR_RE | SCSCR_TE,
167 .scbrr_algo_id = SCBRR_ALGO_4,
169 .irqs = SCIx_IRQ_MUXED(evt2irq(0x0d40)),
172 static struct platform_device scif5_device = {
176 .platform_data = &scif5_platform_data,
181 static struct plat_sci_port scif6_platform_data = {
182 .mapbase = 0xe6cc0000,
183 .flags = UPF_BOOT_AUTOCONF,
184 .scscr = SCSCR_RE | SCSCR_TE,
185 .scbrr_algo_id = SCBRR_ALGO_4,
187 .irqs = SCIx_IRQ_MUXED(evt2irq(0x04c0)),
190 static struct platform_device scif6_device = {
194 .platform_data = &scif6_platform_data,
199 static struct plat_sci_port scif7_platform_data = {
200 .mapbase = 0xe6cd0000,
201 .flags = UPF_BOOT_AUTOCONF,
202 .scscr = SCSCR_RE | SCSCR_TE,
203 .scbrr_algo_id = SCBRR_ALGO_4,
205 .irqs = SCIx_IRQ_MUXED(evt2irq(0x04e0)),
208 static struct platform_device scif7_device = {
212 .platform_data = &scif7_platform_data,
217 static struct plat_sci_port scifb_platform_data = {
218 .mapbase = 0xe6c30000,
219 .flags = UPF_BOOT_AUTOCONF,
220 .scscr = SCSCR_RE | SCSCR_TE,
221 .scbrr_algo_id = SCBRR_ALGO_4,
223 .irqs = SCIx_IRQ_MUXED(evt2irq(0x0d60)),
226 static struct platform_device scifb_device = {
230 .platform_data = &scifb_platform_data,
235 static struct sh_timer_config cmt10_platform_data = {
237 .channel_offset = 0x10,
239 .clockevent_rating = 125,
240 .clocksource_rating = 125,
243 static struct resource cmt10_resources[] = {
248 .flags = IORESOURCE_MEM,
251 .start = evt2irq(0x0b00),
252 .flags = IORESOURCE_IRQ,
256 static struct platform_device cmt10_device = {
260 .platform_data = &cmt10_platform_data,
262 .resource = cmt10_resources,
263 .num_resources = ARRAY_SIZE(cmt10_resources),
266 static struct platform_device *r8a7740_early_devices[] __initdata = {
280 static struct resource i2c0_resources[] = {
284 .end = 0xfff20425 - 1,
285 .flags = IORESOURCE_MEM,
288 .start = intcs_evt2irq(0xe00),
289 .end = intcs_evt2irq(0xe60),
290 .flags = IORESOURCE_IRQ,
294 static struct resource i2c1_resources[] = {
298 .end = 0xe6c20425 - 1,
299 .flags = IORESOURCE_MEM,
302 .start = evt2irq(0x780), /* IIC1_ALI1 */
303 .end = evt2irq(0x7e0), /* IIC1_DTEI1 */
304 .flags = IORESOURCE_IRQ,
308 static struct platform_device i2c0_device = {
309 .name = "i2c-sh_mobile",
311 .resource = i2c0_resources,
312 .num_resources = ARRAY_SIZE(i2c0_resources),
315 static struct platform_device i2c1_device = {
316 .name = "i2c-sh_mobile",
318 .resource = i2c1_resources,
319 .num_resources = ARRAY_SIZE(i2c1_resources),
322 static struct platform_device *r8a7740_late_devices[] __initdata = {
328 #define ICSTART 0x0070
330 #define i2c_read(reg, offset) ioread8(reg + offset)
331 #define i2c_write(reg, offset, data) iowrite8(data, reg + offset)
334 * r8a7740 chip has lasting errata on I2C I/O pad reset.
335 * this is work-around for it.
337 static void r8a7740_i2c_workaround(struct platform_device *pdev)
339 struct resource *res;
342 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
343 if (unlikely(!res)) {
344 pr_err("r8a7740 i2c workaround fail (cannot find resource)\n");
348 reg = ioremap(res->start, resource_size(res));
349 if (unlikely(!reg)) {
350 pr_err("r8a7740 i2c workaround fail (cannot map IO)\n");
354 i2c_write(reg, ICCR, i2c_read(reg, ICCR) | 0x80);
355 i2c_read(reg, ICCR); /* dummy read */
357 i2c_write(reg, ICSTART, i2c_read(reg, ICSTART) | 0x10);
358 i2c_read(reg, ICSTART); /* dummy read */
362 i2c_write(reg, ICCR, 0x01);
363 i2c_write(reg, ICSTART, 0x00);
367 i2c_write(reg, ICCR, 0x10);
369 i2c_write(reg, ICCR, 0x00);
371 i2c_write(reg, ICCR, 0x10);
377 void __init r8a7740_add_standard_devices(void)
379 /* I2C work-around */
380 r8a7740_i2c_workaround(&i2c0_device);
381 r8a7740_i2c_workaround(&i2c1_device);
383 platform_add_devices(r8a7740_early_devices,
384 ARRAY_SIZE(r8a7740_early_devices));
385 platform_add_devices(r8a7740_late_devices,
386 ARRAY_SIZE(r8a7740_late_devices));
389 static void __init r8a7740_earlytimer_init(void)
391 r8a7740_clock_init(0);
392 shmobile_earlytimer_init();
395 void __init r8a7740_add_early_devices(void)
397 early_platform_add_devices(r8a7740_early_devices,
398 ARRAY_SIZE(r8a7740_early_devices));
400 /* setup early console here as well */
401 shmobile_setup_console();
403 /* override timer setup with soc-specific code */
404 shmobile_timer.init = r8a7740_earlytimer_init;