2 * R8A7740 processor support
4 * Copyright (C) 2011 Renesas Solutions Corp.
5 * Copyright (C) 2011 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 #include <linux/delay.h>
21 #include <linux/dma-mapping.h>
22 #include <linux/kernel.h>
23 #include <linux/init.h>
25 #include <linux/platform_device.h>
26 #include <linux/of_platform.h>
27 #include <linux/serial_sci.h>
28 #include <linux/sh_dma.h>
29 #include <linux/sh_timer.h>
30 #include <linux/dma-mapping.h>
31 #include <mach/dma-register.h>
32 #include <mach/r8a7740.h>
33 #include <mach/pm-rmobile.h>
34 #include <mach/common.h>
35 #include <mach/irqs.h>
36 #include <asm/mach-types.h>
37 #include <asm/mach/map.h>
38 #include <asm/mach/arch.h>
39 #include <asm/mach/time.h>
41 static struct map_desc r8a7740_io_desc[] __initdata = {
44 * 0xe6000000-0xefffffff -> 0xe6000000-0xefffffff
47 .virtual = 0xe6000000,
48 .pfn = __phys_to_pfn(0xe6000000),
50 .type = MT_DEVICE_NONSHARED
52 #ifdef CONFIG_CACHE_L2X0
55 * 0xf0100000-0xf0101000 -> 0xf0002000-0xf0003000
58 .virtual = 0xf0002000,
59 .pfn = __phys_to_pfn(0xf0100000),
61 .type = MT_DEVICE_NONSHARED
66 void __init r8a7740_map_io(void)
68 iotable_init(r8a7740_io_desc, ARRAY_SIZE(r8a7740_io_desc));
72 static struct plat_sci_port scif0_platform_data = {
73 .mapbase = 0xe6c40000,
74 .flags = UPF_BOOT_AUTOCONF,
75 .scscr = SCSCR_RE | SCSCR_TE,
76 .scbrr_algo_id = SCBRR_ALGO_4,
78 .irqs = SCIx_IRQ_MUXED(evt2irq(0x0c00)),
81 static struct platform_device scif0_device = {
85 .platform_data = &scif0_platform_data,
90 static struct plat_sci_port scif1_platform_data = {
91 .mapbase = 0xe6c50000,
92 .flags = UPF_BOOT_AUTOCONF,
93 .scscr = SCSCR_RE | SCSCR_TE,
94 .scbrr_algo_id = SCBRR_ALGO_4,
96 .irqs = SCIx_IRQ_MUXED(evt2irq(0x0c20)),
99 static struct platform_device scif1_device = {
103 .platform_data = &scif1_platform_data,
108 static struct plat_sci_port scif2_platform_data = {
109 .mapbase = 0xe6c60000,
110 .flags = UPF_BOOT_AUTOCONF,
111 .scscr = SCSCR_RE | SCSCR_TE,
112 .scbrr_algo_id = SCBRR_ALGO_4,
114 .irqs = SCIx_IRQ_MUXED(evt2irq(0x0c40)),
117 static struct platform_device scif2_device = {
121 .platform_data = &scif2_platform_data,
126 static struct plat_sci_port scif3_platform_data = {
127 .mapbase = 0xe6c70000,
128 .flags = UPF_BOOT_AUTOCONF,
129 .scscr = SCSCR_RE | SCSCR_TE,
130 .scbrr_algo_id = SCBRR_ALGO_4,
132 .irqs = SCIx_IRQ_MUXED(evt2irq(0x0c60)),
135 static struct platform_device scif3_device = {
139 .platform_data = &scif3_platform_data,
144 static struct plat_sci_port scif4_platform_data = {
145 .mapbase = 0xe6c80000,
146 .flags = UPF_BOOT_AUTOCONF,
147 .scscr = SCSCR_RE | SCSCR_TE,
148 .scbrr_algo_id = SCBRR_ALGO_4,
150 .irqs = SCIx_IRQ_MUXED(evt2irq(0x0d20)),
153 static struct platform_device scif4_device = {
157 .platform_data = &scif4_platform_data,
162 static struct plat_sci_port scif5_platform_data = {
163 .mapbase = 0xe6cb0000,
164 .flags = UPF_BOOT_AUTOCONF,
165 .scscr = SCSCR_RE | SCSCR_TE,
166 .scbrr_algo_id = SCBRR_ALGO_4,
168 .irqs = SCIx_IRQ_MUXED(evt2irq(0x0d40)),
171 static struct platform_device scif5_device = {
175 .platform_data = &scif5_platform_data,
180 static struct plat_sci_port scif6_platform_data = {
181 .mapbase = 0xe6cc0000,
182 .flags = UPF_BOOT_AUTOCONF,
183 .scscr = SCSCR_RE | SCSCR_TE,
184 .scbrr_algo_id = SCBRR_ALGO_4,
186 .irqs = SCIx_IRQ_MUXED(evt2irq(0x04c0)),
189 static struct platform_device scif6_device = {
193 .platform_data = &scif6_platform_data,
198 static struct plat_sci_port scif7_platform_data = {
199 .mapbase = 0xe6cd0000,
200 .flags = UPF_BOOT_AUTOCONF,
201 .scscr = SCSCR_RE | SCSCR_TE,
202 .scbrr_algo_id = SCBRR_ALGO_4,
204 .irqs = SCIx_IRQ_MUXED(evt2irq(0x04e0)),
207 static struct platform_device scif7_device = {
211 .platform_data = &scif7_platform_data,
216 static struct plat_sci_port scifb_platform_data = {
217 .mapbase = 0xe6c30000,
218 .flags = UPF_BOOT_AUTOCONF,
219 .scscr = SCSCR_RE | SCSCR_TE,
220 .scbrr_algo_id = SCBRR_ALGO_4,
222 .irqs = SCIx_IRQ_MUXED(evt2irq(0x0d60)),
225 static struct platform_device scifb_device = {
229 .platform_data = &scifb_platform_data,
234 static struct sh_timer_config cmt10_platform_data = {
236 .channel_offset = 0x10,
238 .clockevent_rating = 125,
239 .clocksource_rating = 125,
242 static struct resource cmt10_resources[] = {
247 .flags = IORESOURCE_MEM,
250 .start = evt2irq(0x0b00),
251 .flags = IORESOURCE_IRQ,
255 static struct platform_device cmt10_device = {
259 .platform_data = &cmt10_platform_data,
261 .resource = cmt10_resources,
262 .num_resources = ARRAY_SIZE(cmt10_resources),
265 static struct platform_device *r8a7740_early_devices[] __initdata = {
279 static const struct sh_dmae_slave_config r8a7740_dmae_slaves[] = {
281 .slave_id = SHDMA_SLAVE_SDHI0_TX,
283 .chcr = CHCR_TX(XMIT_SZ_16BIT),
286 .slave_id = SHDMA_SLAVE_SDHI0_RX,
288 .chcr = CHCR_RX(XMIT_SZ_16BIT),
291 .slave_id = SHDMA_SLAVE_SDHI1_TX,
293 .chcr = CHCR_TX(XMIT_SZ_16BIT),
296 .slave_id = SHDMA_SLAVE_SDHI1_RX,
298 .chcr = CHCR_RX(XMIT_SZ_16BIT),
301 .slave_id = SHDMA_SLAVE_SDHI2_TX,
303 .chcr = CHCR_TX(XMIT_SZ_16BIT),
306 .slave_id = SHDMA_SLAVE_SDHI2_RX,
308 .chcr = CHCR_RX(XMIT_SZ_16BIT),
311 .slave_id = SHDMA_SLAVE_FSIA_TX,
313 .chcr = CHCR_TX(XMIT_SZ_32BIT),
316 .slave_id = SHDMA_SLAVE_FSIA_RX,
318 .chcr = CHCR_RX(XMIT_SZ_32BIT),
321 .slave_id = SHDMA_SLAVE_FSIB_TX,
323 .chcr = CHCR_TX(XMIT_SZ_32BIT),
328 #define DMA_CHANNEL(a, b, c) \
333 .chclr_offset = (0x220 - 0x20) + a \
336 static const struct sh_dmae_channel r8a7740_dmae_channels[] = {
337 DMA_CHANNEL(0x00, 0, 0),
338 DMA_CHANNEL(0x10, 0, 8),
339 DMA_CHANNEL(0x20, 4, 0),
340 DMA_CHANNEL(0x30, 4, 8),
341 DMA_CHANNEL(0x50, 8, 0),
342 DMA_CHANNEL(0x60, 8, 8),
345 static struct sh_dmae_pdata dma_platform_data = {
346 .slave = r8a7740_dmae_slaves,
347 .slave_num = ARRAY_SIZE(r8a7740_dmae_slaves),
348 .channel = r8a7740_dmae_channels,
349 .channel_num = ARRAY_SIZE(r8a7740_dmae_channels),
350 .ts_low_shift = TS_LOW_SHIFT,
351 .ts_low_mask = TS_LOW_BIT << TS_LOW_SHIFT,
352 .ts_high_shift = TS_HI_SHIFT,
353 .ts_high_mask = TS_HI_BIT << TS_HI_SHIFT,
354 .ts_shift = dma_ts_shift,
355 .ts_shift_num = ARRAY_SIZE(dma_ts_shift),
356 .dmaor_init = DMAOR_DME,
360 /* Resource order important! */
361 static struct resource r8a7740_dmae0_resources[] = {
363 /* Channel registers and DMAOR */
366 .flags = IORESOURCE_MEM,
372 .flags = IORESOURCE_MEM,
376 .start = evt2irq(0x20c0),
377 .end = evt2irq(0x20c0),
378 .flags = IORESOURCE_IRQ,
381 /* IRQ for channels 0-5 */
382 .start = evt2irq(0x2000),
383 .end = evt2irq(0x20a0),
384 .flags = IORESOURCE_IRQ,
388 /* Resource order important! */
389 static struct resource r8a7740_dmae1_resources[] = {
391 /* Channel registers and DMAOR */
394 .flags = IORESOURCE_MEM,
400 .flags = IORESOURCE_MEM,
404 .start = evt2irq(0x21c0),
405 .end = evt2irq(0x21c0),
406 .flags = IORESOURCE_IRQ,
409 /* IRQ for channels 0-5 */
410 .start = evt2irq(0x2100),
411 .end = evt2irq(0x21a0),
412 .flags = IORESOURCE_IRQ,
416 /* Resource order important! */
417 static struct resource r8a7740_dmae2_resources[] = {
419 /* Channel registers and DMAOR */
422 .flags = IORESOURCE_MEM,
428 .flags = IORESOURCE_MEM,
432 .start = evt2irq(0x22c0),
433 .end = evt2irq(0x22c0),
434 .flags = IORESOURCE_IRQ,
437 /* IRQ for channels 0-5 */
438 .start = evt2irq(0x2200),
439 .end = evt2irq(0x22a0),
440 .flags = IORESOURCE_IRQ,
444 static struct platform_device dma0_device = {
445 .name = "sh-dma-engine",
447 .resource = r8a7740_dmae0_resources,
448 .num_resources = ARRAY_SIZE(r8a7740_dmae0_resources),
450 .platform_data = &dma_platform_data,
454 static struct platform_device dma1_device = {
455 .name = "sh-dma-engine",
457 .resource = r8a7740_dmae1_resources,
458 .num_resources = ARRAY_SIZE(r8a7740_dmae1_resources),
460 .platform_data = &dma_platform_data,
464 static struct platform_device dma2_device = {
465 .name = "sh-dma-engine",
467 .resource = r8a7740_dmae2_resources,
468 .num_resources = ARRAY_SIZE(r8a7740_dmae2_resources),
470 .platform_data = &dma_platform_data,
475 static const struct sh_dmae_channel r8a7740_usb_dma_channels[] = {
483 static const struct sh_dmae_slave_config r8a7740_usb_dma_slaves[] = {
485 .slave_id = SHDMA_SLAVE_USBHS_TX,
486 .chcr = USBTS_INDEX2VAL(USBTS_XMIT_SZ_8BYTE),
488 .slave_id = SHDMA_SLAVE_USBHS_RX,
489 .chcr = USBTS_INDEX2VAL(USBTS_XMIT_SZ_8BYTE),
493 static struct sh_dmae_pdata usb_dma_platform_data = {
494 .slave = r8a7740_usb_dma_slaves,
495 .slave_num = ARRAY_SIZE(r8a7740_usb_dma_slaves),
496 .channel = r8a7740_usb_dma_channels,
497 .channel_num = ARRAY_SIZE(r8a7740_usb_dma_channels),
498 .ts_low_shift = USBTS_LOW_SHIFT,
499 .ts_low_mask = USBTS_LOW_BIT << USBTS_LOW_SHIFT,
500 .ts_high_shift = USBTS_HI_SHIFT,
501 .ts_high_mask = USBTS_HI_BIT << USBTS_HI_SHIFT,
502 .ts_shift = dma_usbts_shift,
503 .ts_shift_num = ARRAY_SIZE(dma_usbts_shift),
504 .dmaor_init = DMAOR_DME,
506 .chcr_ie_bit = 1 << 5,
513 static struct resource r8a7740_usb_dma_resources[] = {
515 /* Channel registers and DMAOR */
517 .end = 0xe68a0064 - 1,
518 .flags = IORESOURCE_MEM,
523 .end = 0xe68a0014 - 1,
524 .flags = IORESOURCE_MEM,
527 /* IRQ for channels */
528 .start = evt2irq(0x0a00),
529 .end = evt2irq(0x0a00),
530 .flags = IORESOURCE_IRQ,
534 static struct platform_device usb_dma_device = {
535 .name = "sh-dma-engine",
537 .resource = r8a7740_usb_dma_resources,
538 .num_resources = ARRAY_SIZE(r8a7740_usb_dma_resources),
540 .platform_data = &usb_dma_platform_data,
545 static struct resource i2c0_resources[] = {
549 .end = 0xfff20425 - 1,
550 .flags = IORESOURCE_MEM,
553 .start = intcs_evt2irq(0xe00),
554 .end = intcs_evt2irq(0xe60),
555 .flags = IORESOURCE_IRQ,
559 static struct resource i2c1_resources[] = {
563 .end = 0xe6c20425 - 1,
564 .flags = IORESOURCE_MEM,
567 .start = evt2irq(0x780), /* IIC1_ALI1 */
568 .end = evt2irq(0x7e0), /* IIC1_DTEI1 */
569 .flags = IORESOURCE_IRQ,
573 static struct platform_device i2c0_device = {
574 .name = "i2c-sh_mobile",
576 .resource = i2c0_resources,
577 .num_resources = ARRAY_SIZE(i2c0_resources),
580 static struct platform_device i2c1_device = {
581 .name = "i2c-sh_mobile",
583 .resource = i2c1_resources,
584 .num_resources = ARRAY_SIZE(i2c1_resources),
587 static struct resource pmu_resources[] = {
589 .start = evt2irq(0x19a0),
590 .end = evt2irq(0x19a0),
591 .flags = IORESOURCE_IRQ,
595 static struct platform_device pmu_device = {
598 .num_resources = ARRAY_SIZE(pmu_resources),
599 .resource = pmu_resources,
602 static struct platform_device *r8a7740_late_devices[] __initdata = {
613 * r8a7740 chip has lasting errata on MERAM buffer.
614 * this is work-around for it.
616 * "Media RAM (MERAM)" on r8a7740 documentation
618 #define MEBUFCNTR 0xFE950098
619 void r8a7740_meram_workaround(void)
623 reg = ioremap_nocache(MEBUFCNTR, 4);
625 iowrite32(0x01600164, reg);
631 #define ICSTART 0x0070
633 #define i2c_read(reg, offset) ioread8(reg + offset)
634 #define i2c_write(reg, offset, data) iowrite8(data, reg + offset)
637 * r8a7740 chip has lasting errata on I2C I/O pad reset.
638 * this is work-around for it.
640 static void r8a7740_i2c_workaround(struct platform_device *pdev)
642 struct resource *res;
645 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
646 if (unlikely(!res)) {
647 pr_err("r8a7740 i2c workaround fail (cannot find resource)\n");
651 reg = ioremap(res->start, resource_size(res));
652 if (unlikely(!reg)) {
653 pr_err("r8a7740 i2c workaround fail (cannot map IO)\n");
657 i2c_write(reg, ICCR, i2c_read(reg, ICCR) | 0x80);
658 i2c_read(reg, ICCR); /* dummy read */
660 i2c_write(reg, ICSTART, i2c_read(reg, ICSTART) | 0x10);
661 i2c_read(reg, ICSTART); /* dummy read */
665 i2c_write(reg, ICCR, 0x01);
666 i2c_write(reg, ICSTART, 0x00);
670 i2c_write(reg, ICCR, 0x10);
672 i2c_write(reg, ICCR, 0x00);
674 i2c_write(reg, ICCR, 0x10);
680 void __init r8a7740_add_standard_devices(void)
682 /* I2C work-around */
683 r8a7740_i2c_workaround(&i2c0_device);
684 r8a7740_i2c_workaround(&i2c1_device);
686 r8a7740_init_pm_domains();
689 platform_add_devices(r8a7740_early_devices,
690 ARRAY_SIZE(r8a7740_early_devices));
691 platform_add_devices(r8a7740_late_devices,
692 ARRAY_SIZE(r8a7740_late_devices));
694 /* add devices to PM domain */
696 rmobile_add_device_to_domain("A3SP", &scif0_device);
697 rmobile_add_device_to_domain("A3SP", &scif1_device);
698 rmobile_add_device_to_domain("A3SP", &scif2_device);
699 rmobile_add_device_to_domain("A3SP", &scif3_device);
700 rmobile_add_device_to_domain("A3SP", &scif4_device);
701 rmobile_add_device_to_domain("A3SP", &scif5_device);
702 rmobile_add_device_to_domain("A3SP", &scif6_device);
703 rmobile_add_device_to_domain("A3SP", &scif7_device);
704 rmobile_add_device_to_domain("A3SP", &scifb_device);
705 rmobile_add_device_to_domain("A3SP", &i2c1_device);
708 static void __init r8a7740_earlytimer_init(void)
710 r8a7740_clock_init(0);
711 shmobile_earlytimer_init();
714 void __init r8a7740_add_early_devices(void)
716 early_platform_add_devices(r8a7740_early_devices,
717 ARRAY_SIZE(r8a7740_early_devices));
719 /* setup early console here as well */
720 shmobile_setup_console();
722 /* override timer setup with soc-specific code */
723 shmobile_timer.init = r8a7740_earlytimer_init;
728 void __init r8a7740_add_early_devices_dt(void)
730 shmobile_setup_delay(800, 1, 3); /* Cortex-A9 @ 800MHz */
732 early_platform_add_devices(r8a7740_early_devices,
733 ARRAY_SIZE(r8a7740_early_devices));
735 /* setup early console here as well */
736 shmobile_setup_console();
739 static const struct of_dev_auxdata r8a7740_auxdata_lookup[] __initconst = {
743 void __init r8a7740_add_standard_devices_dt(void)
745 /* clocks are setup late during boot in the case of DT */
746 r8a7740_clock_init(0);
748 platform_add_devices(r8a7740_early_devices,
749 ARRAY_SIZE(r8a7740_early_devices));
751 of_platform_populate(NULL, of_default_bus_match_table,
752 r8a7740_auxdata_lookup, NULL);
755 static const char *r8a7740_boards_compat_dt[] __initdata = {
760 DT_MACHINE_START(R8A7740_DT, "Generic R8A7740 (Flattened Device Tree)")
761 .map_io = r8a7740_map_io,
762 .init_early = r8a7740_add_early_devices_dt,
763 .init_irq = r8a7740_init_irq,
764 .handle_irq = shmobile_handle_irq_intc,
765 .init_machine = r8a7740_add_standard_devices_dt,
766 .timer = &shmobile_timer,
767 .dt_compat = r8a7740_boards_compat_dt,
770 #endif /* CONFIG_USE_OF */