2 * linux/arch/arm/mach-sa1100/assabet.c
4 * Author: Nicolas Pitre
6 * This file contains all Assabet-specific tweaks.
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
12 #include <linux/init.h>
13 #include <linux/kernel.h>
14 #include <linux/module.h>
15 #include <linux/errno.h>
16 #include <linux/ioport.h>
17 #include <linux/serial_core.h>
18 #include <linux/mtd/mtd.h>
19 #include <linux/mtd/partitions.h>
20 #include <linux/delay.h>
23 #include <video/sa1100fb.h>
25 #include <mach/hardware.h>
26 #include <asm/mach-types.h>
28 #include <asm/setup.h>
30 #include <asm/pgtable-hwdef.h>
31 #include <asm/pgtable.h>
32 #include <asm/tlbflush.h>
34 #include <asm/mach/arch.h>
35 #include <asm/mach/flash.h>
36 #include <asm/mach/irda.h>
37 #include <asm/mach/map.h>
38 #include <asm/mach/serial_sa1100.h>
39 #include <mach/assabet.h>
44 #define ASSABET_BCR_DB1110 \
45 (ASSABET_BCR_SPK_OFF | \
46 ASSABET_BCR_LED_GREEN | ASSABET_BCR_LED_RED | \
47 ASSABET_BCR_RS232EN | ASSABET_BCR_LCD_12RGB | \
50 #define ASSABET_BCR_DB1111 \
51 (ASSABET_BCR_SPK_OFF | \
52 ASSABET_BCR_LED_GREEN | ASSABET_BCR_LED_RED | \
53 ASSABET_BCR_RS232EN | ASSABET_BCR_LCD_12RGB | \
54 ASSABET_BCR_CF_BUS_OFF | ASSABET_BCR_STEREO_LB | \
55 ASSABET_BCR_IRDA_MD0 | ASSABET_BCR_CF_RST)
57 unsigned long SCR_value = ASSABET_SCR_INIT;
58 EXPORT_SYMBOL(SCR_value);
60 static unsigned long BCR_value = ASSABET_BCR_DB1110;
62 void ASSABET_BCR_frob(unsigned int mask, unsigned int val)
66 local_irq_save(flags);
67 BCR_value = (BCR_value & ~mask) | val;
68 ASSABET_BCR = BCR_value;
69 local_irq_restore(flags);
72 EXPORT_SYMBOL(ASSABET_BCR_frob);
76 * Assabet flash support code.
81 * Phase 4 Assabet has two 28F160B3 flash parts in bank 0:
83 static struct mtd_partition assabet_partitions[] = {
88 .mask_flags = MTD_WRITEABLE,
90 .name = "bootloader params",
92 .offset = MTDPART_OFS_APPEND,
93 .mask_flags = MTD_WRITEABLE,
96 .size = MTDPART_SIZ_FULL,
97 .offset = MTDPART_OFS_APPEND,
102 * Phase 5 Assabet has two 28F128J3A flash parts in bank 0:
104 static struct mtd_partition assabet_partitions[] = {
106 .name = "bootloader",
109 .mask_flags = MTD_WRITEABLE,
111 .name = "bootloader params",
113 .offset = MTDPART_OFS_APPEND,
114 .mask_flags = MTD_WRITEABLE,
117 .size = MTDPART_SIZ_FULL,
118 .offset = MTDPART_OFS_APPEND,
123 static struct flash_platform_data assabet_flash_data = {
124 .map_name = "cfi_probe",
125 .parts = assabet_partitions,
126 .nr_parts = ARRAY_SIZE(assabet_partitions),
129 static struct resource assabet_flash_resources[] = {
130 DEFINE_RES_MEM(SA1100_CS0_PHYS, SZ_32M),
131 DEFINE_RES_MEM(SA1100_CS1_PHYS, SZ_32M),
136 * Assabet IrDA support code.
139 static int assabet_irda_set_power(struct device *dev, unsigned int state)
141 static unsigned int bcr_state[4] = {
142 ASSABET_BCR_IRDA_MD0,
143 ASSABET_BCR_IRDA_MD1|ASSABET_BCR_IRDA_MD0,
144 ASSABET_BCR_IRDA_MD1,
149 state = bcr_state[state];
150 ASSABET_BCR_clear(state ^ (ASSABET_BCR_IRDA_MD1|
151 ASSABET_BCR_IRDA_MD0));
152 ASSABET_BCR_set(state);
157 static void assabet_irda_set_speed(struct device *dev, unsigned int speed)
160 ASSABET_BCR_clear(ASSABET_BCR_IRDA_FSEL);
162 ASSABET_BCR_set(ASSABET_BCR_IRDA_FSEL);
165 static struct irda_platform_data assabet_irda_data = {
166 .set_power = assabet_irda_set_power,
167 .set_speed = assabet_irda_set_speed,
170 static struct mcp_plat_data assabet_mcp_data = {
172 .sclk_rate = 11981000,
175 static void assabet_lcd_set_visual(u32 visual)
177 u_int is_true_color = visual == FB_VISUAL_TRUECOLOR;
179 if (machine_is_assabet()) {
180 #if 1 // phase 4 or newer Assabet's
182 ASSABET_BCR_set(ASSABET_BCR_LCD_12RGB);
184 ASSABET_BCR_clear(ASSABET_BCR_LCD_12RGB);
188 ASSABET_BCR_clear(ASSABET_BCR_LCD_12RGB);
190 ASSABET_BCR_set(ASSABET_BCR_LCD_12RGB);
195 #ifndef ASSABET_PAL_VIDEO
196 static void assabet_lcd_backlight_power(int on)
199 ASSABET_BCR_set(ASSABET_BCR_LIGHT_ON);
201 ASSABET_BCR_clear(ASSABET_BCR_LIGHT_ON);
205 * Turn on/off the backlight. When turning the backlight on, we wait
206 * 500us after turning it on so we don't cause the supplies to droop
207 * when we enable the LCD controller (and cause a hard reset.)
209 static void assabet_lcd_power(int on)
212 ASSABET_BCR_set(ASSABET_BCR_LCD_ON);
215 ASSABET_BCR_clear(ASSABET_BCR_LCD_ON);
219 * The assabet uses a sharp LQ039Q2DS54 LCD module. It is actually
220 * takes an RGB666 signal, but we provide it with an RGB565 signal
221 * instead (def_rgb_16).
223 static struct sa1100fb_mach_info lq039q2ds54_info = {
224 .pixclock = 171521, .bpp = 16,
225 .xres = 320, .yres = 240,
227 .hsync_len = 5, .vsync_len = 1,
228 .left_margin = 61, .upper_margin = 3,
229 .right_margin = 9, .lower_margin = 0,
231 .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
233 .lccr0 = LCCR0_Color | LCCR0_Sngl | LCCR0_Act,
234 .lccr3 = LCCR3_OutEnH | LCCR3_PixRsEdg | LCCR3_ACBsDiv(2),
236 .backlight_power = assabet_lcd_backlight_power,
237 .lcd_power = assabet_lcd_power,
238 .set_visual = assabet_lcd_set_visual,
241 static void assabet_pal_backlight_power(int on)
243 ASSABET_BCR_clear(ASSABET_BCR_LIGHT_ON);
246 static void assabet_pal_power(int on)
248 ASSABET_BCR_clear(ASSABET_BCR_LCD_ON);
251 static struct sa1100fb_mach_info pal_info = {
252 .pixclock = 67797, .bpp = 16,
253 .xres = 640, .yres = 512,
255 .hsync_len = 64, .vsync_len = 6,
256 .left_margin = 125, .upper_margin = 70,
257 .right_margin = 115, .lower_margin = 36,
259 .lccr0 = LCCR0_Color | LCCR0_Sngl | LCCR0_Act,
260 .lccr3 = LCCR3_OutEnH | LCCR3_PixRsEdg | LCCR3_ACBsDiv(512),
262 .backlight_power = assabet_pal_backlight_power,
263 .lcd_power = assabet_pal_power,
264 .set_visual = assabet_lcd_set_visual,
268 #ifdef CONFIG_ASSABET_NEPONSET
269 static struct resource neponset_resources[] = {
270 DEFINE_RES_MEM(0x10000000, 0x08000000),
271 DEFINE_RES_MEM(0x18000000, 0x04000000),
272 DEFINE_RES_MEM(0x40000000, SZ_8K),
273 DEFINE_RES_IRQ(IRQ_GPIO25),
277 static void __init assabet_init(void)
280 * Ensure that the power supply is in "high power" mode.
286 * Ensure that these pins are set as outputs and are driving
287 * logic 0. This ensures that we won't inadvertently toggle
288 * the WS latch in the CPLD, and we don't float causing
289 * excessive power drain. --rmk
291 GPCR = GPIO_SSP_TXD | GPIO_SSP_SCLK | GPIO_SSP_SFRM;
292 GPDR |= GPIO_SSP_TXD | GPIO_SSP_SCLK | GPIO_SSP_SFRM;
295 * Also set GPIO27 as an output; this is used to clock UART3
296 * via the FPGA and as otherwise has no pullups or pulldowns,
297 * so stop it floating.
303 * Set up registers for sleep mode.
309 PPDR |= PPC_TXD3 | PPC_TXD1;
310 PPSR |= PPC_TXD3 | PPC_TXD1;
312 if (machine_has_neponset()) {
314 * Angel sets this, but other bootloaders may not.
316 * This must precede any driver calls to BCR_set()
319 ASSABET_BCR = BCR_value = ASSABET_BCR_DB1111;
321 #ifndef CONFIG_ASSABET_NEPONSET
322 printk( "Warning: Neponset detected but full support "
323 "hasn't been configured in the kernel\n" );
325 platform_device_register_simple("neponset", 0,
326 neponset_resources, ARRAY_SIZE(neponset_resources));
330 #ifndef ASSABET_PAL_VIDEO
331 sa11x0_register_lcd(&lq039q2ds54_info);
333 sa11x0_register_lcd(&pal_video);
335 sa11x0_register_mtd(&assabet_flash_data, assabet_flash_resources,
336 ARRAY_SIZE(assabet_flash_resources));
337 sa11x0_register_irda(&assabet_irda_data);
338 sa11x0_register_mcp(&assabet_mcp_data);
342 * On Assabet, we must probe for the Neponset board _before_
343 * paging_init() has occurred to actually determine the amount
344 * of RAM available. To do so, we map the appropriate IO section
345 * in the page table here in order to access GPIO registers.
347 static void __init map_sa1100_gpio_regs( void )
349 unsigned long phys = __PREG(GPLR) & PMD_MASK;
350 unsigned long virt = io_p2v(phys);
351 int prot = PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_DOMAIN(DOMAIN_IO);
354 pmd = pmd_offset(pud_offset(pgd_offset_k(virt), virt), virt);
355 *pmd = __pmd(phys | prot);
356 flush_pmd_entry(pmd);
360 * Read System Configuration "Register"
361 * (taken from "Intel StrongARM SA-1110 Microprocessor Development Board
362 * User's Guide", section 4.4.1)
364 * This same scan is performed in arch/arm/boot/compressed/head-sa1100.S
365 * to set up the serial port for decompression status messages. We
366 * repeat it here because the kernel may not be loaded as a zImage, and
367 * also because it's a hassle to communicate the SCR value to the kernel
368 * from the decompressor.
370 * Note that IRQs are guaranteed to be disabled.
372 static void __init get_assabet_scr(void)
374 unsigned long scr, i;
376 GPDR |= 0x3fc; /* Configure GPIO 9:2 as outputs */
377 GPSR = 0x3fc; /* Write 0xFF to GPIO 9:2 */
378 GPDR &= ~(0x3fc); /* Configure GPIO 9:2 as inputs */
379 for(i = 100; i--; ) /* Read GPIO 9:2 */
381 GPDR |= 0x3fc; /* restore correct pin direction */
382 scr &= 0x3fc; /* save as system configuration byte. */
387 fixup_assabet(struct tag *tags, char **cmdline, struct meminfo *mi)
389 /* This must be done before any call to machine_has_neponset() */
390 map_sa1100_gpio_regs();
393 if (machine_has_neponset())
394 printk("Neponset expansion board detected\n");
398 static void assabet_uart_pm(struct uart_port *port, u_int state, u_int oldstate)
400 if (port->mapbase == _Ser1UTCR0) {
402 ASSABET_BCR_clear(ASSABET_BCR_RS232EN |
403 ASSABET_BCR_COM_RTS |
404 ASSABET_BCR_COM_DTR);
406 ASSABET_BCR_set(ASSABET_BCR_RS232EN |
407 ASSABET_BCR_COM_RTS |
408 ASSABET_BCR_COM_DTR);
413 * Assabet uses COM_RTS and COM_DTR for both UART1 (com port)
414 * and UART3 (radio module). We only handle them for UART1 here.
416 static void assabet_set_mctrl(struct uart_port *port, u_int mctrl)
418 if (port->mapbase == _Ser1UTCR0) {
419 u_int set = 0, clear = 0;
421 if (mctrl & TIOCM_RTS)
422 clear |= ASSABET_BCR_COM_RTS;
424 set |= ASSABET_BCR_COM_RTS;
426 if (mctrl & TIOCM_DTR)
427 clear |= ASSABET_BCR_COM_DTR;
429 set |= ASSABET_BCR_COM_DTR;
431 ASSABET_BCR_clear(clear);
432 ASSABET_BCR_set(set);
436 static u_int assabet_get_mctrl(struct uart_port *port)
439 u_int bsr = ASSABET_BSR;
441 /* need 2 reads to read current value */
444 if (port->mapbase == _Ser1UTCR0) {
445 if (bsr & ASSABET_BSR_COM_DCD)
447 if (bsr & ASSABET_BSR_COM_CTS)
449 if (bsr & ASSABET_BSR_COM_DSR)
451 } else if (port->mapbase == _Ser3UTCR0) {
452 if (bsr & ASSABET_BSR_RAD_DCD)
454 if (bsr & ASSABET_BSR_RAD_CTS)
456 if (bsr & ASSABET_BSR_RAD_DSR)
458 if (bsr & ASSABET_BSR_RAD_RI)
461 ret = TIOCM_CD | TIOCM_CTS | TIOCM_DSR;
467 static struct sa1100_port_fns assabet_port_fns __initdata = {
468 .set_mctrl = assabet_set_mctrl,
469 .get_mctrl = assabet_get_mctrl,
470 .pm = assabet_uart_pm,
473 static struct map_desc assabet_io_desc[] __initdata = {
474 { /* Board Control Register */
475 .virtual = 0xf1000000,
476 .pfn = __phys_to_pfn(0x12000000),
477 .length = 0x00100000,
480 .virtual = 0xf2800000,
481 .pfn = __phys_to_pfn(0x4b800000),
482 .length = 0x00800000,
487 static void __init assabet_map_io(void)
490 iotable_init(assabet_io_desc, ARRAY_SIZE(assabet_io_desc));
493 * Set SUS bit in SDCR0 so serial port 1 functions.
494 * Its called GPCLKR0 in my SA1110 manual.
496 Ser1SDCR0 |= SDCR0_SUS;
498 if (!machine_has_neponset())
499 sa1100_register_uart_fns(&assabet_port_fns);
502 * When Neponset is attached, the first UART should be
503 * UART3. That's what Angel is doing and many documents
506 * We do the Neponset mapping even if Neponset support
507 * isn't compiled in so the user will still get something on
508 * the expected physical serial port.
510 * We no longer do this; not all boot loaders support it,
511 * and UART3 appears to be somewhat unreliable with blob.
513 sa1100_register_uart(0, 1);
514 sa1100_register_uart(2, 3);
518 MACHINE_START(ASSABET, "Intel-Assabet")
519 .atag_offset = 0x100,
520 .fixup = fixup_assabet,
521 .map_io = assabet_map_io,
522 .init_irq = sa1100_init_irq,
523 .timer = &sa1100_timer,
524 .init_machine = assabet_init,
526 .dma_zone_size = SZ_1M,
528 .restart = sa11x0_restart,