1 /* linux/arch/arm/mach-s5p64x0/gpiolib.c
3 * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
6 * S5P64X0 - GPIOlib support
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
13 #include <linux/kernel.h>
14 #include <linux/irq.h>
16 #include <linux/gpio.h>
19 #include <mach/regs-gpio.h>
20 #include <mach/regs-clock.h>
23 #include <plat/gpio-core.h>
24 #include <plat/gpio-cfg.h>
25 #include <plat/gpio-cfg-helpers.h>
28 * S5P6440 GPIO bank summary:
30 * Bank GPIOs Style SlpCon ExtInt Group
39 * N 16 2Bit No IRQ_EINT
43 * S5P6450 GPIO bank summary:
45 * Bank GPIOs Style SlpCon ExtInt Group
56 * N 16 2Bit No IRQ_EINT
59 * R 15 4Bit[2] Yes None
62 * [1] BANKF pins 14,15 do not form part of the external interrupt sources
63 * [2] BANK has two control registers, GPxCON0 and GPxCON1
66 static int s5p64x0_gpiolib_rbank_4bit2_input(struct gpio_chip *chip,
69 struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip);
70 void __iomem *base = ourchip->base;
71 void __iomem *regcon = base;
91 s3c_gpio_lock(ourchip, flags);
93 con = __raw_readl(regcon);
94 con &= ~(0xf << con_4bit_shift(offset));
95 __raw_writel(con, regcon);
97 s3c_gpio_unlock(ourchip, flags);
102 static int s5p64x0_gpiolib_rbank_4bit2_output(struct gpio_chip *chip,
103 unsigned int offset, int value)
105 struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip);
106 void __iomem *base = ourchip->base;
107 void __iomem *regcon = base;
111 unsigned con_offset = offset;
113 switch (con_offset) {
129 s3c_gpio_lock(ourchip, flags);
131 con = __raw_readl(regcon);
132 con &= ~(0xf << con_4bit_shift(con_offset));
133 con |= 0x1 << con_4bit_shift(con_offset);
135 dat = __raw_readl(base + GPIODAT_OFF);
139 dat &= ~(1 << offset);
141 __raw_writel(con, regcon);
142 __raw_writel(dat, base + GPIODAT_OFF);
144 s3c_gpio_unlock(ourchip, flags);
149 int s5p64x0_gpio_setcfg_4bit_rbank(struct s3c_gpio_chip *chip,
150 unsigned int off, unsigned int cfg)
152 void __iomem *reg = chip->base;
163 shift = (off & 7) * 4;
167 shift = ((off + 1) & 7) * 4;
170 shift = ((off + 1) & 7) * 4;
174 if (s3c_gpio_is_cfg_special(cfg)) {
179 con = __raw_readl(reg);
180 con &= ~(0xf << shift);
182 __raw_writel(con, reg);
187 static struct s3c_gpio_cfg s5p64x0_gpio_cfgs[] = {
194 .set_config = s5p64x0_gpio_setcfg_4bit_rbank,
197 .set_config = s3c_gpio_setcfg_s3c24xx,
198 .get_config = s3c_gpio_getcfg_s3c24xx,
201 .set_config = s3c_gpio_setcfg_s3c24xx,
202 .get_config = s3c_gpio_getcfg_s3c24xx,
205 .set_config = s3c_gpio_setcfg_s3c24xx,
206 .get_config = s3c_gpio_getcfg_s3c24xx,
210 static struct s3c_gpio_chip s5p6440_gpio_4bit[] = {
212 .base = S5P64X0_GPA_BASE,
213 .config = &s5p64x0_gpio_cfgs[1],
215 .base = S5P6440_GPA(0),
216 .ngpio = S5P6440_GPIO_A_NR,
220 .base = S5P64X0_GPB_BASE,
221 .config = &s5p64x0_gpio_cfgs[1],
223 .base = S5P6440_GPB(0),
224 .ngpio = S5P6440_GPIO_B_NR,
228 .base = S5P64X0_GPC_BASE,
229 .config = &s5p64x0_gpio_cfgs[1],
231 .base = S5P6440_GPC(0),
232 .ngpio = S5P6440_GPIO_C_NR,
236 .base = S5P64X0_GPG_BASE,
237 .config = &s5p64x0_gpio_cfgs[1],
239 .base = S5P6440_GPG(0),
240 .ngpio = S5P6440_GPIO_G_NR,
246 static struct s3c_gpio_chip s5p6440_gpio_4bit2[] = {
248 .base = S5P64X0_GPH_BASE + 0x4,
249 .config = &s5p64x0_gpio_cfgs[1],
251 .base = S5P6440_GPH(0),
252 .ngpio = S5P6440_GPIO_H_NR,
258 static struct s3c_gpio_chip s5p6440_gpio_rbank_4bit2[] = {
260 .base = S5P64X0_GPR_BASE + 0x4,
261 .config = &s5p64x0_gpio_cfgs[2],
263 .base = S5P6440_GPR(0),
264 .ngpio = S5P6440_GPIO_R_NR,
270 static struct s3c_gpio_chip s5p6440_gpio_2bit[] = {
272 .base = S5P64X0_GPF_BASE,
273 .config = &s5p64x0_gpio_cfgs[5],
275 .base = S5P6440_GPF(0),
276 .ngpio = S5P6440_GPIO_F_NR,
280 .base = S5P64X0_GPI_BASE,
281 .config = &s5p64x0_gpio_cfgs[3],
283 .base = S5P6440_GPI(0),
284 .ngpio = S5P6440_GPIO_I_NR,
288 .base = S5P64X0_GPJ_BASE,
289 .config = &s5p64x0_gpio_cfgs[3],
291 .base = S5P6440_GPJ(0),
292 .ngpio = S5P6440_GPIO_J_NR,
296 .base = S5P64X0_GPN_BASE,
297 .config = &s5p64x0_gpio_cfgs[4],
299 .base = S5P6440_GPN(0),
300 .ngpio = S5P6440_GPIO_N_NR,
304 .base = S5P64X0_GPP_BASE,
305 .config = &s5p64x0_gpio_cfgs[5],
307 .base = S5P6440_GPP(0),
308 .ngpio = S5P6440_GPIO_P_NR,
314 static struct s3c_gpio_chip s5p6450_gpio_4bit[] = {
316 .base = S5P64X0_GPA_BASE,
317 .config = &s5p64x0_gpio_cfgs[1],
319 .base = S5P6450_GPA(0),
320 .ngpio = S5P6450_GPIO_A_NR,
324 .base = S5P64X0_GPB_BASE,
325 .config = &s5p64x0_gpio_cfgs[1],
327 .base = S5P6450_GPB(0),
328 .ngpio = S5P6450_GPIO_B_NR,
332 .base = S5P64X0_GPC_BASE,
333 .config = &s5p64x0_gpio_cfgs[1],
335 .base = S5P6450_GPC(0),
336 .ngpio = S5P6450_GPIO_C_NR,
340 .base = S5P6450_GPD_BASE,
341 .config = &s5p64x0_gpio_cfgs[1],
343 .base = S5P6450_GPD(0),
344 .ngpio = S5P6450_GPIO_D_NR,
348 .base = S5P6450_GPK_BASE,
349 .config = &s5p64x0_gpio_cfgs[1],
351 .base = S5P6450_GPK(0),
352 .ngpio = S5P6450_GPIO_K_NR,
358 static struct s3c_gpio_chip s5p6450_gpio_4bit2[] = {
360 .base = S5P64X0_GPG_BASE + 0x4,
361 .config = &s5p64x0_gpio_cfgs[1],
363 .base = S5P6450_GPG(0),
364 .ngpio = S5P6450_GPIO_G_NR,
368 .base = S5P64X0_GPH_BASE + 0x4,
369 .config = &s5p64x0_gpio_cfgs[1],
371 .base = S5P6450_GPH(0),
372 .ngpio = S5P6450_GPIO_H_NR,
378 static struct s3c_gpio_chip s5p6450_gpio_rbank_4bit2[] = {
380 .base = S5P64X0_GPR_BASE + 0x4,
381 .config = &s5p64x0_gpio_cfgs[2],
383 .base = S5P6450_GPR(0),
384 .ngpio = S5P6450_GPIO_R_NR,
390 static struct s3c_gpio_chip s5p6450_gpio_2bit[] = {
392 .base = S5P64X0_GPF_BASE,
393 .config = &s5p64x0_gpio_cfgs[5],
395 .base = S5P6450_GPF(0),
396 .ngpio = S5P6450_GPIO_F_NR,
400 .base = S5P64X0_GPI_BASE,
401 .config = &s5p64x0_gpio_cfgs[3],
403 .base = S5P6450_GPI(0),
404 .ngpio = S5P6450_GPIO_I_NR,
408 .base = S5P64X0_GPJ_BASE,
409 .config = &s5p64x0_gpio_cfgs[3],
411 .base = S5P6450_GPJ(0),
412 .ngpio = S5P6450_GPIO_J_NR,
416 .base = S5P64X0_GPN_BASE,
417 .config = &s5p64x0_gpio_cfgs[4],
419 .base = S5P6450_GPN(0),
420 .ngpio = S5P6450_GPIO_N_NR,
424 .base = S5P64X0_GPP_BASE,
425 .config = &s5p64x0_gpio_cfgs[5],
427 .base = S5P6450_GPP(0),
428 .ngpio = S5P6450_GPIO_P_NR,
432 .base = S5P6450_GPQ_BASE,
433 .config = &s5p64x0_gpio_cfgs[4],
435 .base = S5P6450_GPQ(0),
436 .ngpio = S5P6450_GPIO_Q_NR,
440 .base = S5P6450_GPS_BASE,
441 .config = &s5p64x0_gpio_cfgs[5],
443 .base = S5P6450_GPS(0),
444 .ngpio = S5P6450_GPIO_S_NR,
450 void __init s5p64x0_gpiolib_set_cfg(struct s3c_gpio_cfg *chipcfg, int nr_chips)
452 for (; nr_chips > 0; nr_chips--, chipcfg++) {
453 if (!chipcfg->set_config)
454 chipcfg->set_config = s3c_gpio_setcfg_s3c64xx_4bit;
455 if (!chipcfg->get_config)
456 chipcfg->get_config = s3c_gpio_getcfg_s3c64xx_4bit;
457 if (!chipcfg->set_pull)
458 chipcfg->set_pull = s3c_gpio_setpull_updown;
459 if (!chipcfg->get_pull)
460 chipcfg->get_pull = s3c_gpio_getpull_updown;
464 static void __init s5p64x0_gpio_add_rbank_4bit2(struct s3c_gpio_chip *chip,
467 for (; nr_chips > 0; nr_chips--, chip++) {
468 chip->chip.direction_input = s5p64x0_gpiolib_rbank_4bit2_input;
469 chip->chip.direction_output =
470 s5p64x0_gpiolib_rbank_4bit2_output;
471 s3c_gpiolib_add(chip);
475 static int __init s5p64x0_gpiolib_init(void)
477 s5p64x0_gpiolib_set_cfg(s5p64x0_gpio_cfgs,
478 ARRAY_SIZE(s5p64x0_gpio_cfgs));
480 if (soc_is_s5p6450()) {
481 samsung_gpiolib_add_2bit_chips(s5p6450_gpio_2bit,
482 ARRAY_SIZE(s5p6450_gpio_2bit));
484 samsung_gpiolib_add_4bit_chips(s5p6450_gpio_4bit,
485 ARRAY_SIZE(s5p6450_gpio_4bit));
487 samsung_gpiolib_add_4bit2_chips(s5p6450_gpio_4bit2,
488 ARRAY_SIZE(s5p6450_gpio_4bit2));
490 s5p64x0_gpio_add_rbank_4bit2(s5p6450_gpio_rbank_4bit2,
491 ARRAY_SIZE(s5p6450_gpio_rbank_4bit2));
493 samsung_gpiolib_add_2bit_chips(s5p6440_gpio_2bit,
494 ARRAY_SIZE(s5p6440_gpio_2bit));
496 samsung_gpiolib_add_4bit_chips(s5p6440_gpio_4bit,
497 ARRAY_SIZE(s5p6440_gpio_4bit));
499 samsung_gpiolib_add_4bit2_chips(s5p6440_gpio_4bit2,
500 ARRAY_SIZE(s5p6440_gpio_4bit2));
502 s5p64x0_gpio_add_rbank_4bit2(s5p6440_gpio_rbank_4bit2,
503 ARRAY_SIZE(s5p6440_gpio_rbank_4bit2));
508 core_initcall(s5p64x0_gpiolib_init);