1 /* linux/arch/arm/mach-s5p64x0/gpio.c
3 * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
6 * S5P64X0 - GPIOlib support
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
13 #include <linux/kernel.h>
14 #include <linux/irq.h>
16 #include <linux/gpio.h>
19 #include <mach/regs-gpio.h>
21 #include <plat/gpio-core.h>
22 #include <plat/gpio-cfg.h>
23 #include <plat/gpio-cfg-helpers.h>
25 /* To be implemented S5P6450 GPIO */
28 * S5P6440 GPIO bank summary:
30 * Bank GPIOs Style SlpCon ExtInt Group
39 * N 16 2Bit No IRQ_EINT
43 * [1] BANKF pins 14,15 do not form part of the external interrupt sources
44 * [2] BANK has two control registers, GPxCON0 and GPxCON1
47 static int s5p64x0_gpiolib_rbank_4bit2_input(struct gpio_chip *chip,
50 struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip);
51 void __iomem *base = ourchip->base;
52 void __iomem *regcon = base;
72 s3c_gpio_lock(ourchip, flags);
74 con = __raw_readl(regcon);
75 con &= ~(0xf << con_4bit_shift(offset));
76 __raw_writel(con, regcon);
78 s3c_gpio_unlock(ourchip, flags);
83 static int s5p64x0_gpiolib_rbank_4bit2_output(struct gpio_chip *chip,
84 unsigned int offset, int value)
86 struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip);
87 void __iomem *base = ourchip->base;
88 void __iomem *regcon = base;
92 unsigned con_offset = offset;
110 s3c_gpio_lock(ourchip, flags);
112 con = __raw_readl(regcon);
113 con &= ~(0xf << con_4bit_shift(con_offset));
114 con |= 0x1 << con_4bit_shift(con_offset);
116 dat = __raw_readl(base + GPIODAT_OFF);
120 dat &= ~(1 << offset);
122 __raw_writel(con, regcon);
123 __raw_writel(dat, base + GPIODAT_OFF);
125 s3c_gpio_unlock(ourchip, flags);
130 int s5p64x0_gpio_setcfg_4bit_rbank(struct s3c_gpio_chip *chip,
131 unsigned int off, unsigned int cfg)
133 void __iomem *reg = chip->base;
144 shift = (off & 7) * 4;
148 shift = ((off + 1) & 7) * 4;
151 shift = ((off + 1) & 7) * 4;
155 if (s3c_gpio_is_cfg_special(cfg)) {
160 con = __raw_readl(reg);
161 con &= ~(0xf << shift);
163 __raw_writel(con, reg);
168 static struct s3c_gpio_cfg s5p64x0_gpio_cfgs[] = {
175 .set_config = s5p64x0_gpio_setcfg_4bit_rbank,
178 .set_config = s3c_gpio_setcfg_s3c24xx,
179 .get_config = s3c_gpio_getcfg_s3c24xx,
182 .set_config = s3c_gpio_setcfg_s3c24xx,
183 .get_config = s3c_gpio_getcfg_s3c24xx,
186 .set_config = s3c_gpio_setcfg_s3c24xx,
187 .get_config = s3c_gpio_getcfg_s3c24xx,
191 static struct s3c_gpio_chip s5p6440_gpio_4bit[] = {
193 .base = S5P6440_GPA_BASE,
194 .config = &s5p64x0_gpio_cfgs[1],
196 .base = S5P6440_GPA(0),
197 .ngpio = S5P6440_GPIO_A_NR,
201 .base = S5P6440_GPB_BASE,
202 .config = &s5p64x0_gpio_cfgs[1],
204 .base = S5P6440_GPB(0),
205 .ngpio = S5P6440_GPIO_B_NR,
209 .base = S5P6440_GPC_BASE,
210 .config = &s5p64x0_gpio_cfgs[1],
212 .base = S5P6440_GPC(0),
213 .ngpio = S5P6440_GPIO_C_NR,
217 .base = S5P6440_GPG_BASE,
218 .config = &s5p64x0_gpio_cfgs[1],
220 .base = S5P6440_GPG(0),
221 .ngpio = S5P6440_GPIO_G_NR,
227 static struct s3c_gpio_chip s5p6440_gpio_4bit2[] = {
229 .base = S5P6440_GPH_BASE + 0x4,
230 .config = &s5p64x0_gpio_cfgs[1],
232 .base = S5P6440_GPH(0),
233 .ngpio = S5P6440_GPIO_H_NR,
239 static struct s3c_gpio_chip s5p6440_gpio_rbank_4bit2[] = {
241 .base = S5P6440_GPR_BASE + 0x4,
242 .config = &s5p64x0_gpio_cfgs[2],
244 .base = S5P6440_GPR(0),
245 .ngpio = S5P6440_GPIO_R_NR,
251 static struct s3c_gpio_chip s5p6440_gpio_2bit[] = {
253 .base = S5P6440_GPF_BASE,
254 .config = &s5p64x0_gpio_cfgs[5],
256 .base = S5P6440_GPF(0),
257 .ngpio = S5P6440_GPIO_F_NR,
261 .base = S5P6440_GPI_BASE,
262 .config = &s5p64x0_gpio_cfgs[3],
264 .base = S5P6440_GPI(0),
265 .ngpio = S5P6440_GPIO_I_NR,
269 .base = S5P6440_GPJ_BASE,
270 .config = &s5p64x0_gpio_cfgs[3],
272 .base = S5P6440_GPJ(0),
273 .ngpio = S5P6440_GPIO_J_NR,
277 .base = S5P6440_GPN_BASE,
278 .config = &s5p64x0_gpio_cfgs[4],
280 .base = S5P6440_GPN(0),
281 .ngpio = S5P6440_GPIO_N_NR,
285 .base = S5P6440_GPP_BASE,
286 .config = &s5p64x0_gpio_cfgs[5],
288 .base = S5P6440_GPP(0),
289 .ngpio = S5P6440_GPIO_P_NR,
295 void __init s5p64x0_gpiolib_set_cfg(struct s3c_gpio_cfg *chipcfg, int nr_chips)
297 for (; nr_chips > 0; nr_chips--, chipcfg++) {
298 if (!chipcfg->set_config)
299 chipcfg->set_config = s3c_gpio_setcfg_s3c64xx_4bit;
300 if (!chipcfg->get_config)
301 chipcfg->get_config = s3c_gpio_getcfg_s3c64xx_4bit;
302 if (!chipcfg->set_pull)
303 chipcfg->set_pull = s3c_gpio_setpull_updown;
304 if (!chipcfg->get_pull)
305 chipcfg->get_pull = s3c_gpio_getpull_updown;
309 static void __init s5p64x0_gpio_add_rbank_4bit2(struct s3c_gpio_chip *chip,
312 for (; nr_chips > 0; nr_chips--, chip++) {
313 chip->chip.direction_input = s5p64x0_gpiolib_rbank_4bit2_input;
314 chip->chip.direction_output =
315 s5p64x0_gpiolib_rbank_4bit2_output;
316 s3c_gpiolib_add(chip);
320 static int __init s5p6440_gpiolib_init(void)
322 struct s3c_gpio_chip *chips = s5p6440_gpio_2bit;
323 int nr_chips = ARRAY_SIZE(s5p6440_gpio_2bit);
325 s5p64x0_gpiolib_set_cfg(s5p64x0_gpio_cfgs,
326 ARRAY_SIZE(s5p64x0_gpio_cfgs));
328 for (; nr_chips > 0; nr_chips--, chips++)
329 s3c_gpiolib_add(chips);
331 samsung_gpiolib_add_4bit_chips(s5p6440_gpio_4bit,
332 ARRAY_SIZE(s5p6440_gpio_4bit));
334 samsung_gpiolib_add_4bit2_chips(s5p6440_gpio_4bit2,
335 ARRAY_SIZE(s5p6440_gpio_4bit2));
337 s5p64x0_gpio_add_rbank_4bit2(s5p6440_gpio_rbank_4bit2,
338 ARRAY_SIZE(s5p6440_gpio_rbank_4bit2));
342 arch_initcall(s5p6440_gpiolib_init);